URL https://opencores.org/ocsvn/adv_debug_sys/adv_debug_sys/trunk

Subversion Repositories adv_debug_sys

[/] [adv_debug_sys/] [tags/] [ADS_RELEASE_2_5_0/] [Hardware/] [xilinx_internal_jtag/] [rtl/] [verilog/] [xilinx_internal_jtag_options.v] - Diff between revs 8 and 48

Rev 8	Rev 48


`// Xilinx has a different HDL entity for the internal JTAG in each of these.`	`// Xilinx has a different HDL entity for the internal JTAG in each of these.`
`// How thoughtful.`	`// How thoughtful.`

//`define SPARTAN2	//`define SPARTAN2
//`define SPARTAN3 // This is also used for SPARTAN 3E devices	//`define SPARTAN3 // This is also used for SPARTAN 3E devices
//`define SPARTAN3A	//`define SPARTAN3A
//`define VIRTEX	//`define VIRTEX
//`define VIRTEX2 // Also used for the VIRTEX 2P	//`define VIRTEX2 // Also used for the VIRTEX 2P
`define VIRTEX4	`define VIRTEX4