//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// cpu_behavioral.v ////
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//// cpu_behavioral.v ////
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//// ////
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//// ////
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//// ////
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//// ////
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//// This file is part of the SoC Debug Interface. ////
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//// This file is part of the SoC Debug Interface. ////
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//// http://www.opencores.org/projects/DebugInterface/ ////
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//// http://www.opencores.org/projects/DebugInterface/ ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// Igor Mohor (igorm@opencores.org) ////
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//// Igor Mohor (igorm@opencores.org) ////
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//// ////
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//// ////
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//// ////
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//// ////
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//// All additional information is avaliable in the README.txt ////
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//// All additional information is avaliable in the README.txt ////
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//// file. ////
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//// file. ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000 - 2004 Authors ////
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//// Copyright (C) 2000 - 2004 Authors ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: cpu_behavioral.v,v $
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// $Log: cpu_behavioral.v,v $
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// Revision 1.2 2010-01-08 01:41:08 Nathan
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// Removed unused, non-existant include from CPU behavioral model. Minor text edits.
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//
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// Revision 1.1 2008/07/08 19:11:55 Nathan
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// Revision 1.1 2008/07/08 19:11:55 Nathan
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// Added second testbench to simulate a complete system, including OR1200, wb_conbus, and onchipram. Renamed sim-only testbench directory from verilog to simulated_system.
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// Added second testbench to simulate a complete system, including OR1200, wb_conbus, and onchipram. Renamed sim-only testbench directory from verilog to simulated_system.
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//
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//
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// Revision 1.1 2008/06/18 18:34:48 Nathan
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// Revision 1.1 2008/06/18 18:34:48 Nathan
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// Initial working version. Only Wishbone module implemented. Simple testbench included, with CPU and Wishbone behavioral models from the old dbg_interface.
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// Initial working version. Only Wishbone module implemented. Simple testbench included, with CPU and Wishbone behavioral models from the old dbg_interface.
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//
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//
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// Revision 1.1.1.1 2008/05/14 12:07:35 Nathan
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// Revision 1.1.1.1 2008/05/14 12:07:35 Nathan
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// Original from OpenCores
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// Original from OpenCores
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//
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//
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// Revision 1.4 2004/03/28 20:27:40 igorm
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// Revision 1.4 2004/03/28 20:27:40 igorm
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// New release of the debug interface (3rd. release).
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// New release of the debug interface (3rd. release).
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//
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//
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// Revision 1.3 2004/01/22 11:07:28 mohor
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// Revision 1.3 2004/01/22 11:07:28 mohor
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// test stall_test added.
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// test stall_test added.
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//
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//
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// Revision 1.2 2004/01/17 18:01:31 mohor
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// Revision 1.2 2004/01/17 18:01:31 mohor
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// New version.
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// New version.
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//
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//
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// Revision 1.1 2004/01/17 17:01:25 mohor
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// Revision 1.1 2004/01/17 17:01:25 mohor
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// Almost finished.
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// Almost finished.
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//
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//
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//
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//
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//
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//
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//
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//
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//
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//
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`include "timescale.v"
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`include "timescale.v"
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`include "dbg_cpu_defines.v"
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module cpu_behavioral
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module cpu_behavioral
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(
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(
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// CPU signals
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// CPU signals
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cpu_rst_i,
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cpu_rst_i,
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cpu_clk_o,
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cpu_clk_o,
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cpu_addr_i,
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cpu_addr_i,
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cpu_data_o,
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cpu_data_o,
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cpu_data_i,
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cpu_data_i,
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cpu_bp_o,
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cpu_bp_o,
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cpu_stall_i,
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cpu_stall_i,
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cpu_stb_i,
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cpu_stb_i,
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cpu_we_i,
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cpu_we_i,
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cpu_ack_o,
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cpu_ack_o,
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cpu_rst_o
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cpu_rst_o
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);
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);
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// CPU signals
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// CPU signals
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input cpu_rst_i;
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input cpu_rst_i;
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output cpu_clk_o;
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output cpu_clk_o;
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input [31:0] cpu_addr_i;
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input [31:0] cpu_addr_i;
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output [31:0] cpu_data_o;
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output [31:0] cpu_data_o;
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input [31:0] cpu_data_i;
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input [31:0] cpu_data_i;
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output cpu_bp_o;
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output cpu_bp_o;
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input cpu_stall_i;
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input cpu_stall_i;
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input cpu_stb_i;
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input cpu_stb_i;
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input cpu_we_i;
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input cpu_we_i;
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output cpu_ack_o;
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output cpu_ack_o;
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output cpu_rst_o;
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output cpu_rst_o;
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reg cpu_clk_o;
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reg cpu_clk_o;
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reg [31:0] cpu_data_o;
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reg [31:0] cpu_data_o;
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reg cpu_bp_o;
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reg cpu_bp_o;
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reg cpu_ack_o;
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reg cpu_ack_o;
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reg cpu_ack_q;
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reg cpu_ack_q;
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wire cpu_ack;
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wire cpu_ack;
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initial
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initial
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begin
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begin
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cpu_clk_o = 1'b0;
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cpu_clk_o = 1'b0;
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forever #5 cpu_clk_o = ~cpu_clk_o;
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forever #5 cpu_clk_o = ~cpu_clk_o;
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end
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end
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initial
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initial
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begin
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begin
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cpu_bp_o = 1'b0;
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cpu_bp_o = 1'b0;
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end
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end
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assign #200 cpu_ack = cpu_stall_i & cpu_stb_i;
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assign #200 cpu_ack = cpu_stall_i & cpu_stb_i;
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always @ (posedge cpu_clk_o or posedge cpu_rst_i)
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always @ (posedge cpu_clk_o or posedge cpu_rst_i)
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begin
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begin
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if (cpu_rst_i)
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if (cpu_rst_i)
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begin
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begin
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cpu_ack_o <= #1 1'b0;
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cpu_ack_o <= #1 1'b0;
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cpu_ack_q <= #1 1'b0;
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cpu_ack_q <= #1 1'b0;
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end
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end
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else
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else
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begin
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begin
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cpu_ack_o <= #1 cpu_ack;
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cpu_ack_o <= #1 cpu_ack;
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cpu_ack_q <= #1 cpu_ack_o;
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cpu_ack_q <= #1 cpu_ack_o;
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end
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end
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end
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end
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always @ (posedge cpu_clk_o or posedge cpu_rst_i)
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always @ (posedge cpu_clk_o or posedge cpu_rst_i)
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begin
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begin
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if (cpu_rst_i)
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if (cpu_rst_i)
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cpu_data_o <= #1 32'h12345678;
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cpu_data_o <= #1 32'h12345678;
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else if (cpu_ack_o && (!cpu_ack_q))
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else if (cpu_ack_o && (!cpu_ack_q))
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cpu_data_o <= #1 cpu_data_o + 32'h11111111;
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cpu_data_o <= #1 cpu_data_o + 32'h11111111;
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end
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end
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endmodule
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endmodule
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