//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// adbg_or1k_biu.v ////
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//// adbg_or1k_biu.v ////
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//// ////
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//// ////
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//// ////
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//// ////
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//// This file is part of the SoC Advanced Debug Interface. ////
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//// This file is part of the SoC Advanced Debug Interface. ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// Nathan Yawn (nathan.yawn@opencores.org) ////
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//// Nathan Yawn (nathan.yawn@opencores.org) ////
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//// ////
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//// ////
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//// ////
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//// ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2008 Authors ////
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//// Copyright (C) 2008 - 2010 Authors ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: adbg_or1k_biu.v,v $
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// $Log: adbg_or1k_biu.v,v $
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// Revision 1.3 2010-01-10 22:54:10 Nathan
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// Update copyright dates
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//
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// Revision 1.2 2009/05/17 20:54:56 Nathan
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// Revision 1.2 2009/05/17 20:54:56 Nathan
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// Changed email address to opencores.org
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// Changed email address to opencores.org
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//
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//
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// Revision 1.1 2008/07/22 20:28:30 Nathan
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// Revision 1.1 2008/07/22 20:28:30 Nathan
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// Changed names of all files and modules (prefixed an a, for advanced). Cleanup, indenting. No functional changes.
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// Changed names of all files and modules (prefixed an a, for advanced). Cleanup, indenting. No functional changes.
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//
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//
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// Revision 1.5 2008/07/08 19:04:03 Nathan
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// Revision 1.5 2008/07/08 19:04:03 Nathan
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// Many small changes to eliminate compiler warnings, no functional
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// Many small changes to eliminate compiler warnings, no functional
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// changes. System will now pass SRAM and CPU self-tests on Altera
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// changes. System will now pass SRAM and CPU self-tests on Altera
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// FPGA using altera_virtual_jtag TAP.
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// FPGA using altera_virtual_jtag TAP.
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//
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//
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module adbg_or1k_biu
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module adbg_or1k_biu
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(
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(
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// Debug interface signals
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// Debug interface signals
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tck_i,
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tck_i,
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rst_i,
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rst_i,
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data_i,
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data_i,
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data_o,
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data_o,
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addr_i,
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addr_i,
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strobe_i,
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strobe_i,
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rd_wrn_i, // If 0, then write op
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rd_wrn_i, // If 0, then write op
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rdy_o,
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rdy_o,
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// OR1K SPR bus signals
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// OR1K SPR bus signals
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cpu_clk_i,
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cpu_clk_i,
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cpu_addr_o,
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cpu_addr_o,
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cpu_data_i,
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cpu_data_i,
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cpu_data_o,
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cpu_data_o,
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cpu_stb_o,
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cpu_stb_o,
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cpu_we_o,
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cpu_we_o,
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cpu_ack_i
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cpu_ack_i
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);
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);
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// Debug interface signals
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// Debug interface signals
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input tck_i;
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input tck_i;
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input rst_i;
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input rst_i;
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input [31:0] data_i; // Assume short words are in UPPER order bits!
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input [31:0] data_i; // Assume short words are in UPPER order bits!
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output [31:0] data_o;
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output [31:0] data_o;
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input [31:0] addr_i;
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input [31:0] addr_i;
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input strobe_i;
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input strobe_i;
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input rd_wrn_i;
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input rd_wrn_i;
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output rdy_o;
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output rdy_o;
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// OR1K SPR bus signals
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// OR1K SPR bus signals
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input cpu_clk_i;
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input cpu_clk_i;
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output [31:0] cpu_addr_o;
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output [31:0] cpu_addr_o;
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input [31:0] cpu_data_i;
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input [31:0] cpu_data_i;
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output [31:0] cpu_data_o;
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output [31:0] cpu_data_o;
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output cpu_stb_o;
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output cpu_stb_o;
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output cpu_we_o;
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output cpu_we_o;
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input cpu_ack_i;
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input cpu_ack_i;
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reg rdy_o;
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reg rdy_o;
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reg cpu_stb_o;
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reg cpu_stb_o;
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// Registers
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// Registers
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reg [31:0] addr_reg;
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reg [31:0] addr_reg;
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reg [31:0] data_in_reg; // dbg->WB
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reg [31:0] data_in_reg; // dbg->WB
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reg [31:0] data_out_reg; // WB->dbg
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reg [31:0] data_out_reg; // WB->dbg
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reg wr_reg;
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reg wr_reg;
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reg str_sync; // This is 'active-toggle' rather than -high or -low.
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reg str_sync; // This is 'active-toggle' rather than -high or -low.
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reg rdy_sync; // ditto, active-toggle
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reg rdy_sync; // ditto, active-toggle
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|
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// Sync registers. TFF indicates TCK domain, WBFF indicates cpu_clk domain
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// Sync registers. TFF indicates TCK domain, WBFF indicates cpu_clk domain
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reg rdy_sync_tff1;
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reg rdy_sync_tff1;
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reg rdy_sync_tff2;
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reg rdy_sync_tff2;
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reg rdy_sync_tff2q; // used to detect toggles
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reg rdy_sync_tff2q; // used to detect toggles
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reg str_sync_wbff1;
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reg str_sync_wbff1;
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reg str_sync_wbff2;
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reg str_sync_wbff2;
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reg str_sync_wbff2q; // used to detect toggles
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reg str_sync_wbff2q; // used to detect toggles
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|
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// Control Signals
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// Control Signals
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reg data_o_en; // latch wb_data_i
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reg data_o_en; // latch wb_data_i
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reg rdy_sync_en; // toggle the rdy_sync signal, indicate ready to TCK domain
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reg rdy_sync_en; // toggle the rdy_sync signal, indicate ready to TCK domain
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|
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// Internal signals
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// Internal signals
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wire start_toggle; // CPU domain, indicates a toggle on the start strobe
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wire start_toggle; // CPU domain, indicates a toggle on the start strobe
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|
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//////////////////////////////////////////////////////
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//////////////////////////////////////////////////////
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// TCK clock domain
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// TCK clock domain
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// There is no FSM here, just signal latching and clock
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// There is no FSM here, just signal latching and clock
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// domain synchronization
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// domain synchronization
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// Latch input data on 'start' strobe, if ready.
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// Latch input data on 'start' strobe, if ready.
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always @ (posedge tck_i or posedge rst_i)
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always @ (posedge tck_i or posedge rst_i)
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begin
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begin
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if(rst_i) begin
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if(rst_i) begin
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addr_reg <= 32'h0;
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addr_reg <= 32'h0;
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data_in_reg <= 32'h0;
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data_in_reg <= 32'h0;
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wr_reg <= 1'b0;
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wr_reg <= 1'b0;
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end
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end
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else
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else
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if(strobe_i && rdy_o) begin
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if(strobe_i && rdy_o) begin
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addr_reg <= addr_i;
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addr_reg <= addr_i;
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if(!rd_wrn_i) data_in_reg <= data_i;
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if(!rd_wrn_i) data_in_reg <= data_i;
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wr_reg <= ~rd_wrn_i;
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wr_reg <= ~rd_wrn_i;
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end
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end
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end
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end
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|
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// Create toggle-active strobe signal for clock sync. This will start a transaction
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// Create toggle-active strobe signal for clock sync. This will start a transaction
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// to the CPU once the toggle propagates to the FSM in the cpu_clk domain.
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// to the CPU once the toggle propagates to the FSM in the cpu_clk domain.
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always @ (posedge tck_i or posedge rst_i)
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always @ (posedge tck_i or posedge rst_i)
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begin
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begin
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if(rst_i) str_sync <= 1'b0;
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if(rst_i) str_sync <= 1'b0;
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else if(strobe_i && rdy_o) str_sync <= ~str_sync;
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else if(strobe_i && rdy_o) str_sync <= ~str_sync;
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end
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end
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// Create rdy_o output. Set on reset, clear on strobe (if set), set on input toggle
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// Create rdy_o output. Set on reset, clear on strobe (if set), set on input toggle
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always @ (posedge tck_i or posedge rst_i)
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always @ (posedge tck_i or posedge rst_i)
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begin
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begin
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if(rst_i) begin
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if(rst_i) begin
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rdy_sync_tff1 <= 1'b0;
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rdy_sync_tff1 <= 1'b0;
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rdy_sync_tff2 <= 1'b0;
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rdy_sync_tff2 <= 1'b0;
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rdy_sync_tff2q <= 1'b0;
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rdy_sync_tff2q <= 1'b0;
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rdy_o <= 1'b1;
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rdy_o <= 1'b1;
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end
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end
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else begin
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else begin
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rdy_sync_tff1 <= rdy_sync; // Synchronize the ready signal across clock domains
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rdy_sync_tff1 <= rdy_sync; // Synchronize the ready signal across clock domains
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rdy_sync_tff2 <= rdy_sync_tff1;
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rdy_sync_tff2 <= rdy_sync_tff1;
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rdy_sync_tff2q <= rdy_sync_tff2; // used to detect toggles
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rdy_sync_tff2q <= rdy_sync_tff2; // used to detect toggles
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|
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if(strobe_i && rdy_o) rdy_o <= 1'b0;
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if(strobe_i && rdy_o) rdy_o <= 1'b0;
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else if(rdy_sync_tff2 != rdy_sync_tff2q) rdy_o <= 1'b1;
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else if(rdy_sync_tff2 != rdy_sync_tff2q) rdy_o <= 1'b1;
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end
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end
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end
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end
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//////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////
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// Direct assignments, unsynchronized
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// Direct assignments, unsynchronized
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|
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assign cpu_data_o = data_in_reg;
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assign cpu_data_o = data_in_reg;
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assign cpu_we_o = wr_reg;
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assign cpu_we_o = wr_reg;
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assign cpu_addr_o = addr_reg;
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assign cpu_addr_o = addr_reg;
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|
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assign data_o = data_out_reg;
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assign data_o = data_out_reg;
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|
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|
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///////////////////////////////////////////////////////
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///////////////////////////////////////////////////////
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// Wishbone clock domain
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// Wishbone clock domain
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|
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// synchronize the start strobe
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// synchronize the start strobe
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always @ (posedge cpu_clk_i or posedge rst_i)
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always @ (posedge cpu_clk_i or posedge rst_i)
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begin
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begin
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if(rst_i) begin
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if(rst_i) begin
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str_sync_wbff1 <= 1'b0;
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str_sync_wbff1 <= 1'b0;
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str_sync_wbff2 <= 1'b0;
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str_sync_wbff2 <= 1'b0;
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str_sync_wbff2q <= 1'b0;
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str_sync_wbff2q <= 1'b0;
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end
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end
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else begin
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else begin
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str_sync_wbff1 <= str_sync;
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str_sync_wbff1 <= str_sync;
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str_sync_wbff2 <= str_sync_wbff1;
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str_sync_wbff2 <= str_sync_wbff1;
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str_sync_wbff2q <= str_sync_wbff2; // used to detect toggles
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str_sync_wbff2q <= str_sync_wbff2; // used to detect toggles
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end
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end
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end
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end
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|
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assign start_toggle = (str_sync_wbff2 != str_sync_wbff2q);
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assign start_toggle = (str_sync_wbff2 != str_sync_wbff2q);
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|
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|
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// CPU->dbg data register
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// CPU->dbg data register
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always @ (posedge cpu_clk_i or posedge rst_i)
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always @ (posedge cpu_clk_i or posedge rst_i)
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begin
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begin
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if(rst_i) data_out_reg <= 32'h0;
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if(rst_i) data_out_reg <= 32'h0;
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else if(data_o_en) data_out_reg <= cpu_data_i;
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else if(data_o_en) data_out_reg <= cpu_data_i;
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end
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end
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|
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// Create a toggle-active ready signal to send to the TCK domain
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// Create a toggle-active ready signal to send to the TCK domain
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always @ (posedge cpu_clk_i or posedge rst_i)
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always @ (posedge cpu_clk_i or posedge rst_i)
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begin
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begin
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if(rst_i) rdy_sync <= 1'b0;
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if(rst_i) rdy_sync <= 1'b0;
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else if(rdy_sync_en) rdy_sync <= ~rdy_sync;
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else if(rdy_sync_en) rdy_sync <= ~rdy_sync;
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end
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end
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/////////////////////////////////////////////////////
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/////////////////////////////////////////////////////
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// Small state machine to create OR1K SPR bus accesses
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// Small state machine to create OR1K SPR bus accesses
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// Not much more that an 'in_progress' bit, but easier
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// Not much more that an 'in_progress' bit, but easier
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// to read. Deals with single-cycle and multi-cycle
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// to read. Deals with single-cycle and multi-cycle
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// accesses.
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// accesses.
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|
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reg cpu_fsm_state;
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reg cpu_fsm_state;
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reg next_fsm_state;
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reg next_fsm_state;
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|
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`define STATE_IDLE 1'h0
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`define STATE_IDLE 1'h0
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`define STATE_TRANSFER 1'h1
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`define STATE_TRANSFER 1'h1
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|
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// Sequential bit
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// Sequential bit
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always @ (posedge cpu_clk_i or posedge rst_i)
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always @ (posedge cpu_clk_i or posedge rst_i)
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begin
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begin
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if(rst_i) cpu_fsm_state <= `STATE_IDLE;
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if(rst_i) cpu_fsm_state <= `STATE_IDLE;
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else cpu_fsm_state <= next_fsm_state;
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else cpu_fsm_state <= next_fsm_state;
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end
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end
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|
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// Determination of next state (combinatorial)
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// Determination of next state (combinatorial)
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always @ (cpu_fsm_state or start_toggle or cpu_ack_i)
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always @ (cpu_fsm_state or start_toggle or cpu_ack_i)
|
begin
|
begin
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case (cpu_fsm_state)
|
case (cpu_fsm_state)
|
`STATE_IDLE:
|
`STATE_IDLE:
|
begin
|
begin
|
if(start_toggle && !cpu_ack_i) next_fsm_state <= `STATE_TRANSFER; // Don't go to next state for 1-cycle transfer
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if(start_toggle && !cpu_ack_i) next_fsm_state <= `STATE_TRANSFER; // Don't go to next state for 1-cycle transfer
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else next_fsm_state <= `STATE_IDLE;
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else next_fsm_state <= `STATE_IDLE;
|
end
|
end
|
`STATE_TRANSFER:
|
`STATE_TRANSFER:
|
begin
|
begin
|
if(cpu_ack_i) next_fsm_state <= `STATE_IDLE;
|
if(cpu_ack_i) next_fsm_state <= `STATE_IDLE;
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else next_fsm_state <= `STATE_TRANSFER;
|
else next_fsm_state <= `STATE_TRANSFER;
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
|
|
// Outputs of state machine (combinatorial)
|
// Outputs of state machine (combinatorial)
|
always @ (cpu_fsm_state or start_toggle or cpu_ack_i or wr_reg)
|
always @ (cpu_fsm_state or start_toggle or cpu_ack_i or wr_reg)
|
begin
|
begin
|
rdy_sync_en <= 1'b0;
|
rdy_sync_en <= 1'b0;
|
data_o_en <= 1'b0;
|
data_o_en <= 1'b0;
|
cpu_stb_o <= 1'b0;
|
cpu_stb_o <= 1'b0;
|
|
|
case (cpu_fsm_state)
|
case (cpu_fsm_state)
|
`STATE_IDLE:
|
`STATE_IDLE:
|
begin
|
begin
|
if(start_toggle) begin
|
if(start_toggle) begin
|
cpu_stb_o <= 1'b1;
|
cpu_stb_o <= 1'b1;
|
if(cpu_ack_i) begin
|
if(cpu_ack_i) begin
|
rdy_sync_en <= 1'b1;
|
rdy_sync_en <= 1'b1;
|
end
|
end
|
|
|
if (cpu_ack_i && !wr_reg) begin // latch read data
|
if (cpu_ack_i && !wr_reg) begin // latch read data
|
data_o_en <= 1'b1;
|
data_o_en <= 1'b1;
|
end
|
end
|
end
|
end
|
end
|
end
|
|
|
`STATE_TRANSFER:
|
`STATE_TRANSFER:
|
begin
|
begin
|
cpu_stb_o <= 1'b1; // OR1K behavioral model needs this. OR1200 should be indifferent.
|
cpu_stb_o <= 1'b1; // OR1K behavioral model needs this. OR1200 should be indifferent.
|
if(cpu_ack_i) begin
|
if(cpu_ack_i) begin
|
data_o_en <= 1'b1;
|
data_o_en <= 1'b1;
|
rdy_sync_en <= 1'b1;
|
rdy_sync_en <= 1'b1;
|
end
|
end
|
end
|
end
|
endcase
|
endcase
|
|
|
end
|
end
|
|
|
endmodule
|
endmodule
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|
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|
|