//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// adbg_wb_biu.v ////
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//// adbg_wb_biu.v ////
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//// ////
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//// ////
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//// ////
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//// ////
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//// This file is part of the SoC Debug Interface. ////
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//// This file is part of the SoC Debug Interface. ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// Nathan Yawn (nathan.yawn@opencores.org) ////
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//// Nathan Yawn (nathan.yawn@opencores.org) ////
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//// ////
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//// ////
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//// ////
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//// ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2008 Authors ////
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//// Copyright (C) 2008-2010 Authors ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: adbg_wb_biu.v,v $
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// $Log: adbg_wb_biu.v,v $
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// Revision 1.4 2010-01-10 22:54:11 Nathan
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// Update copyright dates
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//
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// Revision 1.3 2009/05/17 20:54:57 Nathan
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// Revision 1.3 2009/05/17 20:54:57 Nathan
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// Changed email address to opencores.org
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// Changed email address to opencores.org
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//
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//
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// Revision 1.2 2009/05/04 00:50:10 Nathan
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// Revision 1.2 2009/05/04 00:50:10 Nathan
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// Changed the WB BIU to use big-endian byte ordering, to match the OR1000. Kept little-endian ordering as a compile-time option in case this is ever used with a little-endian CPU.
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// Changed the WB BIU to use big-endian byte ordering, to match the OR1000. Kept little-endian ordering as a compile-time option in case this is ever used with a little-endian CPU.
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//
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//
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// Revision 1.1 2008/07/22 20:28:32 Nathan
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// Revision 1.1 2008/07/22 20:28:32 Nathan
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// Changed names of all files and modules (prefixed an a, for advanced). Cleanup, indenting. No functional changes.
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// Changed names of all files and modules (prefixed an a, for advanced). Cleanup, indenting. No functional changes.
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//
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//
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// Revision 1.4 2008/07/08 19:04:04 Nathan
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// Revision 1.4 2008/07/08 19:04:04 Nathan
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// Many small changes to eliminate compiler warnings, no functional changes.
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// Many small changes to eliminate compiler warnings, no functional changes.
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// System will now pass SRAM and CPU self-tests on Altera FPGA using
|
// System will now pass SRAM and CPU self-tests on Altera FPGA using
|
// altera_virtual_jtag TAP.
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// altera_virtual_jtag TAP.
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//
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//
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`include "adbg_wb_defines.v"
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`include "adbg_wb_defines.v"
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|
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// Top module
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// Top module
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module adbg_wb_biu
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module adbg_wb_biu
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(
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(
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// Debug interface signals
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// Debug interface signals
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tck_i,
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tck_i,
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rst_i,
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rst_i,
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data_i,
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data_i,
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data_o,
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data_o,
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addr_i,
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addr_i,
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strobe_i,
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strobe_i,
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rd_wrn_i, // If 0, then write op
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rd_wrn_i, // If 0, then write op
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rdy_o,
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rdy_o,
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err_o,
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err_o,
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word_size_i, // 1,2, or 4
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word_size_i, // 1,2, or 4
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|
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// Wishbone signals
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// Wishbone signals
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wb_clk_i,
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wb_clk_i,
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wb_adr_o,
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wb_adr_o,
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wb_dat_o,
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wb_dat_o,
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wb_dat_i,
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wb_dat_i,
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wb_cyc_o,
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wb_cyc_o,
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wb_stb_o,
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wb_stb_o,
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wb_sel_o,
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wb_sel_o,
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wb_we_o,
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wb_we_o,
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wb_ack_i,
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wb_ack_i,
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wb_cab_o,
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wb_cab_o,
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wb_err_i,
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wb_err_i,
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wb_cti_o,
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wb_cti_o,
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wb_bte_o
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wb_bte_o
|
);
|
);
|
|
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// Debug interface signals
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// Debug interface signals
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input tck_i;
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input tck_i;
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input rst_i;
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input rst_i;
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input [31:0] data_i; // Assume short words are in UPPER order bits!
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input [31:0] data_i; // Assume short words are in UPPER order bits!
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output [31:0] data_o;
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output [31:0] data_o;
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input [31:0] addr_i;
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input [31:0] addr_i;
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input strobe_i;
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input strobe_i;
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input rd_wrn_i;
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input rd_wrn_i;
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output rdy_o;
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output rdy_o;
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output err_o;
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output err_o;
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input [2:0] word_size_i;
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input [2:0] word_size_i;
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|
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// Wishbone signals
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// Wishbone signals
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input wb_clk_i;
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input wb_clk_i;
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output [31:0] wb_adr_o;
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output [31:0] wb_adr_o;
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output [31:0] wb_dat_o;
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output [31:0] wb_dat_o;
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input [31:0] wb_dat_i;
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input [31:0] wb_dat_i;
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output wb_cyc_o;
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output wb_cyc_o;
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output wb_stb_o;
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output wb_stb_o;
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output [3:0] wb_sel_o;
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output [3:0] wb_sel_o;
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output wb_we_o;
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output wb_we_o;
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input wb_ack_i;
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input wb_ack_i;
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output wb_cab_o;
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output wb_cab_o;
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input wb_err_i;
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input wb_err_i;
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output [2:0] wb_cti_o;
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output [2:0] wb_cti_o;
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output [1:0] wb_bte_o;
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output [1:0] wb_bte_o;
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|
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wire [31:0] data_o;
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wire [31:0] data_o;
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reg rdy_o;
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reg rdy_o;
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wire err_o;
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wire err_o;
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|
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wire [31:0] wb_adr_o;
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wire [31:0] wb_adr_o;
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reg wb_cyc_o;
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reg wb_cyc_o;
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reg wb_stb_o;
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reg wb_stb_o;
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wire [31:0] wb_dat_o;
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wire [31:0] wb_dat_o;
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wire [3:0] wb_sel_o;
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wire [3:0] wb_sel_o;
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wire wb_we_o;
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wire wb_we_o;
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wire wb_cab_o;
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wire wb_cab_o;
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wire [2:0] wb_cti_o;
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wire [2:0] wb_cti_o;
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wire [1:0] wb_bte_o;
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wire [1:0] wb_bte_o;
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|
|
|
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// Registers
|
// Registers
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reg [3:0] sel_reg;
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reg [3:0] sel_reg;
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reg [29:0] addr_reg; // Don't need the two LSB, this info is in the SEL bits
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reg [29:0] addr_reg; // Don't need the two LSB, this info is in the SEL bits
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reg [31:0] data_in_reg; // dbg->WB
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reg [31:0] data_in_reg; // dbg->WB
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reg [31:0] data_out_reg; // WB->dbg
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reg [31:0] data_out_reg; // WB->dbg
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reg wr_reg;
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reg wr_reg;
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reg str_sync; // This is 'active-toggle' rather than -high or -low.
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reg str_sync; // This is 'active-toggle' rather than -high or -low.
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reg rdy_sync; // ditto, active-toggle
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reg rdy_sync; // ditto, active-toggle
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reg err_reg;
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reg err_reg;
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|
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// Sync registers. TFF indicates TCK domain, WBFF indicates wb_clk domain
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// Sync registers. TFF indicates TCK domain, WBFF indicates wb_clk domain
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reg rdy_sync_tff1;
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reg rdy_sync_tff1;
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reg rdy_sync_tff2;
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reg rdy_sync_tff2;
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reg rdy_sync_tff2q; // used to detect toggles
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reg rdy_sync_tff2q; // used to detect toggles
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reg str_sync_wbff1;
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reg str_sync_wbff1;
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reg str_sync_wbff2;
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reg str_sync_wbff2;
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reg str_sync_wbff2q; // used to detect toggles
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reg str_sync_wbff2q; // used to detect toggles
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|
|
|
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// Control Signals
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// Control Signals
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reg data_o_en; // latch wb_data_i
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reg data_o_en; // latch wb_data_i
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reg rdy_sync_en; // toggle the rdy_sync signal, indicate ready to TCK domain
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reg rdy_sync_en; // toggle the rdy_sync signal, indicate ready to TCK domain
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reg err_en; // latch the wb_err_i signal
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reg err_en; // latch the wb_err_i signal
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|
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// Internal signals
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// Internal signals
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reg [3:0] be_dec; // word_size and low-order address bits decoded to SEL bits
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reg [3:0] be_dec; // word_size and low-order address bits decoded to SEL bits
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wire start_toggle; // WB domain, indicates a toggle on the start strobe
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wire start_toggle; // WB domain, indicates a toggle on the start strobe
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reg [31:0] swapped_data_i;
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reg [31:0] swapped_data_i;
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reg [31:0] swapped_data_out;
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reg [31:0] swapped_data_out;
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|
|
//////////////////////////////////////////////////////
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//////////////////////////////////////////////////////
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// TCK clock domain
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// TCK clock domain
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// There is no FSM here, just signal latching and clock
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// There is no FSM here, just signal latching and clock
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// domain synchronization
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// domain synchronization
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|
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// Create byte enable signals from word_size and address (combinatorial)
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// Create byte enable signals from word_size and address (combinatorial)
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`ifdef DBG_WB_LITTLE_ENDIAN
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`ifdef DBG_WB_LITTLE_ENDIAN
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// This uses LITTLE ENDIAN byte ordering...lowest-addressed bytes is the
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// This uses LITTLE ENDIAN byte ordering...lowest-addressed bytes is the
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// least-significant byte of the 32-bit WB bus.
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// least-significant byte of the 32-bit WB bus.
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always @ (word_size_i or addr_i)
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always @ (word_size_i or addr_i)
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begin
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begin
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case (word_size_i)
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case (word_size_i)
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3'h1:
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3'h1:
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begin
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begin
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if(addr_i[1:0] == 2'b00) be_dec <= 4'b0001;
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if(addr_i[1:0] == 2'b00) be_dec <= 4'b0001;
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else if(addr_i[1:0] == 2'b01) be_dec <= 4'b0010;
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else if(addr_i[1:0] == 2'b01) be_dec <= 4'b0010;
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else if(addr_i[1:0] == 2'b10) be_dec <= 4'b0100;
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else if(addr_i[1:0] == 2'b10) be_dec <= 4'b0100;
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else be_dec <= 4'b1000;
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else be_dec <= 4'b1000;
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end
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end
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3'h2:
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3'h2:
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begin
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begin
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if(addr_i[1]) be_dec <= 4'b1100;
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if(addr_i[1]) be_dec <= 4'b1100;
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else be_dec <= 4'b0011;
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else be_dec <= 4'b0011;
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end
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end
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3'h4: be_dec <= 4'b1111;
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3'h4: be_dec <= 4'b1111;
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default: be_dec <= 4'b1111; // default to 32-bit access
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default: be_dec <= 4'b1111; // default to 32-bit access
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endcase
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endcase
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end
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end
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`else
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`else
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// This is for a BIG ENDIAN CPU...lowest-addressed byte is
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// This is for a BIG ENDIAN CPU...lowest-addressed byte is
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// the 8 most significant bits of the 32-bit WB bus.
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// the 8 most significant bits of the 32-bit WB bus.
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always @ (word_size_i or addr_i)
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always @ (word_size_i or addr_i)
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begin
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begin
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case (word_size_i)
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case (word_size_i)
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3'h1:
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3'h1:
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begin
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begin
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if(addr_i[1:0] == 2'b00) be_dec <= 4'b1000;
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if(addr_i[1:0] == 2'b00) be_dec <= 4'b1000;
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else if(addr_i[1:0] == 2'b01) be_dec <= 4'b0100;
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else if(addr_i[1:0] == 2'b01) be_dec <= 4'b0100;
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else if(addr_i[1:0] == 2'b10) be_dec <= 4'b0010;
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else if(addr_i[1:0] == 2'b10) be_dec <= 4'b0010;
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else be_dec <= 4'b0001;
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else be_dec <= 4'b0001;
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end
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end
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3'h2:
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3'h2:
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begin
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begin
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if(addr_i[1] == 1'b1) be_dec <= 4'b0011;
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if(addr_i[1] == 1'b1) be_dec <= 4'b0011;
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else be_dec <= 4'b1100;
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else be_dec <= 4'b1100;
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end
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end
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3'h4: be_dec <= 4'b1111;
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3'h4: be_dec <= 4'b1111;
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default: be_dec <= 4'b1111; // default to 32-bit access
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default: be_dec <= 4'b1111; // default to 32-bit access
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endcase
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endcase
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end
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end
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`endif
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`endif
|
|
|
|
|
// Byte- or word-swap data as necessary. Use the non-latched be_dec signal,
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// Byte- or word-swap data as necessary. Use the non-latched be_dec signal,
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// since it and the swapped data will be latched at the same time.
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// since it and the swapped data will be latched at the same time.
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// Remember that since the data is shifted in LSB-first, shorter words
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// Remember that since the data is shifted in LSB-first, shorter words
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// will be in the high-order bits. (combinatorial)
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// will be in the high-order bits. (combinatorial)
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always @ (be_dec or data_i)
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always @ (be_dec or data_i)
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begin
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begin
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case (be_dec)
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case (be_dec)
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4'b1111: swapped_data_i <= data_i;
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4'b1111: swapped_data_i <= data_i;
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4'b0011: swapped_data_i <= {16'h0,data_i[31:16]};
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4'b0011: swapped_data_i <= {16'h0,data_i[31:16]};
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4'b1100: swapped_data_i <= data_i;
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4'b1100: swapped_data_i <= data_i;
|
4'b0001: swapped_data_i <= {24'h0, data_i[31:24]};
|
4'b0001: swapped_data_i <= {24'h0, data_i[31:24]};
|
4'b0010: swapped_data_i <= {16'h0, data_i[31:24], 8'h0};
|
4'b0010: swapped_data_i <= {16'h0, data_i[31:24], 8'h0};
|
4'b0100: swapped_data_i <= {8'h0, data_i[31:24], 16'h0};
|
4'b0100: swapped_data_i <= {8'h0, data_i[31:24], 16'h0};
|
4'b1000: swapped_data_i <= {data_i[31:24], 24'h0};
|
4'b1000: swapped_data_i <= {data_i[31:24], 24'h0};
|
default: swapped_data_i <= data_i; // Shouldn't be possible
|
default: swapped_data_i <= data_i; // Shouldn't be possible
|
endcase
|
endcase
|
end
|
end
|
|
|
// Latch input data on 'start' strobe, if ready.
|
// Latch input data on 'start' strobe, if ready.
|
always @ (posedge tck_i or posedge rst_i)
|
always @ (posedge tck_i or posedge rst_i)
|
begin
|
begin
|
if(rst_i) begin
|
if(rst_i) begin
|
sel_reg <= 4'h0;
|
sel_reg <= 4'h0;
|
addr_reg <= 30'h0;
|
addr_reg <= 30'h0;
|
data_in_reg <= 32'h0;
|
data_in_reg <= 32'h0;
|
wr_reg <= 1'b0;
|
wr_reg <= 1'b0;
|
end
|
end
|
else
|
else
|
if(strobe_i && rdy_o) begin
|
if(strobe_i && rdy_o) begin
|
sel_reg <= be_dec;
|
sel_reg <= be_dec;
|
addr_reg <= addr_i[31:2];
|
addr_reg <= addr_i[31:2];
|
if(!rd_wrn_i) data_in_reg <= swapped_data_i;
|
if(!rd_wrn_i) data_in_reg <= swapped_data_i;
|
wr_reg <= ~rd_wrn_i;
|
wr_reg <= ~rd_wrn_i;
|
end
|
end
|
end
|
end
|
|
|
// Create toggle-active strobe signal for clock sync. This will start a transaction
|
// Create toggle-active strobe signal for clock sync. This will start a transaction
|
// on the WB once the toggle propagates to the FSM in the WB domain.
|
// on the WB once the toggle propagates to the FSM in the WB domain.
|
always @ (posedge tck_i or posedge rst_i)
|
always @ (posedge tck_i or posedge rst_i)
|
begin
|
begin
|
if(rst_i) str_sync <= 1'b0;
|
if(rst_i) str_sync <= 1'b0;
|
else if(strobe_i && rdy_o) str_sync <= ~str_sync;
|
else if(strobe_i && rdy_o) str_sync <= ~str_sync;
|
end
|
end
|
|
|
// Create rdy_o output. Set on reset, clear on strobe (if set), set on input toggle
|
// Create rdy_o output. Set on reset, clear on strobe (if set), set on input toggle
|
always @ (posedge tck_i or posedge rst_i)
|
always @ (posedge tck_i or posedge rst_i)
|
begin
|
begin
|
if(rst_i) begin
|
if(rst_i) begin
|
rdy_sync_tff1 <= 1'b0;
|
rdy_sync_tff1 <= 1'b0;
|
rdy_sync_tff2 <= 1'b0;
|
rdy_sync_tff2 <= 1'b0;
|
rdy_sync_tff2q <= 1'b0;
|
rdy_sync_tff2q <= 1'b0;
|
rdy_o <= 1'b1;
|
rdy_o <= 1'b1;
|
end
|
end
|
else begin
|
else begin
|
rdy_sync_tff1 <= rdy_sync; // Synchronize the ready signal across clock domains
|
rdy_sync_tff1 <= rdy_sync; // Synchronize the ready signal across clock domains
|
rdy_sync_tff2 <= rdy_sync_tff1;
|
rdy_sync_tff2 <= rdy_sync_tff1;
|
rdy_sync_tff2q <= rdy_sync_tff2; // used to detect toggles
|
rdy_sync_tff2q <= rdy_sync_tff2; // used to detect toggles
|
|
|
if(strobe_i && rdy_o) rdy_o <= 1'b0;
|
if(strobe_i && rdy_o) rdy_o <= 1'b0;
|
else if(rdy_sync_tff2 != rdy_sync_tff2q) rdy_o <= 1'b1;
|
else if(rdy_sync_tff2 != rdy_sync_tff2q) rdy_o <= 1'b1;
|
end
|
end
|
|
|
end
|
end
|
|
|
//////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////
|
// Direct assignments, unsynchronized
|
// Direct assignments, unsynchronized
|
|
|
assign wb_dat_o = data_in_reg;
|
assign wb_dat_o = data_in_reg;
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assign wb_we_o = wr_reg;
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assign wb_we_o = wr_reg;
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assign wb_adr_o = {addr_reg, 2'h0};
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assign wb_adr_o = {addr_reg, 2'h0};
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assign wb_sel_o = sel_reg;
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assign wb_sel_o = sel_reg;
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|
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assign data_o = data_out_reg;
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assign data_o = data_out_reg;
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assign err_o = err_reg;
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assign err_o = err_reg;
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|
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assign wb_cti_o = 3'h0;
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assign wb_cti_o = 3'h0;
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assign wb_bte_o = 2'h0;
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assign wb_bte_o = 2'h0;
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assign wb_cab_o = 1'b0;
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assign wb_cab_o = 1'b0;
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|
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///////////////////////////////////////////////////////
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///////////////////////////////////////////////////////
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// Wishbone clock domain
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// Wishbone clock domain
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|
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// synchronize the start strobe
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// synchronize the start strobe
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always @ (posedge wb_clk_i or posedge rst_i)
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always @ (posedge wb_clk_i or posedge rst_i)
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begin
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begin
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if(rst_i) begin
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if(rst_i) begin
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str_sync_wbff1 <= 1'b0;
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str_sync_wbff1 <= 1'b0;
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str_sync_wbff2 <= 1'b0;
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str_sync_wbff2 <= 1'b0;
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str_sync_wbff2q <= 1'b0;
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str_sync_wbff2q <= 1'b0;
|
end
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end
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else begin
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else begin
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str_sync_wbff1 <= str_sync;
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str_sync_wbff1 <= str_sync;
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str_sync_wbff2 <= str_sync_wbff1;
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str_sync_wbff2 <= str_sync_wbff1;
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str_sync_wbff2q <= str_sync_wbff2; // used to detect toggles
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str_sync_wbff2q <= str_sync_wbff2; // used to detect toggles
|
end
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end
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end
|
end
|
|
|
assign start_toggle = (str_sync_wbff2 != str_sync_wbff2q);
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assign start_toggle = (str_sync_wbff2 != str_sync_wbff2q);
|
|
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// Error indicator register
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// Error indicator register
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always @ (posedge wb_clk_i or posedge rst_i)
|
always @ (posedge wb_clk_i or posedge rst_i)
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begin
|
begin
|
if(rst_i) err_reg <= 1'b0;
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if(rst_i) err_reg <= 1'b0;
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else if(err_en) err_reg <= wb_err_i;
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else if(err_en) err_reg <= wb_err_i;
|
end
|
end
|
|
|
// Byte- or word-swap the WB->dbg data, as necessary (combinatorial)
|
// Byte- or word-swap the WB->dbg data, as necessary (combinatorial)
|
// We assume bits not required by SEL are don't care. We reuse assignments
|
// We assume bits not required by SEL are don't care. We reuse assignments
|
// where possible to keep the MUX smaller. (combinatorial)
|
// where possible to keep the MUX smaller. (combinatorial)
|
always @ (sel_reg or wb_dat_i)
|
always @ (sel_reg or wb_dat_i)
|
begin
|
begin
|
case (sel_reg)
|
case (sel_reg)
|
4'b1111: swapped_data_out <= wb_dat_i;
|
4'b1111: swapped_data_out <= wb_dat_i;
|
4'b0011: swapped_data_out <= wb_dat_i;
|
4'b0011: swapped_data_out <= wb_dat_i;
|
4'b1100: swapped_data_out <= {16'h0, wb_dat_i[31:16]};
|
4'b1100: swapped_data_out <= {16'h0, wb_dat_i[31:16]};
|
4'b0001: swapped_data_out <= wb_dat_i;
|
4'b0001: swapped_data_out <= wb_dat_i;
|
4'b0010: swapped_data_out <= {24'h0, wb_dat_i[15:8]};
|
4'b0010: swapped_data_out <= {24'h0, wb_dat_i[15:8]};
|
4'b0100: swapped_data_out <= {16'h0, wb_dat_i[31:16]};
|
4'b0100: swapped_data_out <= {16'h0, wb_dat_i[31:16]};
|
4'b1000: swapped_data_out <= {24'h0, wb_dat_i[31:24]};
|
4'b1000: swapped_data_out <= {24'h0, wb_dat_i[31:24]};
|
default: swapped_data_out <= wb_dat_i; // Shouldn't be possible
|
default: swapped_data_out <= wb_dat_i; // Shouldn't be possible
|
endcase
|
endcase
|
end
|
end
|
|
|
// WB->dbg data register
|
// WB->dbg data register
|
always @ (posedge wb_clk_i or posedge rst_i)
|
always @ (posedge wb_clk_i or posedge rst_i)
|
begin
|
begin
|
if(rst_i) data_out_reg <= 32'h0;
|
if(rst_i) data_out_reg <= 32'h0;
|
else if(data_o_en) data_out_reg <= swapped_data_out;
|
else if(data_o_en) data_out_reg <= swapped_data_out;
|
end
|
end
|
|
|
// Create a toggle-active ready signal to send to the TCK domain
|
// Create a toggle-active ready signal to send to the TCK domain
|
always @ (posedge wb_clk_i or posedge rst_i)
|
always @ (posedge wb_clk_i or posedge rst_i)
|
begin
|
begin
|
if(rst_i) rdy_sync <= 1'b0;
|
if(rst_i) rdy_sync <= 1'b0;
|
else if(rdy_sync_en) rdy_sync <= ~rdy_sync;
|
else if(rdy_sync_en) rdy_sync <= ~rdy_sync;
|
end
|
end
|
|
|
/////////////////////////////////////////////////////
|
/////////////////////////////////////////////////////
|
// Small state machine to create WB accesses
|
// Small state machine to create WB accesses
|
// Not much more that an 'in_progress' bit, but easier
|
// Not much more that an 'in_progress' bit, but easier
|
// to read. Deals with single-cycle and multi-cycle
|
// to read. Deals with single-cycle and multi-cycle
|
// accesses.
|
// accesses.
|
|
|
reg wb_fsm_state;
|
reg wb_fsm_state;
|
reg next_fsm_state;
|
reg next_fsm_state;
|
|
|
`define STATE_IDLE 1'h0
|
`define STATE_IDLE 1'h0
|
`define STATE_TRANSFER 1'h1
|
`define STATE_TRANSFER 1'h1
|
|
|
// Sequential bit
|
// Sequential bit
|
always @ (posedge wb_clk_i or posedge rst_i)
|
always @ (posedge wb_clk_i or posedge rst_i)
|
begin
|
begin
|
if(rst_i) wb_fsm_state <= `STATE_IDLE;
|
if(rst_i) wb_fsm_state <= `STATE_IDLE;
|
else wb_fsm_state <= next_fsm_state;
|
else wb_fsm_state <= next_fsm_state;
|
end
|
end
|
|
|
// Determination of next state (combinatorial)
|
// Determination of next state (combinatorial)
|
always @ (wb_fsm_state or start_toggle or wb_ack_i or wb_err_i)
|
always @ (wb_fsm_state or start_toggle or wb_ack_i or wb_err_i)
|
begin
|
begin
|
case (wb_fsm_state)
|
case (wb_fsm_state)
|
`STATE_IDLE:
|
`STATE_IDLE:
|
begin
|
begin
|
if(start_toggle && !(wb_ack_i || wb_err_i)) next_fsm_state <= `STATE_TRANSFER; // Don't go to next state for 1-cycle transfer
|
if(start_toggle && !(wb_ack_i || wb_err_i)) next_fsm_state <= `STATE_TRANSFER; // Don't go to next state for 1-cycle transfer
|
else next_fsm_state <= `STATE_IDLE;
|
else next_fsm_state <= `STATE_IDLE;
|
end
|
end
|
`STATE_TRANSFER:
|
`STATE_TRANSFER:
|
begin
|
begin
|
if(wb_ack_i || wb_err_i) next_fsm_state <= `STATE_IDLE;
|
if(wb_ack_i || wb_err_i) next_fsm_state <= `STATE_IDLE;
|
else next_fsm_state <= `STATE_TRANSFER;
|
else next_fsm_state <= `STATE_TRANSFER;
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
|
|
// Outputs of state machine (combinatorial)
|
// Outputs of state machine (combinatorial)
|
always @ (wb_fsm_state or start_toggle or wb_ack_i or wb_err_i or wr_reg)
|
always @ (wb_fsm_state or start_toggle or wb_ack_i or wb_err_i or wr_reg)
|
begin
|
begin
|
rdy_sync_en <= 1'b0;
|
rdy_sync_en <= 1'b0;
|
err_en <= 1'b0;
|
err_en <= 1'b0;
|
data_o_en <= 1'b0;
|
data_o_en <= 1'b0;
|
wb_cyc_o <= 1'b0;
|
wb_cyc_o <= 1'b0;
|
wb_stb_o <= 1'b0;
|
wb_stb_o <= 1'b0;
|
|
|
case (wb_fsm_state)
|
case (wb_fsm_state)
|
`STATE_IDLE:
|
`STATE_IDLE:
|
begin
|
begin
|
if(start_toggle) begin
|
if(start_toggle) begin
|
wb_cyc_o <= 1'b1;
|
wb_cyc_o <= 1'b1;
|
wb_stb_o <= 1'b1;
|
wb_stb_o <= 1'b1;
|
if(wb_ack_i || wb_err_i) begin
|
if(wb_ack_i || wb_err_i) begin
|
err_en <= 1'b1;
|
err_en <= 1'b1;
|
rdy_sync_en <= 1'b1;
|
rdy_sync_en <= 1'b1;
|
end
|
end
|
|
|
if (wb_ack_i && !wr_reg) begin
|
if (wb_ack_i && !wr_reg) begin
|
data_o_en <= 1'b1;
|
data_o_en <= 1'b1;
|
end
|
end
|
end
|
end
|
end
|
end
|
|
|
`STATE_TRANSFER:
|
`STATE_TRANSFER:
|
begin
|
begin
|
wb_cyc_o <= 1'b1;
|
wb_cyc_o <= 1'b1;
|
wb_stb_o <= 1'b1;
|
wb_stb_o <= 1'b1;
|
if(wb_ack_i) begin
|
if(wb_ack_i) begin
|
err_en <= 1'b1;
|
err_en <= 1'b1;
|
data_o_en <= 1'b1;
|
data_o_en <= 1'b1;
|
rdy_sync_en <= 1'b1;
|
rdy_sync_en <= 1'b1;
|
end
|
end
|
else if (wb_err_i) begin
|
else if (wb_err_i) begin
|
err_en <= 1'b1;
|
err_en <= 1'b1;
|
rdy_sync_en <= 1'b1;
|
rdy_sync_en <= 1'b1;
|
end
|
end
|
end
|
end
|
endcase
|
endcase
|
|
|
end
|
end
|
|
|
endmodule
|
endmodule
|
|
|
|
|