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COPYRIGHT
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COPYRIGHT
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Copyright (C) 2006 Shawn Tan Ser Ngiap .
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Copyright (C) 2006 Shawn Tan Ser Ngiap .
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Permission is granted to copy, distribute and/or modify this document
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Permission is granted to copy, distribute and/or modify this document
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under the terms of the GNU Free Documentation License, Version 1.2
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under the terms of the GNU Free Documentation License, Version 1.2
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or any later version published by the Free Software Foundation;
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or any later version published by the Free Software Foundation;
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with no Invariant Sections, no Front-Cover Texts, and no Back-Cover Texts.
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with no Invariant Sections, no Front-Cover Texts, and no Back-Cover Texts.
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A copy of the license is included in the section entitled "GNU
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A copy of the license is included in the section entitled "GNU
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Free Documentation License".
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Free Documentation License".
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INTRODUCTION
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INTRODUCTION
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The AE18 is a clean room implementation of a PIC18 software compatible core.
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The AE18 is a clean room implementation of a PIC18 software compatible core.
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It is developed using publicly available documentation and tools. It is not
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It is developed using publicly available documentation and tools. It is not
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architecturally compatible. Major differences are noted in the section below.
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architecturally compatible. Major differences are noted in the section below.
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NON-STANDARD FEATURES
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NON-STANDARD FEATURES
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There are some things that are implemented in a non standard way from the
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There are some things that are implemented in a non standard way from the
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PIC18. These are mainly minor issues that should not affect normal software
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PIC18. These are mainly minor issues that should not affect normal software
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implementations. However, in certain cases, some software might need to be
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implementations. However, in certain cases, some software might need to be
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modified to ensure correct operation.
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modified to ensure correct operation.
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1) Watch Dog Timer
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1) Watch Dog Timer
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The WDT is enabled by default. As there is no way to set any config bits for
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The WDT is enabled by default. As there is no way to set any config bits for
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this core, the ONLY way to disable it is by clearing the SWDTEN bit in the
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this core, the ONLY way to disable it is by clearing the SWDTEN bit in the
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WDTCON register.
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WDTCON register.
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2) Other Timers
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2) Other Timers
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The other timers found standard on a PIC18 are NOT included with the AE18
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The other timers found standard on a PIC18 are NOT included with the AE18
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core. These timers can all be built as external peripherals and attached to
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core. These timers can all be built as external peripherals and attached to
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the data bus of the AE18.
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the data bus of the AE18.
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3) Other Peripherals
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3) Other Peripherals
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The AE18 core DOES NOT include any I/O devices or peripherals with the core.
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The AE18 core DOES NOT include any I/O devices or peripherals with the core.
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However, it is WISHBONE compliant and can be included in a larger SoC with
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However, it is WISHBONE compliant and can be included in a larger SoC with
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suitable I/O devices and peripherals included.
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suitable I/O devices and peripherals included.
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4) External Interrupts
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4) External Interrupts
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The AE18 has the built in facility to handle external interrupts. However,
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The AE18 has the built in facility to handle external interrupts. However,
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the interrupt controller is not included in the core and will need to be
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the interrupt controller is not included in the core and will need to be
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attached to the data bus as an external device.
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attached to the data bus as an external device.
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The INT_I[1:0] and INTE_I[1:0] inputs are used to indicate high/low interrupt
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The INT_I[1:0] and INTE_I[1:0] inputs are used to indicate high/low interrupt
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sources and enables. The external interrupts are all positive edge triggered.
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sources and enables. The external interrupts are all positive edge triggered.
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On an interrupt, the PC will branch directly to the correct vectors.
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On an interrupt, the PC will branch directly to the correct vectors.
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NON-IMPLEMENTED FEATURES
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NON-IMPLEMENTED FEATURES
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There are a few PIC18 features that are non implemented. These include some
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There are a few PIC18 features that are non implemented. These include some
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SFR and some architectural features. These need to be carefully noted as
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SFR and some architectural features. These need to be carefully noted as
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they will require some minor software changes to ensure correct operation.
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they will require some minor software changes to ensure correct operation.
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1) SFR Non Implemented
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1) SFR Non Implemented
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Some SFR are not implemented. Any attempt to read/write these SFR will not
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Some SFR are not implemented. Any attempt to read/write these SFR will not
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work correctly. These SFR should not be accessed at all.
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work correctly. These SFR should not be accessed at all.
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a) RCON
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a) RCON
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Does not make sense as the only source of reset is EXTERNAL/WDT/RESET.
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Does not make sense as the only source of reset is EXTERNAL/WDT/RESET.
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b) OSCCON/LVDCON
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b) OSCCON/LVDCON
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Does not include a simple way to implement these features in an FPGA.
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Does not include a simple way to implement these features in an FPGA.
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c) INTCON,INTCON2,INTCON3
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c) INTCON,INTCON2,INTCON3
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Not implemented as it depends on external devices.
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Not implemented as it depends on external devices.
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d) ALL peripheral registers
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d) ALL peripheral registers
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These will need to be implemented in each external device.
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These will need to be implemented in each external device.
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2) Important Notes
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2) Important Notes
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a) SLEEP
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a) SLEEP
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This instruction should always be followed by two NOP instructions.
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This instruction should always be followed by two NOP instructions.
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b) DAW
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b) DAW
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This instruction has not been implemented yet.
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This instruction has not been implemented yet.
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c) ACCESS BANK
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c) ACCESS BANK
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The data memory space for SFR has been moved to 0xFF80 and above.
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The data memory space for SFR has been moved to 0xFF80 and above.
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USAGE
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USAGE
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Some software and scripts have been included with the core. These are to assist
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Some software and scripts have been included with the core. These are to assist
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in the simulation and verification of the AE18.
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in the simulation and verification of the AE18.
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1) Simulation
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1) Simulation
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For the purpose of software simulation, the core has been extensively tested
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For the purpose of software simulation, the core has been extensively tested
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using sample test software. The test software is included in the /sw directory.
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using sample test software. The test software is included in the /sw directory.
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The assembly file is compiled using GPASM 0.13.4. The resulting code has been
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The assembly file is compiled using GPASM 0.13.4. The resulting code has been
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simulated using Icarus Verilog 0.8.2 and GPLCVER 2.11a.
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simulated using Icarus Verilog 0.8.2 and GPLCVER 2.11a.
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Sample simulation scripts have been included for both cver and iverilog. These
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Sample simulation scripts have been included for both cver and iverilog. These
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scripts are located in the /sim directory. When running the included testbench
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scripts are located in the /sim directory. When running the included testbench
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software (ae18_core.asm), the core should echo "Test response OK!" if it
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software (ae18_core.asm), the core should echo "Test response OK!" if it
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passed all the tests in the software.
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passed all the tests in the software.
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2) Implementation
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2) Implementation
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The specifics of implementation will depend on the toolset used by the vendor.
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The specifics of implementation will depend on the toolset used by the vendor.
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However, the main point to note is memory implementation. The instruction
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However, the main point to note is memory implementation. The instruction
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memory can be implemented as either on-chip or external memory.
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memory can be implemented as either on-chip or external memory.
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FINAL NOTES
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FINAL NOTES
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Although every care has been taken to test the core, there is no guarantee that
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Although every care has been taken to test the core, there is no guarantee that
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the AE18 core is compatible with the PIC18. If you wish to use this core in
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the AE18 core is compatible with the PIC18. If you wish to use this core in
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production, please test the application thoroughly first.
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production, please test the application thoroughly first.
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1) TODO
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1) TODO
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- Tidy up the code and split it into manageable chunks.
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- Tidy up the code and split it into manageable chunks.
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- Optimise many of the parts (mainly PC and EA calculators).
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- Optimise many of the parts (mainly PC and EA calculators).
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CONTACT INFORMATION
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CONTACT INFORMATION
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Author : Shawn Tan
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Author : Shawn Tan
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Email : shawn.tan@aeste.net
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Email : shawn.tan@aeste.net
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Website : www.aeste.net
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Website : www.aeste.net
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Please do not hesitate to contact me if you use this core in any of your
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Please do not hesitate to contact me if you use this core in any of your
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