/* $Id: aeMB2_bpcu.v,v 1.5 2007-12-21 22:39:38 sybreon Exp $
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/* $Id: aeMB2_bpcu.v,v 1.5 2007-12-21 22:39:38 sybreon Exp $
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**
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**
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** AEMB2 BRANCH/PROGRAMME COUNTER
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** AEMB2 BRANCH/PROGRAMME COUNTER
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**
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**
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** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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**
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**
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** This file is part of AEMB.
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** This file is part of AEMB.
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**
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**
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** AEMB is free software: you can redistribute it and/or modify it
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** AEMB is free software: you can redistribute it and/or modify it
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** under the terms of the GNU Lesser General Public License as
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** under the terms of the GNU Lesser General Public License as
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** published by the Free Software Foundation, either version 3 of the
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** published by the Free Software Foundation, either version 3 of the
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** License, or (at your option) any later version.
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** License, or (at your option) any later version.
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**
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**
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** AEMB is distributed in the hope that it will be useful, but WITHOUT
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** AEMB is distributed in the hope that it will be useful, but WITHOUT
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** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General
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** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General
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** Public License for more details.
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** Public License for more details.
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**
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**
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** You should have received a copy of the GNU Lesser General Public
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** You should have received a copy of the GNU Lesser General Public
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** License along with AEMB. If not, see <http://www.gnu.org/licenses/>.
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** License along with AEMB. If not, see <http://www.gnu.org/licenses/>.
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*/
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*/
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module aeMB2_bpcu (/*AUTOARG*/
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module aeMB2_bpcu (/*AUTOARG*/
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// Outputs
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// Outputs
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iwb_adr_o, rPC_MA, rPC_IF, rIMM_IF, rALT_IF, rOPC_IF, rRD_IF,
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iwb_adr_o, rPC_MA, rPC_IF, rIMM_IF, rALT_IF, rOPC_IF, rRD_IF,
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rRA_IF, rRB_IF, rBRA,
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rRA_IF, rRB_IF, rBRA,
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// Inputs
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// Inputs
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iwb_dat_i, iwb_ack_i, rOPX_OF, rOPC_OF, rRA_OF, rRD_OF, rRES_EX,
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iwb_dat_i, iwb_ack_i, rOPX_OF, rOPC_OF, rRA_OF, rRD_OF, rRES_EX,
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rRD_EX, rOPD_EX, clk_i, rst_i, ena_i, pha_i
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rRD_EX, rOPD_EX, clk_i, rst_i, ena_i, pha_i
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);
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);
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parameter IWB = 32;
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parameter IWB = 32;
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parameter TXE = 1;
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parameter TXE = 1;
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// IWB
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// IWB
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output [IWB-1:2] iwb_adr_o;
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output [IWB-1:2] iwb_adr_o;
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input [31:0] iwb_dat_i;
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input [31:0] iwb_dat_i;
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input iwb_ack_i;
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input iwb_ack_i;
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// PIPELINE
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// PIPELINE
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output [31:2] //rPC_OF,
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output [31:2] //rPC_OF,
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rPC_MA,
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rPC_MA,
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rPC_IF;
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rPC_IF;
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output [15:0] rIMM_IF;
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output [15:0] rIMM_IF;
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output [10:0] rALT_IF;
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output [10:0] rALT_IF;
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output [5:0] rOPC_IF;
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output [5:0] rOPC_IF;
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output [4:0] rRD_IF,
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output [4:0] rRD_IF,
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rRA_IF,
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rRA_IF,
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rRB_IF;
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rRB_IF;
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// BRANCH DETECTION
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// BRANCH DETECTION
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output [1:0] rBRA; // {branch, delay}
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output [1:0] rBRA; // {branch, delay}
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input [31:0] rOPX_OF; // BCC op test
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input [31:0] rOPX_OF; // BCC op test
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input [5:0] rOPC_OF;
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input [5:0] rOPC_OF;
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input [4:0] rRA_OF,
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input [4:0] rRA_OF,
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rRD_OF;
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rRD_OF;
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input [31:0] rRES_EX;
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input [31:0] rRES_EX;
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// MEMORY HAZARD DETECTION
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// MEMORY HAZARD DETECTION
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input [4:0] rRD_EX; ///< RD
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input [4:0] rRD_EX; ///< RD
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input [2:0] rOPD_EX; ///< data register source (ALU, MEM/FSL, PC)
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input [2:0] rOPD_EX; ///< data register source (ALU, MEM/FSL, PC)
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// SYSTEM
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// SYSTEM
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input clk_i,
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input clk_i,
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rst_i,
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rst_i,
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ena_i,
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ena_i,
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pha_i;
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pha_i;
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/*AUTOREG*/
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/*AUTOREG*/
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// Beginning of automatic regs (for this module's undeclared outputs)
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// Beginning of automatic regs (for this module's undeclared outputs)
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reg [1:0] rBRA;
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reg [1:0] rBRA;
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reg [15:0] rIMM_IF;
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reg [15:0] rIMM_IF;
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reg [5:0] rOPC_IF;
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reg [5:0] rOPC_IF;
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reg [31:2] rPC_IF;
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reg [31:2] rPC_IF;
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reg [31:2] rPC_MA;
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reg [31:2] rPC_MA;
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reg [4:0] rRA_IF;
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reg [4:0] rRA_IF;
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reg [4:0] rRD_IF;
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reg [4:0] rRD_IF;
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// End of automatics
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// End of automatics
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/* Partial decoding */
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/* Partial decoding */
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wire [5:0] rOPC = rOPC_IF;
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wire [5:0] rOPC = rOPC_IF;
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wire [4:0] rRA = rRA_IF;
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wire [4:0] rRA = rRA_IF;
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wire [4:0] rRB = rRB_IF;
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wire [4:0] rRB = rRB_IF;
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wire fSFT = (rOPC == 6'o44);
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wire fSFT = (rOPC == 6'o44);
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wire fLOG = ({rOPC[5:4],rOPC[2]} == 3'o4);
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wire fLOG = ({rOPC[5:4],rOPC[2]} == 3'o4);
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wire fMUL = (rOPC == 6'o20) | (rOPC == 6'o30);
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wire fMUL = (rOPC == 6'o20) | (rOPC == 6'o30);
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wire fBSF = (rOPC == 6'o21) | (rOPC == 6'o31);
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wire fBSF = (rOPC == 6'o21) | (rOPC == 6'o31);
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wire fDIV = (rOPC == 6'o22);
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wire fDIV = (rOPC == 6'o22);
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wire fRTD = (rOPC == 6'o55);
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wire fRTD = (rOPC == 6'o55);
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wire fBCC = (rOPC == 6'o47) | (rOPC == 6'o57);
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wire fBCC = (rOPC == 6'o47) | (rOPC == 6'o57);
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wire fBRU = (rOPC == 6'o46) | (rOPC == 6'o56);
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wire fBRU = (rOPC == 6'o46) | (rOPC == 6'o56);
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wire fBRA = fBRU & rRA[3];
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wire fBRA = fBRU & rRA[3];
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wire fIMM = (rOPC == 6'o54);
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wire fIMM = (rOPC == 6'o54);
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wire fMOV = (rOPC == 6'o45);
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wire fMOV = (rOPC == 6'o45);
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wire fLOD = ({rOPC[5:4],rOPC[2]} == 3'o6);
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wire fLOD = ({rOPC[5:4],rOPC[2]} == 3'o6);
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wire fSTR = ({rOPC[5:4],rOPC[2]} == 3'o7);
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wire fSTR = ({rOPC[5:4],rOPC[2]} == 3'o7);
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wire fLDST = (rOPC[5:4] == 2'o3);
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wire fLDST = (rOPC[5:4] == 2'o3);
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wire fPUT = (rOPC == 6'o33) & rRB[4];
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wire fPUT = (rOPC == 6'o33) & rRB[4];
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wire fGET = (rOPC == 6'o33) & !rRB[4];
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wire fGET = (rOPC == 6'o33) & !rRB[4];
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/* Select the PC. */
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/* Select the PC. */
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reg [31:2] rPC, // PC
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reg [31:2] rPC, // PC
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rPC0, rPC1,// register based
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rPC0, rPC1,// register based
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rPCL[0:1]; // LUT based
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rPCL[0:1]; // LUT based
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wire [31:2] wPCNXT = (pha_i | !TXE) ? rPC0 : rPC1;
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wire [31:2] wPCNXT = (pha_i | !TXE) ? rPC0 : rPC1;
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wire [31:2] wPCINC = (rPC + 1);
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wire [31:2] wPCINC = (rPC + 1);
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/* Check for RW data hazard */
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/* Check for RW data hazard */
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// TODO: Optimise
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// TODO: Optimise
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wire fLOAD = (rOPD_EX == 3'o2);
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wire fLOAD = (rOPD_EX == 3'o2);
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wire fMULT = (rOPD_EX == 3'o3);
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wire fMULT = (rOPD_EX == 3'o3);
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wire fWRE = |rRD_EX;
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wire fWRE = |rRD_EX;
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wire fOPBHZD = (rRB_IF == rRD_EX) & (fLOAD | fMULT) & !fMOV & !rOPC_IF[3] & fWRE;
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wire fOPBHZD = (rRB_IF == rRD_EX) & (fLOAD | fMULT) & !fMOV & !rOPC_IF[3] & fWRE;
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wire fOPAHZD = (rRA_IF == rRD_EX) & (fLOAD | fMULT) & !fBRU & fWRE;
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wire fOPAHZD = (rRA_IF == rRD_EX) & (fLOAD | fMULT) & !fBRU & fWRE;
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wire fOPDHZD = (rRD_IF == rRD_EX) & (fLOAD | fMULT) & fSTR & fWRE;
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wire fOPDHZD = (rRD_IF == rRD_EX) & (fLOAD | fMULT) & fSTR & fWRE;
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wire fHZD = (fOPBHZD | fOPAHZD | fOPDHZD) & !rBRA[1];
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wire fHZD = (fOPBHZD | fOPAHZD | fOPDHZD) & !rBRA[1];
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/*
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/*
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IWB PC OUTPUT
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IWB PC OUTPUT
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This is part of the address generation stage. It pre-selects the
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This is part of the address generation stage. It pre-selects the
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next PC to fetch depending on whether it's a branch, retry or
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next PC to fetch depending on whether it's a branch, retry or
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normal. A retry happens during a special hazard */
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normal. A retry happens during a special hazard */
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wire [1:0] wIPCMX = {fHZD, rBRA[1]};
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wire [1:0] wIPCMX = {fHZD, rBRA[1]};
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assign iwb_adr_o = rPC[IWB-1:2];
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assign iwb_adr_o = rPC[IWB-1:2];
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always @ (posedge clk_i)
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always @ (posedge clk_i)
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if (rst_i) begin
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if (rst_i) begin
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rPC <= {(30){1'b1}};
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rPC <= {(30){1'b1}};
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/*AUTORESET*/
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/*AUTORESET*/
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end else if (ena_i) begin
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end else if (ena_i) begin
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case (wIPCMX)
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case (wIPCMX)
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2'o0 : rPC <= #1 wPCNXT[IWB-1:2]; // normal
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2'o0 : rPC <= #1 wPCNXT[IWB-1:2]; // normal
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2'o1 : rPC <= #1 rRES_EX[IWB-1:2]; // branch/return/break
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2'o1 : rPC <= #1 rRES_EX[IWB-1:2]; // branch/return/break
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2'o2 : rPC <= #1 rPC_IF[IWB-1:2]; // retry/stall
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2'o2 : rPC <= #1 rPC_IF[IWB-1:2]; // retry/stall
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default: rPC <= {(IWB-2){1'bX}}; // undefined
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default: rPC <= {(IWB-2){1'bX}}; // undefined
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endcase // case (wIPCMX)
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endcase // case (wIPCMX)
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end
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end
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/*
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/*
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PC INCREMENT
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PC INCREMENT
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This will store the next PC in a holding register until it is
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This will store the next PC in a holding register until it is
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needed during the next AG stage. */
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needed during the next AG stage. */
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always @(posedge clk_i)
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always @(posedge clk_i)
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if (rst_i) begin
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if (rst_i) begin
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/*AUTORESET*/
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/*AUTORESET*/
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// Beginning of autoreset for uninitialized flops
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// Beginning of autoreset for uninitialized flops
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rPC0 <= 30'h0;
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rPC0 <= 30'h0;
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rPC1 <= 30'h0;
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rPC1 <= 30'h0;
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// End of automatics
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// End of automatics
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end else if (ena_i) begin
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end else if (ena_i) begin
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if (pha_i)
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if (pha_i)
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rPC1 <= #1 wPCINC;
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rPC1 <= #1 wPCINC;
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else
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else
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rPC0 <= #1 wPCINC;
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rPC0 <= #1 wPCINC;
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end
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end
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/*
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/*
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INSTRUCTION LATCH
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INSTRUCTION LATCH
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This latches onto the instruction. It may not work correctly if
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This latches onto the instruction. It may not work correctly if
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there is a pipeline stall. */
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there is a pipeline stall. */
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reg [31:2] rPC_OF, rPC_EX;
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reg [31:2] rPC_OF, rPC_EX;
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assign {rRB_IF, rALT_IF} = rIMM_IF;
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assign {rRB_IF, rALT_IF} = rIMM_IF;
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always @(posedge clk_i)
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always @(posedge clk_i)
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if (rst_i) begin
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if (rst_i) begin
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/*AUTORESET*/
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/*AUTORESET*/
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// Beginning of autoreset for uninitialized flops
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// Beginning of autoreset for uninitialized flops
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rIMM_IF <= 16'h0;
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rIMM_IF <= 16'h0;
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rOPC_IF <= 6'h0;
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rOPC_IF <= 6'h0;
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rRA_IF <= 5'h0;
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rRA_IF <= 5'h0;
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rRD_IF <= 5'h0;
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rRD_IF <= 5'h0;
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// End of automatics
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// End of automatics
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end else if (ena_i & iwb_ack_i) begin
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end else if (ena_i & iwb_ack_i) begin
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{rOPC_IF, rRD_IF, rRA_IF, rIMM_IF} <= #1 iwb_dat_i;
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{rOPC_IF, rRD_IF, rRA_IF, rIMM_IF} <= #1 iwb_dat_i;
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end
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end
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/*
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/*
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PC PIPELINE
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PC PIPELINE
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This merely passes the PC down so that it is available during
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This merely passes the PC down so that it is available during
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branch instructions. This may be modified to use a shift register.
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branch instructions. This may be modified to use a shift register.
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*/
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*/
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always @(posedge clk_i) if (rst_i) begin
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always @(posedge clk_i) if (rst_i) begin
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/*AUTORESET*/
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/*AUTORESET*/
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// Beginning of autoreset for uninitialized flops
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// Beginning of autoreset for uninitialized flops
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rPC_EX <= 30'h0;
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rPC_EX <= 30'h0;
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rPC_IF <= 30'h0;
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rPC_IF <= 30'h0;
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rPC_MA <= 30'h0;
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rPC_MA <= 30'h0;
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rPC_OF <= 30'h0;
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rPC_OF <= 30'h0;
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// End of automatics
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// End of automatics
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end else if (ena_i) begin
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end else if (ena_i) begin
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// TODO: Stuff inside a small LUT FIFO
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// TODO: Stuff inside a small LUT FIFO
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{rPC_MA, rPC_EX, rPC_OF, rPC_IF} <= #1 {rPC_EX, rPC_OF, rPC_IF, rPC};
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{rPC_MA, rPC_EX, rPC_OF, rPC_IF} <= #1 {rPC_EX, rPC_OF, rPC_IF, rPC};
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end
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end
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/* Branch Control */
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/* Branch Control */
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wire wRTD = (rOPC_OF == 6'o55);
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wire wRTD = (rOPC_OF == 6'o55);
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wire wBCC = (rOPC_OF == 6'o47) | (rOPC_OF == 6'o57);
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wire wBCC = (rOPC_OF == 6'o47) | (rOPC_OF == 6'o57);
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wire wBRU = (rOPC_OF == 6'o46) | (rOPC_OF == 6'o56);
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wire wBRU = (rOPC_OF == 6'o46) | (rOPC_OF == 6'o56);
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wire wBEQ = (rOPX_OF == 32'd0);
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wire wBEQ = (rOPX_OF == 32'd0);
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wire wBNE = ~wBEQ;
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wire wBNE = ~wBEQ;
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wire wBLT = rOPX_OF[31];
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wire wBLT = rOPX_OF[31];
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wire wBLE = wBLT | wBEQ;
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wire wBLE = wBLT | wBEQ;
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wire wBGE = ~wBLT;
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wire wBGE = ~wBLT;
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wire wBGT = ~wBLE;
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wire wBGT = ~wBLE;
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reg xXCC;
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reg xXCC;
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always @(/*AUTOSENSE*/rRD_OF or wBEQ or wBGE or wBGT or wBLE
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always @(/*AUTOSENSE*/rRD_OF or wBEQ or wBGE or wBGT or wBLE
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or wBLT or wBNE)
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or wBLT or wBNE)
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case (rRD_OF[2:0])
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case (rRD_OF[2:0])
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3'o0: xXCC <= wBEQ;
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3'o0: xXCC <= wBEQ;
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3'o1: xXCC <= wBNE;
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3'o1: xXCC <= wBNE;
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3'o2: xXCC <= wBLT;
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3'o2: xXCC <= wBLT;
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3'o3: xXCC <= wBLE;
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3'o3: xXCC <= wBLE;
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3'o4: xXCC <= wBGT;
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3'o4: xXCC <= wBGT;
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3'o5: xXCC <= wBGE;
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3'o5: xXCC <= wBGE;
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default: xXCC <= 1'bX;
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default: xXCC <= 1'bX;
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endcase // case (rRD_OF[2:0])
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endcase // case (rRD_OF[2:0])
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always @(posedge clk_i)
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always @(posedge clk_i)
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if (rst_i) begin
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if (rst_i) begin
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/*AUTORESET*/
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/*AUTORESET*/
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// Beginning of autoreset for uninitialized flops
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// Beginning of autoreset for uninitialized flops
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rBRA <= 2'h0;
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rBRA <= 2'h0;
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// End of automatics
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// End of automatics
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end else if(ena_i) begin
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end else if(ena_i) begin
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rBRA[1] <= #1 wRTD | wBRU | (wBCC & xXCC);
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rBRA[1] <= #1 wRTD | wBRU | (wBCC & xXCC);
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rBRA[0] <= #1 (wBRU & rRA_OF[4]) | (wBCC & rRD_OF[4]) | wRTD;
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rBRA[0] <= #1 (wBRU & rRA_OF[4]) | (wBCC & rRD_OF[4]) | wRTD;
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end
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end
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endmodule // aeMB2_bpcu
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endmodule // aeMB2_bpcu
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/* $Log: not supported by cvs2svn $
|
/* $Log: not supported by cvs2svn $
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/* Revision 1.4 2007/12/17 12:53:43 sybreon
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/* Revision 1.4 2007/12/17 12:53:43 sybreon
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/* Made idle thread PC track main PC.
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/* Made idle thread PC track main PC.
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/*
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/*
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/* Revision 1.3 2007/12/13 20:12:11 sybreon
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/* Revision 1.3 2007/12/13 20:12:11 sybreon
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/* Code cleanup + minor speed regression.
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/* Code cleanup + minor speed regression.
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/*
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/*
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/* Revision 1.2 2007/12/12 19:16:59 sybreon
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/* Revision 1.2 2007/12/12 19:16:59 sybreon
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/* Minor optimisations (~10% faster)
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/* Minor optimisations (~10% faster)
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/*
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/*
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/* Revision 1.1 2007/12/11 00:43:17 sybreon
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/* Revision 1.1 2007/12/11 00:43:17 sybreon
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/* initial import
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/* initial import
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