/* $Id: aeMB_edk32.v,v 1.14 2008-01-19 16:01:22 sybreon Exp $
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/* $Id: aeMB_edk32.v,v 1.14 2008-01-19 16:01:22 sybreon Exp $
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**
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**
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** AEMB EDK 3.2 Compatible Core
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** AEMB EDK 3.2 Compatible Core
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** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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**
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**
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** This file is part of AEMB.
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** This file is part of AEMB.
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**
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**
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** AEMB is free software: you can redistribute it and/or modify it
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** AEMB is free software: you can redistribute it and/or modify it
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** under the terms of the GNU Lesser General Public License as
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** under the terms of the GNU Lesser General Public License as
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** published by the Free Software Foundation, either version 3 of the
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** published by the Free Software Foundation, either version 3 of the
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** License, or (at your option) any later version.
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** License, or (at your option) any later version.
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**
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**
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** AEMB is distributed in the hope that it will be useful, but WITHOUT
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** AEMB is distributed in the hope that it will be useful, but WITHOUT
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** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General
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** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General
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** Public License for more details.
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** Public License for more details.
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**
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**
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** You should have received a copy of the GNU Lesser General Public
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** You should have received a copy of the GNU Lesser General Public
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** License along with AEMB. If not, see <http://www.gnu.org/licenses/>.
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** License along with AEMB. If not, see <http://www.gnu.org/licenses/>.
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*/
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*/
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module aeMB_edk32 (/*AUTOARG*/
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module aeMB_edk32 (/*AUTOARG*/
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// Outputs
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// Outputs
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iwb_stb_o, iwb_adr_o, fsl_wre_o, fsl_tag_o, fsl_stb_o, fsl_dat_o,
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iwb_stb_o, iwb_adr_o, fsl_wre_o, fsl_tag_o, fsl_stb_o, fsl_dat_o,
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fsl_adr_o, dwb_wre_o, dwb_stb_o, dwb_sel_o, dwb_dat_o, dwb_adr_o,
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fsl_adr_o, dwb_wre_o, dwb_stb_o, dwb_sel_o, dwb_dat_o, dwb_adr_o,
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// Inputs
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// Inputs
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sys_int_i, iwb_dat_i, iwb_ack_i, fsl_dat_i, fsl_ack_i, dwb_dat_i,
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sys_int_i, iwb_dat_i, iwb_ack_i, fsl_dat_i, fsl_ack_i, dwb_dat_i,
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dwb_ack_i, sys_clk_i, sys_rst_i
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dwb_ack_i, sys_clk_i, sys_rst_i
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);
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);
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// Bus widths
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// Bus widths
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parameter IW = 32; /// Instruction bus address width
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parameter IW = 32; /// Instruction bus address width
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parameter DW = 32; /// Data bus address width
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parameter DW = 32; /// Data bus address width
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// Optional functions
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// Optional functions
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parameter MUL = 0; // Multiplier
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parameter MUL = 0; // Multiplier
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parameter BSF = 1; // Barrel Shifter
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parameter BSF = 1; // Barrel Shifter
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/*AUTOOUTPUT*/
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/*AUTOOUTPUT*/
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// Beginning of automatic outputs (from unused autoinst outputs)
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// Beginning of automatic outputs (from unused autoinst outputs)
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output [DW-1:2] dwb_adr_o; // From xecu of aeMB_xecu.v
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output [DW-1:2] dwb_adr_o; // From xecu of aeMB_xecu.v
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output [31:0] dwb_dat_o; // From regf of aeMB_regf.v
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output [31:0] dwb_dat_o; // From regf of aeMB_regf.v
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output [3:0] dwb_sel_o; // From xecu of aeMB_xecu.v
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output [3:0] dwb_sel_o; // From xecu of aeMB_xecu.v
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output dwb_stb_o; // From ctrl of aeMB_ctrl.v
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output dwb_stb_o; // From ctrl of aeMB_ctrl.v
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output dwb_wre_o; // From ctrl of aeMB_ctrl.v
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output dwb_wre_o; // From ctrl of aeMB_ctrl.v
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output [6:2] fsl_adr_o; // From xecu of aeMB_xecu.v
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output [6:2] fsl_adr_o; // From xecu of aeMB_xecu.v
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output [31:0] fsl_dat_o; // From regf of aeMB_regf.v
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output [31:0] fsl_dat_o; // From regf of aeMB_regf.v
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output fsl_stb_o; // From ctrl of aeMB_ctrl.v
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output fsl_stb_o; // From ctrl of aeMB_ctrl.v
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output [1:0] fsl_tag_o; // From xecu of aeMB_xecu.v
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output [1:0] fsl_tag_o; // From xecu of aeMB_xecu.v
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output fsl_wre_o; // From ctrl of aeMB_ctrl.v
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output fsl_wre_o; // From ctrl of aeMB_ctrl.v
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output [IW-1:2] iwb_adr_o; // From bpcu of aeMB_bpcu.v
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output [IW-1:2] iwb_adr_o; // From bpcu of aeMB_bpcu.v
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output iwb_stb_o; // From ibuf of aeMB_ibuf.v
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output iwb_stb_o; // From ibuf of aeMB_ibuf.v
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// End of automatics
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// End of automatics
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/*AUTOINPUT*/
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/*AUTOINPUT*/
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// Beginning of automatic inputs (from unused autoinst inputs)
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// Beginning of automatic inputs (from unused autoinst inputs)
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input dwb_ack_i; // To ctrl of aeMB_ctrl.v
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input dwb_ack_i; // To ctrl of aeMB_ctrl.v
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input [31:0] dwb_dat_i; // To regf of aeMB_regf.v
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input [31:0] dwb_dat_i; // To regf of aeMB_regf.v
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input fsl_ack_i; // To ctrl of aeMB_ctrl.v
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input fsl_ack_i; // To ctrl of aeMB_ctrl.v
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input [31:0] fsl_dat_i; // To regf of aeMB_regf.v
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input [31:0] fsl_dat_i; // To regf of aeMB_regf.v
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input iwb_ack_i; // To ibuf of aeMB_ibuf.v, ...
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input iwb_ack_i; // To ibuf of aeMB_ibuf.v, ...
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input [31:0] iwb_dat_i; // To ibuf of aeMB_ibuf.v
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input [31:0] iwb_dat_i; // To ibuf of aeMB_ibuf.v
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input sys_int_i; // To ibuf of aeMB_ibuf.v
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input sys_int_i; // To ibuf of aeMB_ibuf.v
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// End of automatics
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// End of automatics
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/*AUTOWIRE*/
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire [10:0] rALT; // From ibuf of aeMB_ibuf.v
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wire [10:0] rALT; // From ibuf of aeMB_ibuf.v
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wire rBRA; // From bpcu of aeMB_bpcu.v
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wire rBRA; // From bpcu of aeMB_bpcu.v
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wire rDLY; // From bpcu of aeMB_bpcu.v
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wire rDLY; // From bpcu of aeMB_bpcu.v
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wire [31:0] rDWBDI; // From regf of aeMB_regf.v
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wire [31:0] rDWBDI; // From regf of aeMB_regf.v
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wire [3:0] rDWBSEL; // From xecu of aeMB_xecu.v
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wire [3:0] rDWBSEL; // From xecu of aeMB_xecu.v
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wire [15:0] rIMM; // From ibuf of aeMB_ibuf.v
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wire [15:0] rIMM; // From ibuf of aeMB_ibuf.v
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wire rMSR_BIP; // From xecu of aeMB_xecu.v
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wire rMSR_BIP; // From xecu of aeMB_xecu.v
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wire rMSR_IE; // From xecu of aeMB_xecu.v
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wire rMSR_IE; // From xecu of aeMB_xecu.v
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wire [1:0] rMXALT; // From ctrl of aeMB_ctrl.v
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wire [1:0] rMXALT; // From ctrl of aeMB_ctrl.v
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wire [2:0] rMXALU; // From ctrl of aeMB_ctrl.v
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wire [2:0] rMXALU; // From ctrl of aeMB_ctrl.v
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wire [1:0] rMXDST; // From ctrl of aeMB_ctrl.v
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wire [1:0] rMXDST; // From ctrl of aeMB_ctrl.v
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wire [1:0] rMXSRC; // From ctrl of aeMB_ctrl.v
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wire [1:0] rMXSRC; // From ctrl of aeMB_ctrl.v
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wire [1:0] rMXTGT; // From ctrl of aeMB_ctrl.v
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wire [1:0] rMXTGT; // From ctrl of aeMB_ctrl.v
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wire [5:0] rOPC; // From ibuf of aeMB_ibuf.v
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wire [5:0] rOPC; // From ibuf of aeMB_ibuf.v
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wire [31:2] rPC; // From bpcu of aeMB_bpcu.v
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wire [31:2] rPC; // From bpcu of aeMB_bpcu.v
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wire [31:2] rPCLNK; // From bpcu of aeMB_bpcu.v
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wire [31:2] rPCLNK; // From bpcu of aeMB_bpcu.v
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wire [4:0] rRA; // From ibuf of aeMB_ibuf.v
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wire [4:0] rRA; // From ibuf of aeMB_ibuf.v
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wire [4:0] rRB; // From ibuf of aeMB_ibuf.v
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wire [4:0] rRB; // From ibuf of aeMB_ibuf.v
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wire [4:0] rRD; // From ibuf of aeMB_ibuf.v
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wire [4:0] rRD; // From ibuf of aeMB_ibuf.v
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wire [31:0] rREGA; // From regf of aeMB_regf.v
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wire [31:0] rREGA; // From regf of aeMB_regf.v
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wire [31:0] rREGB; // From regf of aeMB_regf.v
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wire [31:0] rREGB; // From regf of aeMB_regf.v
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wire [31:0] rRESULT; // From xecu of aeMB_xecu.v
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wire [31:0] rRESULT; // From xecu of aeMB_xecu.v
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wire [4:0] rRW; // From ctrl of aeMB_ctrl.v
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wire [4:0] rRW; // From ctrl of aeMB_ctrl.v
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wire [31:0] rSIMM; // From ibuf of aeMB_ibuf.v
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wire [31:0] rSIMM; // From ibuf of aeMB_ibuf.v
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wire rSTALL; // From ibuf of aeMB_ibuf.v
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wire rSTALL; // From ibuf of aeMB_ibuf.v
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wire [31:0] xIREG; // From ibuf of aeMB_ibuf.v
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wire [31:0] xIREG; // From ibuf of aeMB_ibuf.v
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// End of automatics
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// End of automatics
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input sys_clk_i;
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input sys_clk_i;
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input sys_rst_i;
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input sys_rst_i;
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wire grst = sys_rst_i;
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wire grst = sys_rst_i;
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wire gclk = sys_clk_i;
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wire gclk = sys_clk_i;
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wire gena = !((dwb_stb_o ^ dwb_ack_i) | (fsl_stb_o ^ fsl_ack_i) | !iwb_ack_i) & !rSTALL;
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wire gena = !((dwb_stb_o ^ dwb_ack_i) | (fsl_stb_o ^ fsl_ack_i) | !iwb_ack_i) & !rSTALL;
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wire oena = ((dwb_stb_o ^ dwb_ack_i) | (fsl_stb_o ^ fsl_ack_i) | !iwb_ack_i);
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wire oena = ((dwb_stb_o ^ dwb_ack_i) | (fsl_stb_o ^ fsl_ack_i) | !iwb_ack_i);
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// --- INSTANTIATIONS -------------------------------------
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// --- INSTANTIATIONS -------------------------------------
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aeMB_ibuf
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aeMB_ibuf
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ibuf (/*AUTOINST*/
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ibuf (/*AUTOINST*/
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// Outputs
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// Outputs
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.rIMM (rIMM[15:0]),
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.rIMM (rIMM[15:0]),
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.rRA (rRA[4:0]),
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.rRA (rRA[4:0]),
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.rRD (rRD[4:0]),
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.rRD (rRD[4:0]),
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.rRB (rRB[4:0]),
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.rRB (rRB[4:0]),
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.rALT (rALT[10:0]),
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.rALT (rALT[10:0]),
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.rOPC (rOPC[5:0]),
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.rOPC (rOPC[5:0]),
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.rSIMM (rSIMM[31:0]),
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.rSIMM (rSIMM[31:0]),
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.xIREG (xIREG[31:0]),
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.xIREG (xIREG[31:0]),
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.rSTALL (rSTALL),
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.rSTALL (rSTALL),
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.iwb_stb_o (iwb_stb_o),
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.iwb_stb_o (iwb_stb_o),
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// Inputs
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// Inputs
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.rBRA (rBRA),
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.rBRA (rBRA),
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.rMSR_IE (rMSR_IE),
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.rMSR_IE (rMSR_IE),
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.rMSR_BIP (rMSR_BIP),
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.rMSR_BIP (rMSR_BIP),
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.iwb_dat_i (iwb_dat_i[31:0]),
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.iwb_dat_i (iwb_dat_i[31:0]),
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.iwb_ack_i (iwb_ack_i),
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.iwb_ack_i (iwb_ack_i),
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.sys_int_i (sys_int_i),
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.sys_int_i (sys_int_i),
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.gclk (gclk),
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.gclk (gclk),
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.grst (grst),
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.grst (grst),
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.gena (gena),
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.gena (gena),
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.oena (oena));
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.oena (oena));
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aeMB_ctrl
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aeMB_ctrl
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ctrl (/*AUTOINST*/
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ctrl (/*AUTOINST*/
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// Outputs
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// Outputs
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.rMXDST (rMXDST[1:0]),
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.rMXDST (rMXDST[1:0]),
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.rMXSRC (rMXSRC[1:0]),
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.rMXSRC (rMXSRC[1:0]),
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.rMXTGT (rMXTGT[1:0]),
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.rMXTGT (rMXTGT[1:0]),
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.rMXALT (rMXALT[1:0]),
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.rMXALT (rMXALT[1:0]),
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.rMXALU (rMXALU[2:0]),
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.rMXALU (rMXALU[2:0]),
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.rRW (rRW[4:0]),
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.rRW (rRW[4:0]),
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.dwb_stb_o (dwb_stb_o),
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.dwb_stb_o (dwb_stb_o),
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.dwb_wre_o (dwb_wre_o),
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.dwb_wre_o (dwb_wre_o),
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.fsl_stb_o (fsl_stb_o),
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.fsl_stb_o (fsl_stb_o),
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.fsl_wre_o (fsl_wre_o),
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.fsl_wre_o (fsl_wre_o),
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// Inputs
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// Inputs
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.rDLY (rDLY),
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.rDLY (rDLY),
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.rIMM (rIMM[15:0]),
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.rIMM (rIMM[15:0]),
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.rALT (rALT[10:0]),
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.rALT (rALT[10:0]),
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.rOPC (rOPC[5:0]),
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.rOPC (rOPC[5:0]),
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.rRD (rRD[4:0]),
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.rRD (rRD[4:0]),
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.rRA (rRA[4:0]),
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.rRA (rRA[4:0]),
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.rRB (rRB[4:0]),
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.rRB (rRB[4:0]),
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.rPC (rPC[31:2]),
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.rPC (rPC[31:2]),
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.rBRA (rBRA),
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.rBRA (rBRA),
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.rMSR_IE (rMSR_IE),
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.rMSR_IE (rMSR_IE),
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.xIREG (xIREG[31:0]),
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.xIREG (xIREG[31:0]),
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.dwb_ack_i (dwb_ack_i),
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.dwb_ack_i (dwb_ack_i),
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.iwb_ack_i (iwb_ack_i),
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.iwb_ack_i (iwb_ack_i),
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.fsl_ack_i (fsl_ack_i),
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.fsl_ack_i (fsl_ack_i),
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.gclk (gclk),
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.gclk (gclk),
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.grst (grst),
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.grst (grst),
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.gena (gena));
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.gena (gena));
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aeMB_bpcu #(IW)
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aeMB_bpcu #(IW)
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bpcu (/*AUTOINST*/
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bpcu (/*AUTOINST*/
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// Outputs
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// Outputs
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.iwb_adr_o (iwb_adr_o[IW-1:2]),
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.iwb_adr_o (iwb_adr_o[IW-1:2]),
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.rPC (rPC[31:2]),
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.rPC (rPC[31:2]),
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.rPCLNK (rPCLNK[31:2]),
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.rPCLNK (rPCLNK[31:2]),
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.rBRA (rBRA),
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.rBRA (rBRA),
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.rDLY (rDLY),
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.rDLY (rDLY),
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// Inputs
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// Inputs
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.rMXALT (rMXALT[1:0]),
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.rMXALT (rMXALT[1:0]),
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.rOPC (rOPC[5:0]),
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.rOPC (rOPC[5:0]),
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.rRD (rRD[4:0]),
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.rRD (rRD[4:0]),
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.rRA (rRA[4:0]),
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.rRA (rRA[4:0]),
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.rRESULT (rRESULT[31:0]),
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.rRESULT (rRESULT[31:0]),
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.rDWBDI (rDWBDI[31:0]),
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.rDWBDI (rDWBDI[31:0]),
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.rREGA (rREGA[31:0]),
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.rREGA (rREGA[31:0]),
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.gclk (gclk),
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.gclk (gclk),
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.grst (grst),
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.grst (grst),
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.gena (gena));
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.gena (gena));
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aeMB_regf
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aeMB_regf
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regf (/*AUTOINST*/
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regf (/*AUTOINST*/
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// Outputs
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// Outputs
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.rREGA (rREGA[31:0]),
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.rREGA (rREGA[31:0]),
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.rREGB (rREGB[31:0]),
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.rREGB (rREGB[31:0]),
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.rDWBDI (rDWBDI[31:0]),
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.rDWBDI (rDWBDI[31:0]),
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.dwb_dat_o (dwb_dat_o[31:0]),
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.dwb_dat_o (dwb_dat_o[31:0]),
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.fsl_dat_o (fsl_dat_o[31:0]),
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.fsl_dat_o (fsl_dat_o[31:0]),
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// Inputs
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// Inputs
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.rOPC (rOPC[5:0]),
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.rOPC (rOPC[5:0]),
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.rRA (rRA[4:0]),
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.rRA (rRA[4:0]),
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.rRB (rRB[4:0]),
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.rRB (rRB[4:0]),
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.rRW (rRW[4:0]),
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.rRW (rRW[4:0]),
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.rRD (rRD[4:0]),
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.rRD (rRD[4:0]),
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.rMXDST (rMXDST[1:0]),
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.rMXDST (rMXDST[1:0]),
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.rPCLNK (rPCLNK[31:2]),
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.rPCLNK (rPCLNK[31:2]),
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.rRESULT (rRESULT[31:0]),
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.rRESULT (rRESULT[31:0]),
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.rDWBSEL (rDWBSEL[3:0]),
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.rDWBSEL (rDWBSEL[3:0]),
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.rBRA (rBRA),
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.rBRA (rBRA),
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.rDLY (rDLY),
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.rDLY (rDLY),
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.dwb_dat_i (dwb_dat_i[31:0]),
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.dwb_dat_i (dwb_dat_i[31:0]),
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.fsl_dat_i (fsl_dat_i[31:0]),
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.fsl_dat_i (fsl_dat_i[31:0]),
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.gclk (gclk),
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.gclk (gclk),
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.grst (grst),
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.grst (grst),
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.gena (gena));
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.gena (gena));
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aeMB_xecu #(DW, MUL, BSF)
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aeMB_xecu #(DW, MUL, BSF)
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xecu (/*AUTOINST*/
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xecu (/*AUTOINST*/
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// Outputs
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// Outputs
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.dwb_adr_o (dwb_adr_o[DW-1:2]),
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.dwb_adr_o (dwb_adr_o[DW-1:2]),
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.dwb_sel_o (dwb_sel_o[3:0]),
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.dwb_sel_o (dwb_sel_o[3:0]),
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.fsl_adr_o (fsl_adr_o[6:2]),
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.fsl_adr_o (fsl_adr_o[6:2]),
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.fsl_tag_o (fsl_tag_o[1:0]),
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.fsl_tag_o (fsl_tag_o[1:0]),
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.rRESULT (rRESULT[31:0]),
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.rRESULT (rRESULT[31:0]),
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.rDWBSEL (rDWBSEL[3:0]),
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.rDWBSEL (rDWBSEL[3:0]),
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.rMSR_IE (rMSR_IE),
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.rMSR_IE (rMSR_IE),
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.rMSR_BIP (rMSR_BIP),
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.rMSR_BIP (rMSR_BIP),
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// Inputs
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// Inputs
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.rREGA (rREGA[31:0]),
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.rREGA (rREGA[31:0]),
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.rREGB (rREGB[31:0]),
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.rREGB (rREGB[31:0]),
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.rMXSRC (rMXSRC[1:0]),
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.rMXSRC (rMXSRC[1:0]),
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.rMXTGT (rMXTGT[1:0]),
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.rMXTGT (rMXTGT[1:0]),
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.rRA (rRA[4:0]),
|
.rRA (rRA[4:0]),
|
.rRB (rRB[4:0]),
|
.rRB (rRB[4:0]),
|
.rMXALU (rMXALU[2:0]),
|
.rMXALU (rMXALU[2:0]),
|
.rBRA (rBRA),
|
.rBRA (rBRA),
|
.rDLY (rDLY),
|
.rDLY (rDLY),
|
.rALT (rALT[10:0]),
|
.rALT (rALT[10:0]),
|
.rSTALL (rSTALL),
|
.rSTALL (rSTALL),
|
.rSIMM (rSIMM[31:0]),
|
.rSIMM (rSIMM[31:0]),
|
.rIMM (rIMM[15:0]),
|
.rIMM (rIMM[15:0]),
|
.rOPC (rOPC[5:0]),
|
.rOPC (rOPC[5:0]),
|
.rRD (rRD[4:0]),
|
.rRD (rRD[4:0]),
|
.rDWBDI (rDWBDI[31:0]),
|
.rDWBDI (rDWBDI[31:0]),
|
.rPC (rPC[31:2]),
|
.rPC (rPC[31:2]),
|
.gclk (gclk),
|
.gclk (gclk),
|
.grst (grst),
|
.grst (grst),
|
.gena (gena));
|
.gena (gena));
|
|
|
|
|
endmodule // aeMB_edk32
|
endmodule // aeMB_edk32
|
|
|
/*
|
/*
|
$Log: not supported by cvs2svn $
|
$Log: not supported by cvs2svn $
|
Revision 1.13 2007/12/25 22:15:09 sybreon
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Revision 1.13 2007/12/25 22:15:09 sybreon
|
Stalls pipeline on MUL/BSF instructions results in minor speed improvements.
|
Stalls pipeline on MUL/BSF instructions results in minor speed improvements.
|
|
|
Revision 1.12 2007/12/23 20:40:44 sybreon
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Revision 1.12 2007/12/23 20:40:44 sybreon
|
Abstracted simulation kernel (aeMB_sim) to split simulation models from synthesis models.
|
Abstracted simulation kernel (aeMB_sim) to split simulation models from synthesis models.
|
|
|
Revision 1.11 2007/11/30 17:08:29 sybreon
|
Revision 1.11 2007/11/30 17:08:29 sybreon
|
Moved simulation kernel into code.
|
Moved simulation kernel into code.
|
|
|
Revision 1.10 2007/11/16 21:52:03 sybreon
|
Revision 1.10 2007/11/16 21:52:03 sybreon
|
Added fsl_tag_o to FSL bus (tag either address or data).
|
Added fsl_tag_o to FSL bus (tag either address or data).
|
|
|
Revision 1.9 2007/11/14 23:19:24 sybreon
|
Revision 1.9 2007/11/14 23:19:24 sybreon
|
Fixed minor typo.
|
Fixed minor typo.
|
|
|
Revision 1.8 2007/11/14 22:14:34 sybreon
|
Revision 1.8 2007/11/14 22:14:34 sybreon
|
Changed interrupt handling system (reported by M. Ettus).
|
Changed interrupt handling system (reported by M. Ettus).
|
|
|
Revision 1.7 2007/11/10 16:39:38 sybreon
|
Revision 1.7 2007/11/10 16:39:38 sybreon
|
Upgraded license to LGPLv3.
|
Upgraded license to LGPLv3.
|
Significant performance optimisations.
|
Significant performance optimisations.
|
|
|
Revision 1.6 2007/11/09 20:51:52 sybreon
|
Revision 1.6 2007/11/09 20:51:52 sybreon
|
Added GET/PUT support through a FSL bus.
|
Added GET/PUT support through a FSL bus.
|
|
|
Revision 1.5 2007/11/08 17:48:14 sybreon
|
Revision 1.5 2007/11/08 17:48:14 sybreon
|
Fixed data WISHBONE arbitration problem (reported by J Lee).
|
Fixed data WISHBONE arbitration problem (reported by J Lee).
|
|
|
Revision 1.4 2007/11/08 14:17:47 sybreon
|
Revision 1.4 2007/11/08 14:17:47 sybreon
|
Parameterised optional components.
|
Parameterised optional components.
|
|
|
Revision 1.3 2007/11/03 08:34:55 sybreon
|
Revision 1.3 2007/11/03 08:34:55 sybreon
|
Minor code cleanup.
|
Minor code cleanup.
|
|
|
Revision 1.2 2007/11/02 19:20:58 sybreon
|
Revision 1.2 2007/11/02 19:20:58 sybreon
|
Added better (beta) interrupt support.
|
Added better (beta) interrupt support.
|
Changed MSR_IE to disabled at reset as per MB docs.
|
Changed MSR_IE to disabled at reset as per MB docs.
|
|
|
Revision 1.1 2007/11/02 03:25:40 sybreon
|
Revision 1.1 2007/11/02 03:25:40 sybreon
|
New EDK 3.2 compatible design with optional barrel-shifter and multiplier.
|
New EDK 3.2 compatible design with optional barrel-shifter and multiplier.
|
Fixed various minor data hazard bugs.
|
Fixed various minor data hazard bugs.
|
Code compatible with -O0/1/2/3/s generated code.
|
Code compatible with -O0/1/2/3/s generated code.
|
|
|
