/*
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/*
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* $Id: aeMB_control.v,v 1.6 2007-05-17 09:08:21 sybreon Exp $
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* $Id: aeMB_control.v,v 1.6 2007-05-17 09:08:21 sybreon Exp $
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*
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*
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* AE68 System Control Unit
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* AE68 System Control Unit
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* Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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* Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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*
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*
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* This library is free software; you can redistribute it and/or
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public License
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* modify it under the terms of the GNU Lesser General Public License
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* as published by the Free Software Foundation; either version 2.1 of
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* as published by the Free Software Foundation; either version 2.1 of
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* the License, or (at your option) any later version.
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* the License, or (at your option) any later version.
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*
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*
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* This library is distributed in the hope that it will be useful, but
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* This library is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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* Lesser General Public License for more details.
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*
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*
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* You should have received a copy of the GNU Lesser General Public
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
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* USA
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* USA
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*
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*
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* DESCRIPTION
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* DESCRIPTION
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* Controls the state of the processor.
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* Controls the state of the processor.
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*
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*
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* HISTORY
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* HISTORY
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* $Log: not supported by cvs2svn $
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* $Log: not supported by cvs2svn $
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* Revision 1.5 2007/05/16 12:32:21 sybreon
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* Revision 1.5 2007/05/16 12:32:21 sybreon
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* Added async BRA/DLY signals for future clock, reset, and interrupt features.
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* Added async BRA/DLY signals for future clock, reset, and interrupt features.
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*
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*
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* Revision 1.4 2007/04/27 00:23:55 sybreon
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* Revision 1.4 2007/04/27 00:23:55 sybreon
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* Added code documentation.
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* Added code documentation.
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* Improved size & speed of rtl/verilog/aeMB_aslu.v
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* Improved size & speed of rtl/verilog/aeMB_aslu.v
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*
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*
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* Revision 1.3 2007/04/11 04:30:43 sybreon
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* Revision 1.3 2007/04/11 04:30:43 sybreon
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* Added pipeline stalling from incomplete bus cycles.
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* Added pipeline stalling from incomplete bus cycles.
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* Separated sync and async portions of code.
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* Separated sync and async portions of code.
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*
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*
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* Revision 1.2 2007/04/04 14:08:34 sybreon
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* Revision 1.2 2007/04/04 14:08:34 sybreon
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* Added initial interrupt/exception support.
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* Added initial interrupt/exception support.
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*
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*
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* Revision 1.1 2007/03/09 17:52:17 sybreon
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* Revision 1.1 2007/03/09 17:52:17 sybreon
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* initial import
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* initial import
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*
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*
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*/
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*/
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module aeMB_control (/*AUTOARG*/
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module aeMB_control (/*AUTOARG*/
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// Outputs
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// Outputs
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rFSM, nclk, prst, prun, frun, drun,
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rFSM, nclk, prst, prun, frun, drun,
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// Inputs
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// Inputs
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sys_rst_i, sys_clk_i, sys_int_i, sys_exc_i, rIWBSTB, iwb_ack_i,
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sys_rst_i, sys_clk_i, sys_int_i, sys_exc_i, rIWBSTB, iwb_ack_i,
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rDWBSTB, dwb_ack_i, rBRA, rDLY
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rDWBSTB, dwb_ack_i, rBRA, rDLY
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);
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);
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// System
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// System
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input sys_rst_i, sys_clk_i;
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input sys_rst_i, sys_clk_i;
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input sys_int_i;
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input sys_int_i;
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input sys_exc_i;
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input sys_exc_i;
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// Instruction WB
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// Instruction WB
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input rIWBSTB;
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input rIWBSTB;
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input iwb_ack_i;
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input iwb_ack_i;
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// Data WB
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// Data WB
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input rDWBSTB;
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input rDWBSTB;
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input dwb_ack_i;
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input dwb_ack_i;
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// Internal
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// Internal
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input rBRA, rDLY;
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input rBRA, rDLY;
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output [1:0] rFSM;
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output [1:0] rFSM;
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//, rLDST;
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//, rLDST;
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output nclk, prst, prun;
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output nclk, prst, prun;
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output frun, drun;
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output frun, drun;
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/**
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/**
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RUN Signal
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RUN Signal
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----------
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----------
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This master run signal will pause or run the entire pipeline. It
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This master run signal will pause or run the entire pipeline. It
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will pause for any incomplete bus transaction.
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will pause for any incomplete bus transaction.
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*/
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*/
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assign prun = ~((rDWBSTB ^ dwb_ack_i) | ((rIWBSTB ^ iwb_ack_i)));
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assign prun = ~((rDWBSTB ^ dwb_ack_i) | ((rIWBSTB ^ iwb_ack_i)));
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/**
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/**
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Debounce
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Debounce
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--------
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--------
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The following external signals are debounced and synchronised:
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The following external signals are debounced and synchronised:
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- Interrupt
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- Interrupt
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*/
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*/
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reg [2:0] rEXC, rINT;
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reg [2:0] rEXC, rINT;
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always @(negedge nclk)
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always @(negedge nclk)
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if (prst) begin
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if (prst) begin
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/*AUTORESET*/
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/*AUTORESET*/
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// Beginning of autoreset for uninitialized flops
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// Beginning of autoreset for uninitialized flops
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rINT <= 3'h0;
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rINT <= 3'h0;
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// End of automatics
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// End of automatics
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end else if (prun) begin
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end else if (prun) begin
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//rEXC <= #1 {rEXC[1:0], sys_exc_i};
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//rEXC <= #1 {rEXC[1:0], sys_exc_i};
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rINT <= #1 {rINT[1:0], sys_int_i};
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rINT <= #1 {rINT[1:0], sys_int_i};
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end
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end
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/**
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/**
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Machine States
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Machine States
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--------------
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--------------
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The internal machine state is affected by external interrupt,
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The internal machine state is affected by external interrupt,
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exception and software exceptions. Only interrupts are
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exception and software exceptions. Only interrupts are
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implemented.
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implemented.
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TODO: Implement exceptions.
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TODO: Implement exceptions.
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*/
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*/
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parameter [1:0]
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parameter [1:0]
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FSM_RUN = 2'o0,
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FSM_RUN = 2'o0,
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FSM_SWEXC = 2'o3,
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FSM_SWEXC = 2'o3,
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FSM_HWEXC = 2'o2,
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FSM_HWEXC = 2'o2,
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FSM_HWINT = 2'o1;
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FSM_HWINT = 2'o1;
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reg [1:0] rFSM, rNXT;
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reg [1:0] rFSM, rNXT;
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always @(negedge nclk)
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always @(negedge nclk)
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if (prst) begin
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if (prst) begin
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/*AUTORESET*/
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/*AUTORESET*/
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// Beginning of autoreset for uninitialized flops
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// Beginning of autoreset for uninitialized flops
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rFSM <= 2'h0;
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rFSM <= 2'h0;
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// End of automatics
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// End of automatics
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end else if (prun) begin
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end else if (prun) begin
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rFSM <= #1 rNXT;
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rFSM <= #1 rNXT;
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end
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end
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always @(/*AUTOSENSE*/rFSM or rINT)
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always @(/*AUTOSENSE*/rFSM or rINT)
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case (rFSM)
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case (rFSM)
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FSM_HWEXC: rNXT <= FSM_RUN;
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FSM_HWEXC: rNXT <= FSM_RUN;
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//FSM_SWEXC: rNXT <= FSM_RUN;
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//FSM_SWEXC: rNXT <= FSM_RUN;
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FSM_HWINT: rNXT <= FSM_RUN;
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FSM_HWINT: rNXT <= FSM_RUN;
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default: begin
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default: begin
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rNXT <= //(rEXC == 3'h3) ? FSM_HWEXC :
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rNXT <= //(rEXC == 3'h3) ? FSM_HWEXC :
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(rINT == 3'h3) ? FSM_HWINT :
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(rINT == 3'h3) ? FSM_HWINT :
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FSM_RUN;
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FSM_RUN;
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end
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end
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endcase // case (rFSM)
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endcase // case (rFSM)
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/**
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/**
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Bubble
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Bubble
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------
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------
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Pipeline bubbles are introduced during a branch or interrupt.
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Pipeline bubbles are introduced during a branch or interrupt.
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TODO: Implement interrupt bubble.
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TODO: Implement interrupt bubble.
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*/
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*/
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reg [1:0] rRUN, xRUN;
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reg [1:0] rRUN, xRUN;
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assign {drun,frun} = xRUN;
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assign {drun,frun} = xRUN;
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always @(/*AUTOSENSE*/rBRA or rDLY) begin
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always @(/*AUTOSENSE*/rBRA or rDLY) begin
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xRUN <= {~(rBRA ^ rDLY), ~rBRA};
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xRUN <= {~(rBRA ^ rDLY), ~rBRA};
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end
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end
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/**
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/**
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Clock/Reset
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Clock/Reset
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-----------
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-----------
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This controls the internal clock/reset signal for the core. Any
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This controls the internal clock/reset signal for the core. Any
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DCM/PLL/DPLL can be instantiated here if needed.
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DCM/PLL/DPLL can be instantiated here if needed.
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*/
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*/
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reg [1:0] rRST;
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reg [1:0] rRST;
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assign nclk = sys_clk_i;
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assign nclk = sys_clk_i;
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assign prst = rRST[1];
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assign prst = rRST[1];
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always @(negedge nclk)
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always @(negedge nclk)
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if (!sys_rst_i) begin
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if (!sys_rst_i) begin
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rRST <= 2'h3;
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rRST <= 2'h3;
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/*AUTORESET*/
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/*AUTORESET*/
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end else begin
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end else begin
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rRST <= {rRST[0],1'b0};
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rRST <= {rRST[0],1'b0};
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end
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end
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endmodule // aeMB_control
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endmodule // aeMB_control
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