/* $Id: aeMB2_bsft.v,v 1.3 2008-04-28 08:15:25 sybreon Exp $
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/* $Id: aeMB2_bsft.v,v 1.3 2008-04-28 08:15:25 sybreon Exp $
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**
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**
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** AEMB2 EDK 6.2 COMPATIBLE CORE
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** AEMB2 EDK 6.2 COMPATIBLE CORE
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** Copyright (C) 2004-2008 Shawn Tan <shawn.tan@aeste.net>
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** Copyright (C) 2004-2008 Shawn Tan <shawn.tan@aeste.net>
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**
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**
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** This file is part of AEMB.
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** This file is part of AEMB.
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**
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**
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** AEMB is free software: you can redistribute it and/or modify it
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** AEMB is free software: you can redistribute it and/or modify it
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** under the terms of the GNU Lesser General Public License as
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** under the terms of the GNU Lesser General Public License as
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** published by the Free Software Foundation, either version 3 of the
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** published by the Free Software Foundation, either version 3 of the
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** License, or (at your option) any later version.
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** License, or (at your option) any later version.
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**
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**
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** AEMB is distributed in the hope that it will be useful, but WITHOUT
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** AEMB is distributed in the hope that it will be useful, but WITHOUT
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** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General
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** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General
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** Public License for more details.
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** Public License for more details.
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**
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**
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** You should have received a copy of the GNU Lesser General Public
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** You should have received a copy of the GNU Lesser General Public
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** License along with AEMB. If not, see <http:**www.gnu.org/licenses/>.
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** License along with AEMB. If not, see <http:**www.gnu.org/licenses/>.
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*/
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*/
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/**
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/**
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* Two Cycle Barrel Shift Unit
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* Two Cycle Barrel Shift Unit
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* @file aeMB2_bsft.v
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* @file aeMB2_bsft.v
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* This implements a 2 cycle barrel shifter. The design can be further
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* This implements a 2 cycle barrel shifter. The design can be further
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optimised depending on architecture.
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optimised depending on architecture.
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*/
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*/
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// 420 LUTS
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// 420 LUTS
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module aeMB2_bsft (/*AUTOARG*/
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module aeMB2_bsft (/*AUTOARG*/
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// Outputs
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// Outputs
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bsf_mx,
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bsf_mx,
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// Inputs
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// Inputs
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opa_of, opb_of, opc_of, imm_of, gclk, grst, dena, gpha
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opa_of, opb_of, opc_of, imm_of, gclk, grst, dena, gpha
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);
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);
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parameter AEMB_BSF = 1; ///< implement barrel shift
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parameter AEMB_BSF = 1; ///< implement barrel shift
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output [31:0] bsf_mx;
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output [31:0] bsf_mx;
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input [31:0] opa_of;
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input [31:0] opa_of;
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input [31:0] opb_of;
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input [31:0] opb_of;
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input [5:0] opc_of;
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input [5:0] opc_of;
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input [10:9] imm_of;
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input [10:9] imm_of;
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// SYS signals
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// SYS signals
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input gclk,
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input gclk,
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grst,
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grst,
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dena,
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dena,
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gpha;
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gpha;
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/*AUTOREG*/
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/*AUTOREG*/
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reg [31:0] rBSLL, rBSRL, rBSRA;
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reg [31:0] rBSLL, rBSRL, rBSRA;
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reg [31:0] rBSR;
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reg [31:0] rBSR;
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reg [10:9] imm_ex;
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reg [10:9] imm_ex;
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wire [31:0] wOPB = opb_of;
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wire [31:0] wOPB = opb_of;
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wire [31:0] wOPA = opa_of;
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wire [31:0] wOPA = opa_of;
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// STAGE-1 SHIFTERS
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// STAGE-1 SHIFTERS
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// logical
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// logical
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always @(posedge gclk)
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always @(posedge gclk)
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if (grst) begin
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if (grst) begin
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/*AUTORESET*/
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/*AUTORESET*/
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// Beginning of autoreset for uninitialized flops
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// Beginning of autoreset for uninitialized flops
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rBSLL <= 32'h0;
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rBSLL <= 32'h0;
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rBSRL <= 32'h0;
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rBSRL <= 32'h0;
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// End of automatics
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// End of automatics
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end else if (dena) begin
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end else if (dena) begin
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rBSLL <= #1 wOPA << wOPB[4:0];
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rBSLL <= #1 wOPA << wOPB[4:0];
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rBSRL <= #1 wOPA >> wOPB[4:0];
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rBSRL <= #1 wOPA >> wOPB[4:0];
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end
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end
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// arithmetic
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// arithmetic
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always @(posedge gclk)
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always @(posedge gclk)
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if (grst) begin
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if (grst) begin
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/*AUTORESET*/
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/*AUTORESET*/
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// Beginning of autoreset for uninitialized flops
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// Beginning of autoreset for uninitialized flops
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rBSRA <= 32'h0;
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rBSRA <= 32'h0;
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// End of automatics
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// End of automatics
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end else if (dena)
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end else if (dena)
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case (wOPB[4:0])
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case (wOPB[4:0])
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5'd00: rBSRA <= wOPA;
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5'd00: rBSRA <= wOPA;
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5'd01: rBSRA <= {{(1){wOPA[31]}}, wOPA[31:1]};
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5'd01: rBSRA <= {{(1){wOPA[31]}}, wOPA[31:1]};
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5'd02: rBSRA <= {{(2){wOPA[31]}}, wOPA[31:2]};
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5'd02: rBSRA <= {{(2){wOPA[31]}}, wOPA[31:2]};
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5'd03: rBSRA <= {{(3){wOPA[31]}}, wOPA[31:3]};
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5'd03: rBSRA <= {{(3){wOPA[31]}}, wOPA[31:3]};
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5'd04: rBSRA <= {{(4){wOPA[31]}}, wOPA[31:4]};
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5'd04: rBSRA <= {{(4){wOPA[31]}}, wOPA[31:4]};
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5'd05: rBSRA <= {{(5){wOPA[31]}}, wOPA[31:5]};
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5'd05: rBSRA <= {{(5){wOPA[31]}}, wOPA[31:5]};
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5'd06: rBSRA <= {{(6){wOPA[31]}}, wOPA[31:6]};
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5'd06: rBSRA <= {{(6){wOPA[31]}}, wOPA[31:6]};
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5'd07: rBSRA <= {{(7){wOPA[31]}}, wOPA[31:7]};
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5'd07: rBSRA <= {{(7){wOPA[31]}}, wOPA[31:7]};
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5'd08: rBSRA <= {{(8){wOPA[31]}}, wOPA[31:8]};
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5'd08: rBSRA <= {{(8){wOPA[31]}}, wOPA[31:8]};
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5'd09: rBSRA <= {{(9){wOPA[31]}}, wOPA[31:9]};
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5'd09: rBSRA <= {{(9){wOPA[31]}}, wOPA[31:9]};
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5'd10: rBSRA <= {{(10){wOPA[31]}}, wOPA[31:10]};
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5'd10: rBSRA <= {{(10){wOPA[31]}}, wOPA[31:10]};
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5'd11: rBSRA <= {{(11){wOPA[31]}}, wOPA[31:11]};
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5'd11: rBSRA <= {{(11){wOPA[31]}}, wOPA[31:11]};
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5'd12: rBSRA <= {{(12){wOPA[31]}}, wOPA[31:12]};
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5'd12: rBSRA <= {{(12){wOPA[31]}}, wOPA[31:12]};
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5'd13: rBSRA <= {{(13){wOPA[31]}}, wOPA[31:13]};
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5'd13: rBSRA <= {{(13){wOPA[31]}}, wOPA[31:13]};
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5'd14: rBSRA <= {{(14){wOPA[31]}}, wOPA[31:14]};
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5'd14: rBSRA <= {{(14){wOPA[31]}}, wOPA[31:14]};
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5'd15: rBSRA <= {{(15){wOPA[31]}}, wOPA[31:15]};
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5'd15: rBSRA <= {{(15){wOPA[31]}}, wOPA[31:15]};
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5'd16: rBSRA <= {{(16){wOPA[31]}}, wOPA[31:16]};
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5'd16: rBSRA <= {{(16){wOPA[31]}}, wOPA[31:16]};
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5'd17: rBSRA <= {{(17){wOPA[31]}}, wOPA[31:17]};
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5'd17: rBSRA <= {{(17){wOPA[31]}}, wOPA[31:17]};
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5'd18: rBSRA <= {{(18){wOPA[31]}}, wOPA[31:18]};
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5'd18: rBSRA <= {{(18){wOPA[31]}}, wOPA[31:18]};
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5'd19: rBSRA <= {{(19){wOPA[31]}}, wOPA[31:19]};
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5'd19: rBSRA <= {{(19){wOPA[31]}}, wOPA[31:19]};
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5'd20: rBSRA <= {{(20){wOPA[31]}}, wOPA[31:20]};
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5'd20: rBSRA <= {{(20){wOPA[31]}}, wOPA[31:20]};
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5'd21: rBSRA <= {{(21){wOPA[31]}}, wOPA[31:21]};
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5'd21: rBSRA <= {{(21){wOPA[31]}}, wOPA[31:21]};
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5'd22: rBSRA <= {{(22){wOPA[31]}}, wOPA[31:22]};
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5'd22: rBSRA <= {{(22){wOPA[31]}}, wOPA[31:22]};
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5'd23: rBSRA <= {{(23){wOPA[31]}}, wOPA[31:23]};
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5'd23: rBSRA <= {{(23){wOPA[31]}}, wOPA[31:23]};
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5'd24: rBSRA <= {{(24){wOPA[31]}}, wOPA[31:24]};
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5'd24: rBSRA <= {{(24){wOPA[31]}}, wOPA[31:24]};
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5'd25: rBSRA <= {{(25){wOPA[31]}}, wOPA[31:25]};
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5'd25: rBSRA <= {{(25){wOPA[31]}}, wOPA[31:25]};
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5'd26: rBSRA <= {{(26){wOPA[31]}}, wOPA[31:26]};
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5'd26: rBSRA <= {{(26){wOPA[31]}}, wOPA[31:26]};
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5'd27: rBSRA <= {{(27){wOPA[31]}}, wOPA[31:27]};
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5'd27: rBSRA <= {{(27){wOPA[31]}}, wOPA[31:27]};
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5'd28: rBSRA <= {{(28){wOPA[31]}}, wOPA[31:28]};
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5'd28: rBSRA <= {{(28){wOPA[31]}}, wOPA[31:28]};
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5'd29: rBSRA <= {{(29){wOPA[31]}}, wOPA[31:29]};
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5'd29: rBSRA <= {{(29){wOPA[31]}}, wOPA[31:29]};
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5'd30: rBSRA <= {{(30){wOPA[31]}}, wOPA[31:30]};
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5'd30: rBSRA <= {{(30){wOPA[31]}}, wOPA[31:30]};
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5'd31: rBSRA <= {{(31){wOPA[31]}}, wOPA[31]};
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5'd31: rBSRA <= {{(31){wOPA[31]}}, wOPA[31]};
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endcase // case (wOPB[4:0])
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endcase // case (wOPB[4:0])
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// STAGE-2 SHIFT
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// STAGE-2 SHIFT
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always @(posedge gclk)
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always @(posedge gclk)
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if (grst) begin
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if (grst) begin
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/*AUTORESET*/
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/*AUTORESET*/
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// Beginning of autoreset for uninitialized flops
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// Beginning of autoreset for uninitialized flops
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imm_ex <= 2'h0;
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imm_ex <= 2'h0;
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rBSR <= 32'h0;
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rBSR <= 32'h0;
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// End of automatics
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// End of automatics
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end else if (dena) begin
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end else if (dena) begin
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case (imm_ex)
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case (imm_ex)
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2'o0: rBSR <= #1 rBSRL;
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2'o0: rBSR <= #1 rBSRL;
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2'o1: rBSR <= #1 rBSRA;
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2'o1: rBSR <= #1 rBSRA;
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2'o2: rBSR <= #1 rBSLL;
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2'o2: rBSR <= #1 rBSLL;
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default: rBSR <= #1 32'hX;
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default: rBSR <= #1 32'hX;
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endcase // case (imm_ex)
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endcase // case (imm_ex)
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imm_ex <= #1 imm_of[10:9]; // delay 1 cycle
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imm_ex <= #1 imm_of[10:9]; // delay 1 cycle
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end
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end
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assign bsf_mx = (AEMB_BSF[0]) ? rBSR : 32'hX;
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assign bsf_mx = (AEMB_BSF[0]) ? rBSR : 32'hX;
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endmodule // aeMB2_bsft
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endmodule // aeMB2_bsft
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/*
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/*
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$Log: not supported by cvs2svn $
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$Log: not supported by cvs2svn $
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Revision 1.2 2008/04/26 01:09:05 sybreon
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Revision 1.2 2008/04/26 01:09:05 sybreon
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Passes basic tests. Minor documentation changes to make it compatible with iverilog pre-processor.
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Passes basic tests. Minor documentation changes to make it compatible with iverilog pre-processor.
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Revision 1.1 2008/04/18 00:21:52 sybreon
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Revision 1.1 2008/04/18 00:21:52 sybreon
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Initial import.
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Initial import.
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