/* $Id: aeMB2_ctrl.v,v 1.7 2008-05-11 13:50:50 sybreon Exp $
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/* $Id: aeMB2_ctrl.v,v 1.7 2008-05-11 13:50:50 sybreon Exp $
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**
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**
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** AEMB2 EDK 6.2 COMPATIBLE CORE
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** AEMB2 EDK 6.2 COMPATIBLE CORE
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** Copyright (C) 2004-2008 Shawn Tan <shawn.tan@aeste.net>
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** Copyright (C) 2004-2008 Shawn Tan <shawn.tan@aeste.net>
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**
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**
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** This file is part of AEMB.
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** This file is part of AEMB.
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**
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**
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** AEMB is free software: you can redistribute it and/or modify it
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** AEMB is free software: you can redistribute it and/or modify it
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** under the terms of the GNU Lesser General Public License as
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** under the terms of the GNU Lesser General Public License as
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** published by the Free Software Foundation, either version 3 of the
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** published by the Free Software Foundation, either version 3 of the
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** License, or (at your option) any later version.
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** License, or (at your option) any later version.
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**
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**
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** AEMB is distributed in the hope that it will be useful, but WITHOUT
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** AEMB is distributed in the hope that it will be useful, but WITHOUT
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** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General
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** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General
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** Public License for more details.
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** Public License for more details.
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**
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**
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** You should have received a copy of the GNU Lesser General Public
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** You should have received a copy of the GNU Lesser General Public
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** License along with AEMB. If not, see <http:**www.gnu.org/licenses/>.
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** License along with AEMB. If not, see <http:**www.gnu.org/licenses/>.
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*/
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*/
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/**
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/**
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* Instruction Decode & Control
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* Instruction Decode & Control
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* @file aeMB2_ctrl.v
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* @file aeMB2_ctrl.v
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* This is the data decoder that will control the command signals and
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* This is the data decoder that will control the command signals and
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operand fetch.
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operand fetch.
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*/
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*/
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module aeMB2_ctrl (/*AUTOARG*/
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module aeMB2_ctrl (/*AUTOARG*/
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// Outputs
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// Outputs
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opa_of, opb_of, opd_of, opc_of, ra_of, rd_of, imm_of, rd_ex,
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opa_of, opb_of, opd_of, opc_of, ra_of, rd_of, imm_of, rd_ex,
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mux_of, mux_ex, hzd_bpc, hzd_fwd,
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mux_of, mux_ex, hzd_bpc, hzd_fwd,
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// Inputs
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// Inputs
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opa_if, opb_if, opd_if, brk_if, bra_ex, rpc_if, alu_ex, ich_dat,
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opa_if, opb_if, opd_if, brk_if, bra_ex, rpc_if, alu_ex, ich_dat,
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gclk, grst, dena, iena, gpha
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gclk, grst, dena, iena, gpha
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);
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);
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parameter AEMB_HTX = 1;
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parameter AEMB_HTX = 1;
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// EX CONTROL
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// EX CONTROL
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output [31:0] opa_of;
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output [31:0] opa_of;
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output [31:0] opb_of;
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output [31:0] opb_of;
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output [31:0] opd_of;
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output [31:0] opd_of;
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output [5:0] opc_of;
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output [5:0] opc_of;
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output [4:0] ra_of,
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output [4:0] ra_of,
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//rb_of,
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//rb_of,
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rd_of;
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rd_of;
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output [15:0] imm_of;
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output [15:0] imm_of;
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output [4:0] rd_ex;
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output [4:0] rd_ex;
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// REGS
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// REGS
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input [31:0] opa_if,
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input [31:0] opa_if,
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opb_if,
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opb_if,
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opd_if;
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opd_if;
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// WB CONTROL
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// WB CONTROL
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output [2:0] mux_of,
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output [2:0] mux_of,
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mux_ex;
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mux_ex;
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// INTERNAL
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// INTERNAL
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input [1:0] brk_if;
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input [1:0] brk_if;
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input [1:0] bra_ex;
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input [1:0] bra_ex;
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input [31:2] rpc_if;
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input [31:2] rpc_if;
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input [31:0] alu_ex;
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input [31:0] alu_ex;
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input [31:0] ich_dat;
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input [31:0] ich_dat;
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output hzd_bpc;
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output hzd_bpc;
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output hzd_fwd;
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output hzd_fwd;
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// SYSTEM
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// SYSTEM
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input gclk,
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input gclk,
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grst,
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grst,
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dena,
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dena,
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iena,
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iena,
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gpha;
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gpha;
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/*AUTOREG*/
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/*AUTOREG*/
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// Beginning of automatic regs (for this module's undeclared outputs)
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// Beginning of automatic regs (for this module's undeclared outputs)
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reg [15:0] imm_of;
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reg [15:0] imm_of;
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reg [2:0] mux_ex;
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reg [2:0] mux_ex;
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reg [2:0] mux_of;
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reg [2:0] mux_of;
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reg [31:0] opa_of;
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reg [31:0] opa_of;
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reg [31:0] opb_of;
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reg [31:0] opb_of;
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reg [5:0] opc_of;
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reg [5:0] opc_of;
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reg [31:0] opd_of;
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reg [31:0] opd_of;
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reg [4:0] ra_of;
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reg [4:0] ra_of;
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reg [4:0] rd_ex;
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reg [4:0] rd_ex;
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reg [4:0] rd_of;
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reg [4:0] rd_of;
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// End of automatics
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// End of automatics
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wire fINT;
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wire fINT;
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//wire [31:0] wXCEOP = 32'hBA2D0020; // Vector 0x20
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//wire [31:0] wXCEOP = 32'hBA2D0020; // Vector 0x20
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wire [31:0] wINTOP = 32'hB9CD0010; // Vector 0x10
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wire [31:0] wINTOP = 32'hB9CD0010; // Vector 0x10
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//wire [31:0] wNOPOP = 32'h88000000; // branch-no-delay/stall
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//wire [31:0] wNOPOP = 32'h88000000; // branch-no-delay/stall
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wire [1:0] mux_opa, mux_opb, mux_opd;
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wire [1:0] mux_opa, mux_opb, mux_opd;
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// translate signals
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// translate signals
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wire [4:0] wRD, wRA, wRB;
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wire [4:0] wRD, wRA, wRB;
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wire [5:0] wOPC;
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wire [5:0] wOPC;
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wire [15:0] wIMM;
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wire [15:0] wIMM;
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wire [31:0] imm_if;
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wire [31:0] imm_if;
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assign {wOPC, wRD, wRA, wIMM} = (fINT) ? wINTOP : ich_dat;
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assign {wOPC, wRD, wRA, wIMM} = (fINT) ? wINTOP : ich_dat;
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assign wRB = wIMM[15:11];
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assign wRB = wIMM[15:11];
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// decode main opgroups
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// decode main opgroups
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//wire fSFT = (wOPC == 6'o44);
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//wire fSFT = (wOPC == 6'o44);
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//wire fLOG = ({wOPC[5:4],wOPC[2]} == 3'o4);
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//wire fLOG = ({wOPC[5:4],wOPC[2]} == 3'o4);
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wire fMUL = (wOPC == 6'o20) | (wOPC == 6'o30);
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wire fMUL = (wOPC == 6'o20) | (wOPC == 6'o30);
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wire fBSF = (wOPC == 6'o21) | (wOPC == 6'o31);
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wire fBSF = (wOPC == 6'o21) | (wOPC == 6'o31);
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//wire fDIV = (wOPC == 6'o22);
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//wire fDIV = (wOPC == 6'o22);
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wire fRTD = (wOPC == 6'o55);
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wire fRTD = (wOPC == 6'o55);
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wire fBCC = (wOPC == 6'o47) | (wOPC == 6'o57);
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wire fBCC = (wOPC == 6'o47) | (wOPC == 6'o57);
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wire fBRU = (wOPC == 6'o46) | (wOPC == 6'o56);
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wire fBRU = (wOPC == 6'o46) | (wOPC == 6'o56);
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//wire fBRA = fBRU & wRA[3];
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//wire fBRA = fBRU & wRA[3];
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wire fIMM = (wOPC == 6'o54);
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wire fIMM = (wOPC == 6'o54);
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wire fMOV = (wOPC == 6'o45);
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wire fMOV = (wOPC == 6'o45);
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wire fLOD = ({wOPC[5:4],wOPC[2]} == 3'o6);
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wire fLOD = ({wOPC[5:4],wOPC[2]} == 3'o6);
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wire fSTR = ({wOPC[5:4],wOPC[2]} == 3'o7);
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wire fSTR = ({wOPC[5:4],wOPC[2]} == 3'o7);
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//wire fLDST = (wOPC[5:4] == 2'o3);
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//wire fLDST = (wOPC[5:4] == 2'o3);
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//wire fPUT = (wOPC == 6'o33) & wRB[4];
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//wire fPUT = (wOPC == 6'o33) & wRB[4];
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wire fGET = (wOPC == 6'o33) & !wRB[4];
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wire fGET = (wOPC == 6'o33) & !wRB[4];
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// control signals
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// control signals
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localparam [2:0] MUX_SFR = 3'o7,
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localparam [2:0] MUX_SFR = 3'o7,
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MUX_BSF = 3'o6,
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MUX_BSF = 3'o6,
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MUX_MUL = 3'o5,
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MUX_MUL = 3'o5,
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MUX_MEM = 3'o4,
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MUX_MEM = 3'o4,
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MUX_RPC = 3'o2,
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MUX_RPC = 3'o2,
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MUX_ALU = 3'o1,
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MUX_ALU = 3'o1,
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MUX_NOP = 3'o0;
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MUX_NOP = 3'o0;
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always @(posedge gclk)
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always @(posedge gclk)
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if (grst) begin
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if (grst) begin
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/*AUTORESET*/
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/*AUTORESET*/
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// Beginning of autoreset for uninitialized flops
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// Beginning of autoreset for uninitialized flops
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imm_of <= 16'h0;
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imm_of <= 16'h0;
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mux_of <= 3'h0;
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mux_of <= 3'h0;
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opc_of <= 6'h0;
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opc_of <= 6'h0;
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ra_of <= 5'h0;
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ra_of <= 5'h0;
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rd_of <= 5'h0;
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rd_of <= 5'h0;
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// End of automatics
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// End of automatics
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end else if (dena) begin
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end else if (dena) begin
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mux_of <= #1
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mux_of <= #1
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(hzd_bpc | hzd_fwd | fSTR | fRTD | fBCC) ? MUX_NOP :
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(hzd_bpc | hzd_fwd | fSTR | fRTD | fBCC) ? MUX_NOP :
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(fLOD | fGET) ? MUX_MEM :
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(fLOD | fGET) ? MUX_MEM :
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(fMOV) ? MUX_SFR :
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(fMOV) ? MUX_SFR :
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(fMUL) ? MUX_MUL :
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(fMUL) ? MUX_MUL :
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(fBSF) ? MUX_BSF :
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(fBSF) ? MUX_BSF :
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(fBRU) ? MUX_RPC :
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(fBRU) ? MUX_RPC :
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MUX_ALU;
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MUX_ALU;
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opc_of <= #1
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opc_of <= #1
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(hzd_bpc | hzd_fwd) ? 6'o42 : // XOR (SKIP)
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(hzd_bpc | hzd_fwd) ? 6'o42 : // XOR (SKIP)
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wOPC;
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wOPC;
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rd_of <= #1 wRD;
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rd_of <= #1 wRD;
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ra_of <= #1 wRA;
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ra_of <= #1 wRA;
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imm_of <= #1 wIMM;
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imm_of <= #1 wIMM;
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end // if (dena)
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end // if (dena)
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// immediate implementation
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// immediate implementation
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reg [15:0] rIMM0, rIMM1;
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reg [15:0] rIMM0, rIMM1;
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reg rFIM0, rFIM1;
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reg rFIM0, rFIM1;
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//wire wFIMH = (gpha & AEMB_HTX[0]) ? rFIM1 : rFIM0;
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//wire wFIMH = (gpha & AEMB_HTX[0]) ? rFIM1 : rFIM0;
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//wire [15:0] wIMMH = (gpha & AEMB_HTX[0]) ? rIMM1 : rIMM0;
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//wire [15:0] wIMMH = (gpha & AEMB_HTX[0]) ? rIMM1 : rIMM0;
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assign imm_if[15:0] = wIMM;
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assign imm_if[15:0] = wIMM;
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assign imm_if[31:16] = (rFIM1) ? rIMM1 :
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assign imm_if[31:16] = (rFIM1) ? rIMM1 :
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{(16){wIMM[15]}};
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{(16){wIMM[15]}};
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// BARREL IMM
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// BARREL IMM
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always @(posedge gclk)
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always @(posedge gclk)
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if (grst) begin
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if (grst) begin
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/*AUTORESET*/
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/*AUTORESET*/
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// Beginning of autoreset for uninitialized flops
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// Beginning of autoreset for uninitialized flops
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rFIM0 <= 1'h0;
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rFIM0 <= 1'h0;
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rFIM1 <= 1'h0;
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rFIM1 <= 1'h0;
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rIMM0 <= 16'h0;
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rIMM0 <= 16'h0;
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rIMM1 <= 16'h0;
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rIMM1 <= 16'h0;
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// End of automatics
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// End of automatics
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end else if (dena) begin
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end else if (dena) begin
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rFIM1 <= #1 rFIM0;
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rFIM1 <= #1 rFIM0;
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rFIM0 <= #1 fIMM & !hzd_bpc;
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rFIM0 <= #1 fIMM & !hzd_bpc;
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rIMM1 <= #1 rIMM0;
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rIMM1 <= #1 rIMM0;
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rIMM0 <= #1 wIMM;
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rIMM0 <= #1 wIMM;
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end
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end
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assign fINT = brk_if[0] & gpha & !rFIM1;
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assign fINT = brk_if[0] & gpha & !rFIM1;
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// operand latch
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// operand latch
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reg wrb_ex;
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reg wrb_ex;
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reg fwd_ex;
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reg fwd_ex;
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reg [2:0] mux_mx;
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reg [2:0] mux_mx;
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wire opb_fwd, opa_fwd, opd_fwd;
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wire opb_fwd, opa_fwd, opd_fwd;
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assign mux_opb = {wOPC[3], opb_fwd};
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assign mux_opb = {wOPC[3], opb_fwd};
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assign opb_fwd = ((wRB ^ rd_ex) == 5'd0) & // RB forwarding needed
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assign opb_fwd = ((wRB ^ rd_ex) == 5'd0) & // RB forwarding needed
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fwd_ex & wrb_ex;
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fwd_ex & wrb_ex;
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assign mux_opa = {(fBRU|fBCC), opa_fwd};
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assign mux_opa = {(fBRU|fBCC), opa_fwd};
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assign opa_fwd = ((wRA ^ rd_ex) == 5'd0) & // RA forwarding needed
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assign opa_fwd = ((wRA ^ rd_ex) == 5'd0) & // RA forwarding needed
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fwd_ex & wrb_ex;
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fwd_ex & wrb_ex;
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assign mux_opd = {fBCC, opd_fwd};
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assign mux_opd = {fBCC, opd_fwd};
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assign opd_fwd = (( ((wRA ^ rd_ex) == 5'd0) & fBCC) | // RA forwarding
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assign opd_fwd = (( ((wRA ^ rd_ex) == 5'd0) & fBCC) | // RA forwarding
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( ((wRD ^ rd_ex) == 5'd0) & fSTR)) & // RD forwarding
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( ((wRD ^ rd_ex) == 5'd0) & fSTR)) & // RD forwarding
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fwd_ex & wrb_ex;
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fwd_ex & wrb_ex;
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always @(posedge gclk)
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always @(posedge gclk)
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if (grst) begin
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if (grst) begin
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/*AUTORESET*/
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/*AUTORESET*/
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// Beginning of autoreset for uninitialized flops
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// Beginning of autoreset for uninitialized flops
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fwd_ex <= 1'h0;
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fwd_ex <= 1'h0;
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mux_ex <= 3'h0;
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mux_ex <= 3'h0;
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mux_mx <= 3'h0;
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mux_mx <= 3'h0;
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rd_ex <= 5'h0;
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rd_ex <= 5'h0;
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wrb_ex <= 1'h0;
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wrb_ex <= 1'h0;
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// End of automatics
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// End of automatics
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end else if (dena) begin
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end else if (dena) begin
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wrb_ex <= #1 |rd_of & |mux_of; // FIXME: check mux
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wrb_ex <= #1 |rd_of & |mux_of; // FIXME: check mux
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fwd_ex <= #1 |mux_of; // FIXME: check mux
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fwd_ex <= #1 |mux_of; // FIXME: check mux
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mux_mx <= #1 mux_ex;
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mux_mx <= #1 mux_ex;
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mux_ex <= #1 mux_of;
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mux_ex <= #1 mux_of;
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rd_ex <= #1 rd_of;
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rd_ex <= #1 rd_of;
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end
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end
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always @(posedge gclk)
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always @(posedge gclk)
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if (grst) begin
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if (grst) begin
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/*AUTORESET*/
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/*AUTORESET*/
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// Beginning of autoreset for uninitialized flops
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// Beginning of autoreset for uninitialized flops
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opa_of <= 32'h0;
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opa_of <= 32'h0;
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opb_of <= 32'h0;
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opb_of <= 32'h0;
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opd_of <= 32'h0;
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opd_of <= 32'h0;
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// End of automatics
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// End of automatics
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end else if (dena) begin
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end else if (dena) begin
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case (mux_opd)
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case (mux_opd)
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2'o2: opd_of <= #1 opa_if; // BCC
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2'o2: opd_of <= #1 opa_if; // BCC
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2'o1: opd_of <= #1 alu_ex; // FWD
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2'o1: opd_of <= #1 alu_ex; // FWD
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2'o0: opd_of <= #1 opd_if; // SXX
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2'o0: opd_of <= #1 opd_if; // SXX
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2'o3: opd_of <= #1 alu_ex; // FWD
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2'o3: opd_of <= #1 alu_ex; // FWD
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endcase // case (mux_opd)
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endcase // case (mux_opd)
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case (mux_opb)
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case (mux_opb)
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2'o0: opb_of <= #1 opb_if;
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2'o0: opb_of <= #1 opb_if;
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2'o1: opb_of <= #1 alu_ex;
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2'o1: opb_of <= #1 alu_ex;
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2'o2: opb_of <= #1 imm_if;
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2'o2: opb_of <= #1 imm_if;
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2'o3: opb_of <= #1 imm_if;
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2'o3: opb_of <= #1 imm_if;
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endcase // case (mux_opb)
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endcase // case (mux_opb)
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case (mux_opa)
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case (mux_opa)
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2'o0: opa_of <= #1 opa_if;
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2'o0: opa_of <= #1 opa_if;
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2'o1: opa_of <= #1 alu_ex;
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2'o1: opa_of <= #1 alu_ex;
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2'o2: opa_of <= #1 {rpc_if, 2'o0};
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2'o2: opa_of <= #1 {rpc_if, 2'o0};
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2'o3: opa_of <= #1 {rpc_if, 2'o0};
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2'o3: opa_of <= #1 {rpc_if, 2'o0};
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endcase // case (mux_opa)
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endcase // case (mux_opa)
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end // if (dena)
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end // if (dena)
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// Hazard Detection
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// Hazard Detection
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//wire wFMUL = (mux_ex == MUX_MUL);
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//wire wFMUL = (mux_ex == MUX_MUL);
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//wire wFBSF = (mux_ex == MUX_BSF);
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//wire wFBSF = (mux_ex == MUX_BSF);
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//wire wFMEM = (mux_ex == MUX_MEM);
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//wire wFMEM = (mux_ex == MUX_MEM);
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//wire wFMOV = (mux_ex == MUX_SFR);
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//wire wFMOV = (mux_ex == MUX_SFR);
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assign hzd_fwd = (opd_fwd | opa_fwd | opb_fwd) & mux_ex[2];
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assign hzd_fwd = (opd_fwd | opa_fwd | opb_fwd) & mux_ex[2];
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//(wFMUL | wFBSF | wFMEM | wFMOV);
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//(wFMUL | wFBSF | wFMEM | wFMOV);
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assign hzd_bpc = (bra_ex[1] & !bra_ex[0]);
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assign hzd_bpc = (bra_ex[1] & !bra_ex[0]);
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endmodule // aeMB2_ctrl
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endmodule // aeMB2_ctrl
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/*
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/*
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$Log: not supported by cvs2svn $
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$Log: not supported by cvs2svn $
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Revision 1.6 2008/05/01 08:32:58 sybreon
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Revision 1.6 2008/05/01 08:32:58 sybreon
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Added interrupt capability.
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Added interrupt capability.
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Revision 1.5 2008/04/28 08:15:25 sybreon
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Revision 1.5 2008/04/28 08:15:25 sybreon
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Optimisations.
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Optimisations.
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Revision 1.4 2008/04/26 17:57:43 sybreon
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Revision 1.4 2008/04/26 17:57:43 sybreon
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Minor performance improvements.
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Minor performance improvements.
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Revision 1.3 2008/04/26 01:09:05 sybreon
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Revision 1.3 2008/04/26 01:09:05 sybreon
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Passes basic tests. Minor documentation changes to make it compatible with iverilog pre-processor.
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Passes basic tests. Minor documentation changes to make it compatible with iverilog pre-processor.
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Revision 1.2 2008/04/20 16:34:32 sybreon
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Revision 1.2 2008/04/20 16:34:32 sybreon
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Basic version with some features left out.
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Basic version with some features left out.
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Revision 1.1 2008/04/18 00:21:52 sybreon
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Revision 1.1 2008/04/18 00:21:52 sybreon
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Initial import.
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Initial import.
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