/* $Id: aeMB2_iche.v,v 1.5 2008-04-28 00:54:31 sybreon Exp $
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/* $Id: aeMB2_iche.v,v 1.5 2008-04-28 00:54:31 sybreon Exp $
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**
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**
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** AEMB2 EDK 6.2 COMPATIBLE CORE
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** AEMB2 EDK 6.2 COMPATIBLE CORE
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** Copyright (C) 2004-2008 Shawn Tan <shawn.tan@aeste.net>
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** Copyright (C) 2004-2008 Shawn Tan <shawn.tan@aeste.net>
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**
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**
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** This file is part of AEMB.
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** This file is part of AEMB.
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**
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**
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** AEMB is free software: you can redistribute it and/or modify it
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** AEMB is free software: you can redistribute it and/or modify it
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** under the terms of the GNU Lesser General Public License as
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** under the terms of the GNU Lesser General Public License as
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** published by the Free Software Foundation, either version 3 of the
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** published by the Free Software Foundation, either version 3 of the
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** License, or (at your option) any later version.
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** License, or (at your option) any later version.
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**
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**
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** AEMB is distributed in the hope that it will be useful, but WITHOUT
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** AEMB is distributed in the hope that it will be useful, but WITHOUT
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** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General
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** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General
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** Public License for more details.
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** Public License for more details.
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**
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**
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** You should have received a copy of the GNU Lesser General Public
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** You should have received a copy of the GNU Lesser General Public
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** License along with AEMB. If not, see <http:**www.gnu.org/licenses/>.
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** License along with AEMB. If not, see <http:**www.gnu.org/licenses/>.
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*/
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*/
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/**
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/**
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* Instruction Cache Block
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* Instruction Cache Block
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* @file aeMB2_iche.v
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* @file aeMB2_iche.v
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* This is a non-optional instruction cache for single cycle
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* This is a non-optional instruction cache for single cycle
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operations. The maximum line width is 16 words (512 bits)
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operations. The maximum line width is 16 words (512 bits)
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* Single port synchronous RAM is used as the main cache DATA
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* Single port synchronous RAM is used as the main cache DATA
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block. A single port asynchronous RAM is used as the TAG block.
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block. A single port asynchronous RAM is used as the TAG block.
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* The sizes need to be selected carefully to minimise resource
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* The sizes need to be selected carefully to minimise resource
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wastage. Details are provided in the documentation.
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wastage. Details are provided in the documentation.
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*/
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*/
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// 63@158 - X3S
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// 63@158 - X3S
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module aeMB2_iche (/*AUTOARG*/
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module aeMB2_iche (/*AUTOARG*/
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// Outputs
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// Outputs
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ich_dat, ich_hit, ich_fb,
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ich_dat, ich_hit, ich_fb,
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// Inputs
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// Inputs
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ich_adr, iwb_dat_i, iwb_ack_i, gclk, grst, iena, gpha
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ich_adr, iwb_dat_i, iwb_ack_i, gclk, grst, iena, gpha
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);
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);
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parameter AEMB_IWB = 32;
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parameter AEMB_IWB = 32;
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parameter AEMB_ICH = 11;
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parameter AEMB_ICH = 11;
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parameter AEMB_IDX = 6;
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parameter AEMB_IDX = 6;
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parameter AEMB_HTX = 1;
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parameter AEMB_HTX = 1;
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// Cache
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// Cache
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input [AEMB_IWB-1:2] ich_adr;
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input [AEMB_IWB-1:2] ich_adr;
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output [31:0] ich_dat;
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output [31:0] ich_dat;
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output ich_hit; ///< cache hit
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output ich_hit; ///< cache hit
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output ich_fb; ///< cache hit
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output ich_fb; ///< cache hit
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// Wishbone
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// Wishbone
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input [31:0] iwb_dat_i;
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input [31:0] iwb_dat_i;
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input iwb_ack_i;
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input iwb_ack_i;
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// SYS signals
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// SYS signals
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input gclk,
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input gclk,
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grst,
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grst,
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iena,
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iena,
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gpha;
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gpha;
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// SOME MATH
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// SOME MATH
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localparam SIZ = AEMB_ICH-2; // 2^SIZ entries
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localparam SIZ = AEMB_ICH-2; // 2^SIZ entries
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localparam BLK = AEMB_ICH-AEMB_IDX; // 2^BLK blocks
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localparam BLK = AEMB_ICH-AEMB_IDX; // 2^BLK blocks
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localparam LNE = AEMB_IDX-2; // 2^LNE lines per block
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localparam LNE = AEMB_IDX-2; // 2^LNE lines per block
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localparam TAG = AEMB_IWB-AEMB_ICH; // TAG length
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localparam TAG = AEMB_IWB-AEMB_ICH; // TAG length
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localparam VAL = (1<<LNE); // VAL values (max 16)
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localparam VAL = (1<<LNE); // VAL values (max 16)
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/*AUTOWIRE*/
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/*AUTOWIRE*/
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/*AUTOREG*/
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/*AUTOREG*/
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assign ich_fb = ich_hit;
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assign ich_fb = ich_hit;
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// 1-of-X decoder
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// 1-of-X decoder
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// FIXME: Make decoder dynamic.
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// FIXME: Make decoder dynamic.
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// TODO: Factorise into primitive
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// TODO: Factorise into primitive
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reg [VAL:1] rDEC;
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reg [VAL:1] rDEC;
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always @(/*AUTOSENSE*/ich_adr)
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always @(/*AUTOSENSE*/ich_adr)
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case (ich_adr[AEMB_IDX-1:2])
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case (ich_adr[AEMB_IDX-1:2])
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4'h0: rDEC <= #1 16'h0001;
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4'h0: rDEC <= #1 16'h0001;
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4'h1: rDEC <= #1 16'h0002;
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4'h1: rDEC <= #1 16'h0002;
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4'h2: rDEC <= #1 16'h0004;
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4'h2: rDEC <= #1 16'h0004;
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4'h3: rDEC <= #1 16'h0008;
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4'h3: rDEC <= #1 16'h0008;
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4'h4: rDEC <= #1 16'h0010;
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4'h4: rDEC <= #1 16'h0010;
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4'h5: rDEC <= #1 16'h0020;
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4'h5: rDEC <= #1 16'h0020;
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4'h6: rDEC <= #1 16'h0040;
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4'h6: rDEC <= #1 16'h0040;
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4'h7: rDEC <= #1 16'h0080;
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4'h7: rDEC <= #1 16'h0080;
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4'h8: rDEC <= #1 16'h0100;
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4'h8: rDEC <= #1 16'h0100;
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4'h9: rDEC <= #1 16'h0200;
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4'h9: rDEC <= #1 16'h0200;
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4'hA: rDEC <= #1 16'h0400;
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4'hA: rDEC <= #1 16'h0400;
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4'hB: rDEC <= #1 16'h0800;
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4'hB: rDEC <= #1 16'h0800;
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4'hC: rDEC <= #1 16'h1000;
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4'hC: rDEC <= #1 16'h1000;
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4'hD: rDEC <= #1 16'h2000;
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4'hD: rDEC <= #1 16'h2000;
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4'hE: rDEC <= #1 16'h4000;
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4'hE: rDEC <= #1 16'h4000;
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4'hF: rDEC <= #1 16'h8000;
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4'hF: rDEC <= #1 16'h8000;
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endcase // case (ich_adr[AEMB_IDX-1:2])
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endcase // case (ich_adr[AEMB_IDX-1:2])
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wire [VAL:1] wDEC = rDEC[VAL:1]; // resize decoder
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wire [VAL:1] wDEC = rDEC[VAL:1]; // resize decoder
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// explode the address bits
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// explode the address bits
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wire [VAL:1] oVAL, iVAL;
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wire [VAL:1] oVAL, iVAL;
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wire [SIZ:1] aLNE = ich_adr[AEMB_ICH-1:2]; // line address
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wire [SIZ:1] aLNE = ich_adr[AEMB_ICH-1:2]; // line address
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wire [BLK:1] aTAG = ich_adr[AEMB_ICH-1:AEMB_IDX]; // block address
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wire [BLK:1] aTAG = ich_adr[AEMB_ICH-1:AEMB_IDX]; // block address
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wire [TAG:1] iTAG = ich_adr[AEMB_IWB-1:AEMB_ICH]; // current TAG value
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wire [TAG:1] iTAG = ich_adr[AEMB_IWB-1:AEMB_ICH]; // current TAG value
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wire [TAG:1] oTAG;
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wire [TAG:1] oTAG;
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// HIT CHECKS
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// HIT CHECKS
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wire hTAG = ((iTAG ^ oTAG) == {(TAG){1'b0}}); // 100.0
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wire hTAG = ((iTAG ^ oTAG) == {(TAG){1'b0}}); // 100.0
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//~|(iTAG ^ oTAG); // 98
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//~|(iTAG ^ oTAG); // 98
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//(iTAG == oTAG); // 85
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//(iTAG == oTAG); // 85
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wire hVAL = //|(oVAL & wDEC);
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wire hVAL = //|(oVAL & wDEC);
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((oVAL & wDEC) != {(VAL){1'b0}});
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((oVAL & wDEC) != {(VAL){1'b0}});
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assign ich_hit = hTAG & hVAL;
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assign ich_hit = hTAG & hVAL;
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assign iVAL = (hTAG) ? // BLOCK/LINE fill check
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assign iVAL = (hTAG) ? // BLOCK/LINE fill check
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oVAL | wDEC : // LINE fill
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oVAL | wDEC : // LINE fill
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wDEC; // BLOCK replace
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wDEC; // BLOCK replace
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/*
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/*
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aeMB2_tpsram AUTO_TEMPLATE (
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aeMB2_tpsram AUTO_TEMPLATE (
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.AW(SIZ),
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.AW(SIZ),
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.DW(6'd32),
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.DW(6'd32),
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.dat_o(),
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.dat_o(),
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.dat_i(iwb_dat_i[31:0]),
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.dat_i(iwb_dat_i[31:0]),
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.adr_i(aLNE[SIZ:1]),
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.adr_i(aLNE[SIZ:1]),
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.rst_i(),
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.rst_i(),
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.ena_i(iwb_ack_i),
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.ena_i(iwb_ack_i),
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.clk_i(gclk),
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.clk_i(gclk),
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.wre_i(iwb_ack_i),
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.wre_i(iwb_ack_i),
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.xdat_o(ich_dat[31:0]),
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.xdat_o(ich_dat[31:0]),
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.xdat_i(),
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.xdat_i(),
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.xadr_i(aLNE[SIZ:1]),
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.xadr_i(aLNE[SIZ:1]),
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.xrst_i(grst),
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.xrst_i(grst),
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.xena_i(iena),
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.xena_i(iena),
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.xclk_i(gclk),
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.xclk_i(gclk),
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.xwre_i(),
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.xwre_i(),
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)
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)
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aeMB2_sparam AUTO_TEMPLATE (
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aeMB2_sparam AUTO_TEMPLATE (
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.AW(BLK),
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.AW(BLK),
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.DW(VAL+TAG),
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.DW(VAL+TAG),
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.dat_o({oVAL, oTAG}),
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.dat_o({oVAL, oTAG}),
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.dat_i({iVAL, iTAG}),
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.dat_i({iVAL, iTAG}),
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.adr_i(aTAG[BLK:1]),
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.adr_i(aTAG[BLK:1]),
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.ena_i(iwb_ack_i),
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.ena_i(iwb_ack_i),
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.clk_i(gclk),
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.clk_i(gclk),
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.wre_i(iwb_ack_i),
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.wre_i(iwb_ack_i),
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)
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)
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*/
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*/
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// CACHE TAG BLOCK
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// CACHE TAG BLOCK
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aeMB2_sparam
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aeMB2_sparam
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#(/*AUTOINSTPARAM*/
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#(/*AUTOINSTPARAM*/
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// Parameters
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// Parameters
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.AW (BLK), // Templated
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.AW (BLK), // Templated
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.DW (VAL+TAG)) // Templated
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.DW (VAL+TAG)) // Templated
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tag0
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tag0
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(/*AUTOINST*/
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(/*AUTOINST*/
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// Outputs
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// Outputs
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.dat_o ({oVAL, oTAG}), // Templated
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.dat_o ({oVAL, oTAG}), // Templated
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// Inputs
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// Inputs
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.adr_i (aTAG[BLK:1]), // Templated
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.adr_i (aTAG[BLK:1]), // Templated
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.dat_i ({iVAL, iTAG}), // Templated
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.dat_i ({iVAL, iTAG}), // Templated
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.wre_i (iwb_ack_i), // Templated
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.wre_i (iwb_ack_i), // Templated
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.clk_i (gclk), // Templated
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.clk_i (gclk), // Templated
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.ena_i (iwb_ack_i)); // Templated
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.ena_i (iwb_ack_i)); // Templated
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// CACHE DATA BLOCK
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// CACHE DATA BLOCK
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// Writes on successful IWB bus transfers.
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// Writes on successful IWB bus transfers.
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// Reads on pipeline enable.
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// Reads on pipeline enable.
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aeMB2_tpsram
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aeMB2_tpsram
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#(/*AUTOINSTPARAM*/
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#(/*AUTOINSTPARAM*/
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// Parameters
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// Parameters
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.AW (SIZ), // Templated
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.AW (SIZ), // Templated
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.DW (6'd32)) // Templated
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.DW (6'd32)) // Templated
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data0
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data0
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(/*AUTOINST*/
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(/*AUTOINST*/
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// Outputs
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// Outputs
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.dat_o (), // Templated
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.dat_o (), // Templated
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.xdat_o (ich_dat[31:0]), // Templated
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.xdat_o (ich_dat[31:0]), // Templated
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// Inputs
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// Inputs
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.adr_i (aLNE[SIZ:1]), // Templated
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.adr_i (aLNE[SIZ:1]), // Templated
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.dat_i (iwb_dat_i[31:0]), // Templated
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.dat_i (iwb_dat_i[31:0]), // Templated
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.wre_i (iwb_ack_i), // Templated
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.wre_i (iwb_ack_i), // Templated
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.ena_i (iwb_ack_i), // Templated
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.ena_i (iwb_ack_i), // Templated
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.rst_i (), // Templated
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.rst_i (), // Templated
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.clk_i (gclk), // Templated
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.clk_i (gclk), // Templated
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.xadr_i (aLNE[SIZ:1]), // Templated
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.xadr_i (aLNE[SIZ:1]), // Templated
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.xdat_i (), // Templated
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.xdat_i (), // Templated
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.xwre_i (), // Templated
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.xwre_i (), // Templated
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.xena_i (iena), // Templated
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.xena_i (iena), // Templated
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.xrst_i (grst), // Templated
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.xrst_i (grst), // Templated
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.xclk_i (gclk)); // Templated
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.xclk_i (gclk)); // Templated
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endmodule // aeMB2_iche
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endmodule // aeMB2_iche
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/*
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/*
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$Log: not supported by cvs2svn $
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$Log: not supported by cvs2svn $
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Revision 1.4 2008/04/26 17:57:43 sybreon
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Revision 1.4 2008/04/26 17:57:43 sybreon
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Minor performance improvements.
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Minor performance improvements.
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Revision 1.3 2008/04/26 01:09:06 sybreon
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Revision 1.3 2008/04/26 01:09:06 sybreon
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Passes basic tests. Minor documentation changes to make it compatible with iverilog pre-processor.
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Passes basic tests. Minor documentation changes to make it compatible with iverilog pre-processor.
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Revision 1.2 2008/04/20 16:34:32 sybreon
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Revision 1.2 2008/04/20 16:34:32 sybreon
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Basic version with some features left out.
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Basic version with some features left out.
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Revision 1.1 2008/04/18 00:21:52 sybreon
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Revision 1.1 2008/04/18 00:21:52 sybreon
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Initial import.
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Initial import.
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