/* $Id: aeMB2_intu.v,v 1.7 2008-05-01 12:00:18 sybreon Exp $
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/* $Id: aeMB2_intu.v,v 1.7 2008-05-01 12:00:18 sybreon Exp $
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**
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**
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** AEMB2 EDK 6.2 COMPATIBLE CORE
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** AEMB2 EDK 6.2 COMPATIBLE CORE
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** Copyright (C) 2004-2008 Shawn Tan <shawn.tan@aeste.net>
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** Copyright (C) 2004-2008 Shawn Tan <shawn.tan@aeste.net>
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**
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**
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** This file is part of AEMB.
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** This file is part of AEMB.
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**
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**
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** AEMB is free software: you can redistribute it and/or modify it
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** AEMB is free software: you can redistribute it and/or modify it
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** under the terms of the GNU Lesser General Public License as
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** under the terms of the GNU Lesser General Public License as
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** published by the Free Software Foundation, either version 3 of the
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** published by the Free Software Foundation, either version 3 of the
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** License, or (at your option) any later version.
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** License, or (at your option) any later version.
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**
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**
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** AEMB is distributed in the hope that it will be useful, but WITHOUT
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** AEMB is distributed in the hope that it will be useful, but WITHOUT
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** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General
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** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General
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** Public License for more details.
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** Public License for more details.
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**
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**
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** You should have received a copy of the GNU Lesser General Public
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** You should have received a copy of the GNU Lesser General Public
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** License along with AEMB. If not, see <http:**www.gnu.org/licenses/>.
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** License along with AEMB. If not, see <http:**www.gnu.org/licenses/>.
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*/
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*/
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/**
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/**
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* One Cycle Integer Unit
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* One Cycle Integer Unit
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* @file aeMB2_intu.v
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* @file aeMB2_intu.v
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* This implements a single cycle integer unit. It performs all basic
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* This implements a single cycle integer unit. It performs all basic
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arithmetic, shift, and logic operations.
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arithmetic, shift, and logic operations.
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*/
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*/
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module aeMB2_intu (/*AUTOARG*/
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module aeMB2_intu (/*AUTOARG*/
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// Outputs
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// Outputs
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mem_ex, bpc_ex, alu_ex, alu_mx, msr_ex, sfr_mx,
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mem_ex, bpc_ex, alu_ex, alu_mx, msr_ex, sfr_mx,
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// Inputs
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// Inputs
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opc_of, opa_of, opb_of, opd_of, imm_of, rd_of, ra_of, gclk, grst,
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exc_dwb, exc_ill, rpc_ex, opc_of, opa_of, opb_of, opd_of, imm_of,
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dena, gpha
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rd_of, ra_of, gclk, grst, dena, gpha
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);
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);
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parameter AEMB_DWB = 32;
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parameter AEMB_DWB = 32;
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parameter AEMB_IWB = 32;
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parameter AEMB_IWB = 32;
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parameter AEMB_HTX = 1;
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parameter AEMB_HTX = 1;
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output [31:2] mem_ex;
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output [31:2] mem_ex;
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output [31:2] bpc_ex;
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output [31:2] bpc_ex;
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output [31:0] alu_ex,
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output [31:0] alu_ex,
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alu_mx;
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alu_mx;
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input [1:0] exc_dwb;
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input exc_ill;
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input [31:2] rpc_ex;
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//input [2:0] mux_of;
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//input [2:0] mux_of;
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input [5:0] opc_of;
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input [5:0] opc_of;
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input [31:0] opa_of;
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input [31:0] opa_of;
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input [31:0] opb_of;
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input [31:0] opb_of;
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input [31:0] opd_of;
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input [31:0] opd_of;
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input [15:0] imm_of;
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input [15:0] imm_of;
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input [4:0] rd_of,
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input [4:0] rd_of,
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ra_of;
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ra_of;
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output [9:0] msr_ex;
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output [9:0] msr_ex;
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output [31:0] sfr_mx;
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output [31:0] sfr_mx;
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// SYS signals
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// SYS signals
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input gclk,
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input gclk,
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grst,
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grst,
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dena,
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dena,
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gpha;
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gpha;
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/*AUTOREG*/
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/*AUTOREG*/
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// Beginning of automatic regs (for this module's undeclared outputs)
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// Beginning of automatic regs (for this module's undeclared outputs)
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reg [31:0] alu_ex;
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reg [31:0] alu_ex;
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reg [31:0] alu_mx;
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reg [31:0] alu_mx;
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reg [31:2] bpc_ex;
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reg [31:2] bpc_ex;
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reg [31:2] mem_ex;
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reg [31:2] mem_ex;
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reg [31:0] sfr_mx;
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reg [31:0] sfr_mx;
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// End of automatics
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// End of automatics
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localparam [2:0] MUX_SFR = 3'o7,
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localparam [2:0] MUX_SFR = 3'o7,
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MUX_BSF = 3'o6,
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MUX_BSF = 3'o6,
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MUX_MUL = 3'o5,
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MUX_MUL = 3'o5,
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MUX_MEM = 3'o4,
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MUX_MEM = 3'o4,
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MUX_RPC = 3'o2,
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MUX_RPC = 3'o2,
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MUX_ALU = 3'o1,
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MUX_ALU = 3'o1,
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MUX_NOP = 3'o0;
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MUX_NOP = 3'o0;
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reg rMSR_C,
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reg rMSR_C,
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rMSR_EE,
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rMSR_EE,
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rMSR_EIP,
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rMSR_EIP,
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rMSR_CC,
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rMSR_CC,
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rMSR_MTX,
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rMSR_MTX,
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rMSR_DTE,
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rMSR_DTE,
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rMSR_ITE,
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rMSR_ITE,
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rMSR_BIP,
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rMSR_BIP,
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rMSR_IE,
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rMSR_IE,
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rMSR_BE;
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rMSR_BE;
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reg [31:0] rEAR,
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rEAR_C;
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reg [1:0] rESR,
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rESR_C;
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// Infer a ADD with carry cell because ADDSUB cannot be inferred
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// Infer a ADD with carry cell because ADDSUB cannot be inferred
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// across technologies.
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// across technologies.
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reg [31:0] add_ex;
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reg [31:0] add_ex;
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reg add_c;
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reg add_c;
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wire [31:0] wADD;
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wire [31:0] wADD;
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wire wADC;
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wire wADC;
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wire fCCC = !opc_of[5] & opc_of[1]; // & !opc_of[4]
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wire fCCC = !opc_of[5] & opc_of[1]; // & !opc_of[4]
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wire fSUB = !opc_of[5] & opc_of[0]; // & !opc_of[4]
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wire fSUB = !opc_of[5] & opc_of[0]; // & !opc_of[4]
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wire fCMP = !opc_of[3] & imm_of[1]; // unsigned only
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wire fCMP = !opc_of[3] & imm_of[1]; // unsigned only
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wire wCMP = (fCMP) ? !wADC : wADD[31]; // cmpu adjust
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wire wCMP = (fCMP) ? !wADC : wADD[31]; // cmpu adjust
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wire [31:0] wOPA = (fSUB) ? ~opa_of : opa_of;
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wire [31:0] wOPA = (fSUB) ? ~opa_of : opa_of;
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wire wOPC = (fCCC) ? rMSR_CC : fSUB;
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wire wOPC = (fCCC) ? rMSR_CC : fSUB;
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assign {wADC, wADD} = (opb_of + wOPA) + wOPC; // add carry
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assign {wADC, wADD} = (opb_of + wOPA) + wOPC; // add carry
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always @(/*AUTOSENSE*/wADC or wADD or wCMP) begin
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always @(/*AUTOSENSE*/wADC or wADD or wCMP) begin
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{add_c, add_ex} <= #1 {wADC, wCMP, wADD[30:0]}; // add with carry
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{add_c, add_ex} <= #1 {wADC, wCMP, wADD[30:0]}; // add with carry
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end
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end
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// SHIFT/LOGIC/MOVE
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// SHIFT/LOGIC/MOVE
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reg [31:0] slm_ex;
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reg [31:0] slm_ex;
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always @(/*AUTOSENSE*/imm_of or opa_of or opb_of or opc_of
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always @(/*AUTOSENSE*/imm_of or opa_of or opb_of or opc_of
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or rMSR_CC)
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or rMSR_CC)
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case (opc_of[2:0])
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case (opc_of[2:0])
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// LOGIC
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// LOGIC
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3'o0: slm_ex <= #1 opa_of | opb_of;
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3'o0: slm_ex <= #1 opa_of | opb_of;
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3'o1: slm_ex <= #1 opa_of & opb_of;
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3'o1: slm_ex <= #1 opa_of & opb_of;
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3'o2: slm_ex <= #1 opa_of ^ opb_of;
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3'o2: slm_ex <= #1 opa_of ^ opb_of;
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3'o3: slm_ex <= #1 opa_of & ~opb_of;
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3'o3: slm_ex <= #1 opa_of & ~opb_of;
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// SHIFT/SEXT
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// SHIFT/SEXT
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3'o4: case ({imm_of[6:5],imm_of[0]})
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3'o4: case ({imm_of[6:5],imm_of[0]})
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3'o1: slm_ex <= #1 {opa_of[31],opa_of[31:1]}; // SRA
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3'o1: slm_ex <= #1 {opa_of[31],opa_of[31:1]}; // SRA
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3'o3: slm_ex <= #1 {rMSR_CC,opa_of[31:1]}; // SRC
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3'o3: slm_ex <= #1 {rMSR_CC,opa_of[31:1]}; // SRC
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3'o5: slm_ex <= #1 {1'b0,opa_of[31:1]}; // SRL
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3'o5: slm_ex <= #1 {1'b0,opa_of[31:1]}; // SRL
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3'o6: slm_ex <= #1 {{(24){opa_of[7]}}, opa_of[7:0]}; // SEXT8
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3'o6: slm_ex <= #1 {{(24){opa_of[7]}}, opa_of[7:0]}; // SEXT8
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3'o7: slm_ex <= #1 {{(16){opa_of[15]}}, opa_of[15:0]}; // SEXT16
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3'o7: slm_ex <= #1 {{(16){opa_of[15]}}, opa_of[15:0]}; // SEXT16
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default: slm_ex <= #1 32'hX;
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default: slm_ex <= #1 32'hX;
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endcase // case ({imm_of[6:5],imm_of[0]})
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endcase // case ({imm_of[6:5],imm_of[0]})
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// MFS/MTS/MSET/MCLR
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// MFS/MTS/MSET/MCLR
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//3'o5: slm_ex <= #1 sfr_of;
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//3'o5: slm_ex <= #1 sfr_of;
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// BRL (PC from SFR)
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// BRL (PC from SFR)
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//3'o6: slm_ex <= #1 sfr_of;
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//3'o6: slm_ex <= #1 sfr_of;
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default: slm_ex <= #1 32'hX;
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default: slm_ex <= #1 32'hX;
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endcase // case (opc_of[2:0])
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endcase // case (opc_of[2:0])
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// ALU RESULT
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// ALU RESULT
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always @(posedge gclk)
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always @(posedge gclk)
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if (grst) begin
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if (grst) begin
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/*AUTORESET*/
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/*AUTORESET*/
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// Beginning of autoreset for uninitialized flops
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// Beginning of autoreset for uninitialized flops
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alu_ex <= 32'h0;
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alu_ex <= 32'h0;
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alu_mx <= 32'h0;
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alu_mx <= 32'h0;
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bpc_ex <= 30'h0;
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bpc_ex <= 30'h0;
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mem_ex <= 30'h0;
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mem_ex <= 30'h0;
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// End of automatics
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// End of automatics
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end else if (dena) begin
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end else if (dena) begin
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alu_mx <= #1 alu_ex;
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alu_mx <= #1 alu_ex;
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alu_ex <= #1 (opc_of[5]) ? slm_ex : add_ex;
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alu_ex <= #1 (opc_of[5]) ? slm_ex : add_ex;
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mem_ex <= #1 wADD[AEMB_DWB-1:2]; // LXX/SXX
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mem_ex <= #1 wADD[AEMB_DWB-1:2]; // LXX/SXX
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bpc_ex <= #1
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bpc_ex <= #1
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(!opc_of[0] & ra_of[3]) ? // check for BRA
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(!opc_of[0] & ra_of[3]) ? // check for BRA
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opb_of[AEMB_IWB-1:2] : // BRA only
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opb_of[AEMB_IWB-1:2] : // BRA only
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wADD[AEMB_IWB-1:2]; // RTD/BCC/BR
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wADD[AEMB_IWB-1:2]; // RTD/BCC/BR
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end
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end
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// MSR SECTION
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// MSR SECTION
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/*
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/*
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MSR REGISTER
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MSR REGISTER
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We should keep common configuration bits in the lower 16-bits of
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We should keep common configuration bits in the lower 16-bits of
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the MSR in order to avoid using the IMMI instruction.
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the MSR in order to avoid using the IMMI instruction.
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MSR bits
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MSR bits
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31 - CC (carry copy)
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31 - CC (carry copy)
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30 - HTE (hardware thread enabled)
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30 - HTE (hardware thread enabled)
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29 - PHA (current phase)
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29 - PHA (current phase)
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9 - EIP (exception in progress)
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8 - EE (exception enable)
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7 - DTE (data cache enable)
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7 - DTE (data cache enable)
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5 - ITE (instruction cache enable)
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5 - ITE (instruction cache enable)
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4 - MTX (hardware mutex bit)
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4 - MTX (hardware mutex bit)
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3 - BIP (break in progress)
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3 - BIP (break in progress)
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2 - C (carry flag)
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2 - C (carry flag)
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1 - IE (interrupt enable)
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1 - IE (interrupt enable)
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0 - BE (bus-lock enable)
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0 - BE (bus-lock enable)
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*/
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*/
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assign msr_ex = {
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assign msr_ex = {
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rMSR_EIP,
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rMSR_EIP,
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rMSR_EE,
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rMSR_EE,
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rMSR_DTE,
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rMSR_DTE,
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1'b0,
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1'b0,
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rMSR_ITE,
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rMSR_ITE,
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rMSR_MTX,
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rMSR_MTX,
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rMSR_BIP,
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rMSR_BIP,
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rMSR_C,
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rMSR_C,
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rMSR_IE,
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rMSR_IE,
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rMSR_BE
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rMSR_BE
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};
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};
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// MSRSET/MSRCLR (small ALU)
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// MSRSET/MSRCLR (small ALU)
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wire [9:0] wRES = (ra_of[0]) ?
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wire [9:0] wRES = (ra_of[0]) ?
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(msr_ex[9:0]) & ~imm_of[9:0] : // MSRCLR
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(msr_ex[9:0]) & ~imm_of[9:0] : // MSRCLR
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(msr_ex[9:0]) | imm_of[9:0]; // MSRSET
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(msr_ex[9:0]) | imm_of[9:0]; // MSRSET
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// 0 - Break
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// 0 - Break
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// 1 - Interrupt
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// 1 - Interrupt
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// 2 - Exception
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// 2 - Exception
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// 3 - Reserved
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// 3 - Reserved
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// break
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// break
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wire fRTBD = (opc_of == 6'o55) & rd_of[1];
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wire fRTBD = (opc_of == 6'o55) & rd_of[1];
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wire fBRKB = ((opc_of == 6'o46) | (opc_of == 6'o56)) & (ra_of[4:0] == 5'hC);
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wire fBRKB = ((opc_of == 6'o46) | (opc_of == 6'o56)) & (ra_of[4:0] == 5'hC);
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// interrupt
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// interrupt
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wire fRTID = (opc_of == 6'o55) & rd_of[0];
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wire fRTID = (opc_of == 6'o55) & rd_of[0];
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wire fBRKI = (opc_of == 6'o56) & (ra_of[4:0] == 5'hD);
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wire fBRKI = (opc_of == 6'o56) & (ra_of[4:0] == 5'hD);
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// exception
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// exception
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wire fRTED = (opc_of == 6'o55) & rd_of[2];
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wire fRTED = (opc_of == 6'o55) & rd_of[2];
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wire fBRKE = (opc_of == 6'o56) & (ra_of[4:0] == 5'hE);
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wire fBRKE = (opc_of == 6'o56) & (ra_of[4:0] == 5'hE);
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wire fMOV = (opc_of == 6'o45);
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wire fMOV = (opc_of == 6'o45);
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wire fMTS = fMOV & &imm_of[15:14];
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wire fMTS = fMOV & &imm_of[15:14];
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wire fMOP = fMOV & ~|imm_of[15:14];
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wire fMOP = fMOV & ~|imm_of[15:14];
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wire fMFS = fMOV & imm_of[15] & !imm_of[14];
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reg [31:0] sfr_ex;
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reg [31:0] sfr_ex;
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reg [2:0] sfr_sel;
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always @(posedge gclk)
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always @(posedge gclk)
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if (grst) begin
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if (grst) begin
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/*AUTORESET*/
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/*AUTORESET*/
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// Beginning of autoreset for uninitialized flops
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// Beginning of autoreset for uninitialized flops
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rMSR_BE <= 1'h0;
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rMSR_BIP <= 1'h0;
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rMSR_DTE <= 1'h0;
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rMSR_EE <= 1'h0;
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rMSR_EIP <= 1'h0;
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rMSR_IE <= 1'h0;
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rMSR_ITE <= 1'h0;
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rMSR_MTX <= 1'h0;
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sfr_ex <= 32'h0;
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sfr_ex <= 32'h0;
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sfr_mx <= 32'h0;
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sfr_mx <= 32'h0;
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sfr_sel <= 3'h0;
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// End of automatics
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// End of automatics
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end else if (dena) begin // if (grst)
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end else if (dena) begin
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sfr_mx <= #1 sfr_ex;
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case (sfr_sel[2:0])
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//3'o0: sfr_mx <= #1 {rpc_ex[31:2], 2'o0};
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3'o5: sfr_mx <= #1 {30'd0, rESR_C};
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3'o3: sfr_mx <= #1 rEAR_C;
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3'o1: sfr_mx <= #1 {rMSR_C,
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AEMB_HTX[0],
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gpha,
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19'd0,
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rMSR_EIP,
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rMSR_EE,
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rMSR_DTE,
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1'b0,
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rMSR_ITE,
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rMSR_MTX,
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rMSR_BIP,
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rMSR_C,
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rMSR_IE,
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rMSR_BE
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};
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default: sfr_mx <= #1 sfr_ex;
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endcase // case (imm_of[2:0])
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sfr_ex <= #1
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sfr_ex <= #1
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{rMSR_CC,
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{rMSR_CC,
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AEMB_HTX[0],
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AEMB_HTX[0],
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gpha,
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gpha,
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21'd0,
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19'd0,
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rMSR_EIP,
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rMSR_EE,
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rMSR_DTE,
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rMSR_DTE,
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1'b0,
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1'b0,
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rMSR_ITE,
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rMSR_ITE,
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rMSR_MTX,
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rMSR_MTX,
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rMSR_BIP,
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rMSR_BIP,
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rMSR_CC,
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rMSR_CC,
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rMSR_IE,
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rMSR_IE,
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rMSR_BE
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rMSR_BE
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};
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};
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sfr_sel <= #1 imm_of[2:0];
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|
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end
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always @(posedge gclk)
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if (grst) begin
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/*AUTORESET*/
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// Beginning of autoreset for uninitialized flops
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rMSR_BE <= 1'h0;
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rMSR_BIP <= 1'h0;
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rMSR_DTE <= 1'h0;
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|
rMSR_EE <= 1'h0;
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rMSR_EIP <= 1'h0;
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rMSR_IE <= 1'h0;
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rMSR_ITE <= 1'h0;
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rMSR_MTX <= 1'h0;
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// End of automatics
|
|
end else if (dena) begin // if (grst)
|
rMSR_DTE <= #1
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rMSR_DTE <= #1
|
(fMTS) ? opa_of[7] :
|
(fMTS) ? opa_of[7] :
|
(fMOP) ? wRES[7] :
|
(fMOP) ? wRES[7] :
|
rMSR_DTE;
|
rMSR_DTE;
|
|
|
rMSR_ITE <= #1
|
rMSR_ITE <= #1
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(fMTS) ? opa_of[5] :
|
(fMTS) ? opa_of[5] :
|
(fMOP) ? wRES[5] :
|
(fMOP) ? wRES[5] :
|
rMSR_ITE;
|
rMSR_ITE;
|
|
|
rMSR_MTX <= #1
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rMSR_MTX <= #1
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(fMTS) ? opa_of[4] :
|
(fMTS) ? opa_of[4] :
|
(fMOP) ? wRES[4] :
|
(fMOP) ? wRES[4] :
|
rMSR_MTX;
|
rMSR_MTX;
|
|
|
rMSR_BE <= #1
|
rMSR_BE <= #1
|
(fMTS) ? opa_of[0] :
|
(fMTS) ? opa_of[0] :
|
(fMOP) ? wRES[0] :
|
(fMOP) ? wRES[0] :
|
rMSR_BE;
|
rMSR_BE;
|
|
|
rMSR_IE <= #1
|
rMSR_IE <= #1
|
(fBRKI) ? 1'b0 :
|
(fBRKI) ? 1'b0 :
|
(fRTID) ? 1'b1 :
|
(fRTID) ? 1'b1 :
|
(fMTS) ? opa_of[1] :
|
(fMTS) ? opa_of[1] :
|
(fMOP) ? wRES[1] :
|
(fMOP) ? wRES[1] :
|
rMSR_IE;
|
rMSR_IE;
|
|
|
rMSR_BIP <= #1
|
rMSR_BIP <= #1
|
(fBRKB) ? 1'b1 :
|
(fBRKB) ? 1'b1 :
|
(fRTBD) ? 1'b0 :
|
(fRTBD) ? 1'b0 :
|
(fMTS) ? opa_of[3] :
|
(fMTS) ? opa_of[3] :
|
(fMOP) ? wRES[3] :
|
(fMOP) ? wRES[3] :
|
rMSR_BIP;
|
rMSR_BIP;
|
|
|
rMSR_EE <= #1
|
rMSR_EE <= #1
|
(fBRKE) ? 1'b0 :
|
(fBRKE) ? 1'b0 :
|
(fRTED) ? 1'b1 :
|
(fRTED) ? 1'b1 :
|
(fMTS) ? opa_of[8] :
|
(fMTS) ? opa_of[8] :
|
(fMOP) ? wRES[8] :
|
(fMOP) ? wRES[8] :
|
rMSR_EE;
|
rMSR_EE;
|
|
|
rMSR_EIP <= #1
|
rMSR_EIP <= #1
|
(fBRKE) ? 1'b1 :
|
(fBRKE) ? 1'b1 :
|
(fRTED) ? 1'b0 :
|
(fRTED) ? 1'b0 :
|
(fMTS) ? opa_of[9] :
|
(fMTS) ? opa_of[9] :
|
(fMOP) ? wRES[9] :
|
(fMOP) ? wRES[9] :
|
rMSR_EIP;
|
rMSR_EIP;
|
|
|
/*
|
|
|
|
case ({fMTS, fMOP})
|
|
2'o2: {rMSR_DTE,
|
|
rMSR_ITE,
|
|
rMSR_MTX,
|
|
rMSR_BE} <= #1 {opa_of[7],
|
|
opa_of[5],
|
|
opa_of[4],
|
|
opa_of[0]};
|
|
2'o1: {rMSR_DTE,
|
|
rMSR_ITE,
|
|
rMSR_MTX,
|
|
rMSR_BE} <= #1 {wRES[7],
|
|
wRES[5],
|
|
wRES[4],
|
|
wRES[0]};
|
|
default: {rMSR_DTE,
|
|
rMSR_ITE,
|
|
rMSR_MTX,
|
|
rMSR_BE} <= #1 {rMSR_DTE,
|
|
rMSR_ITE,
|
|
rMSR_MTX,
|
|
rMSR_BE};
|
|
endcase // case ({fMTS, fMOP})
|
|
|
|
case ({fMTS, fMOP})
|
|
2'o2: {rMSR_BIP,
|
|
rMSR_IE} <= #1 {opa_of[3],
|
|
opa_of[1]};
|
|
2'o1: {rMSR_BIP,
|
|
rMSR_IE} <= #1 {wRES[3],
|
|
wRES[1]};
|
|
default: begin
|
|
rMSR_BIP <= #1 (fBRKB | fRTBD) ? !rMSR_BIP : rMSR_BIP;
|
|
rMSR_IE <= #1 (fBRKI | fRTID) ? !rMSR_IE : rMSR_IE;
|
|
end
|
|
endcase // case ({fMTS, fMOP})
|
|
*/
|
|
end // if (dena)
|
end // if (dena)
|
|
|
// BARREL C
|
// BARREL C
|
wire fADDSUB = !opc_of[5] & !opc_of[4] & !opc_of[2];
|
wire fADDSUB = !opc_of[5] & !opc_of[4] & !opc_of[2];
|
// (opc_of[5:2] == 4'h0) | (opc_of[5:2] == 4'h2);
|
// (opc_of[5:2] == 4'h0) | (opc_of[5:2] == 4'h2);
|
wire fSHIFT = (opc_of == 6'o44) & &imm_of[6:5];
|
wire fSHIFT = (opc_of == 6'o44) & &imm_of[6:5];
|
|
|
always @(posedge gclk)
|
always @(posedge gclk)
|
if (grst) begin
|
if (grst) begin
|
/*AUTORESET*/
|
/*AUTORESET*/
|
|
// Beginning of autoreset for uninitialized flops
|
|
rEAR_C <= 32'h0;
|
|
rESR_C <= 2'h0;
|
|
rMSR_CC <= 1'h0;
|
|
// End of automatics
|
end else if (dena) begin
|
end else if (dena) begin
|
|
rEAR_C <= #1 rEAR;
|
|
rESR_C <= #1 rESR;
|
|
rMSR_CC <= #1 rMSR_C;
|
|
//sfr_mx <= #1 sfr_ex;
|
end
|
end
|
|
|
always @(posedge gclk)
|
always @(posedge gclk)
|
if (grst) begin
|
if (grst) begin
|
/*AUTORESET*/
|
/*AUTORESET*/
|
// Beginning of autoreset for uninitialized flops
|
// Beginning of autoreset for uninitialized flops
|
|
rEAR <= 32'h0;
|
|
rESR <= 2'h0;
|
rMSR_C <= 1'h0;
|
rMSR_C <= 1'h0;
|
rMSR_CC <= 1'h0;
|
|
// End of automatics
|
// End of automatics
|
end else if (dena) begin
|
end else if (dena) begin
|
rMSR_CC <= #1 rMSR_C;
|
rEAR <= #1 (exc_dwb[1]) ? {mem_ex, 2'o0} : rEAR_C; // LXX/SXX
|
|
|
|
rESR <= #1 (exc_ill | exc_dwb[1]) ?
|
|
{exc_ill, exc_dwb[1]} : rESR_C; // ESR
|
|
|
rMSR_C <= #1
|
rMSR_C <= #1
|
(fMTS) ? opa_of[2] :
|
(fMTS) ? opa_of[2] :
|
(fMOP) ? wRES[2] :
|
(fMOP) ? wRES[2] :
|
(fSHIFT) ? opa_of[0] : // SRA/SRL/SRC
|
(fSHIFT) ? opa_of[0] : // SRA/SRL/SRC
|
(fADDSUB) ? add_c : // ADD/SUB/ADDC/SUBC
|
(fADDSUB) ? add_c : // ADD/SUB/ADDC/SUBC
|
rMSR_CC;
|
rMSR_CC;
|
|
|
/*
|
end // if (dena)
|
case ({fMTS,fMOP,fSHIFT,fADDSUB})
|
|
4'h8: rMSR_C <= #1 opa_of[2];
|
|
4'h4: rMSR_C <= #1 wRES[2];
|
|
4'h2: rMSR_C <= #1 opa_of[0];
|
|
4'h1: rMSR_C <= #1 add_c;
|
|
default: rMSR_C <= #1 rMSR_CC;
|
|
endcase // case ({fMTS,fMOP,fSHIFT,fADDSUB})
|
|
*/
|
|
end
|
|
|
|
endmodule // aeMB2_intu
|
endmodule // aeMB2_intu
|
|
|
|
|
