/* $Id: aeMB2_mult.v,v 1.5 2008-04-28 08:15:25 sybreon Exp $
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/* $Id: aeMB2_mult.v,v 1.5 2008-04-28 08:15:25 sybreon Exp $
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**
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**
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** AEMB2 EDK 6.2 COMPATIBLE CORE
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** AEMB2 EDK 6.2 COMPATIBLE CORE
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** Copyright (C) 2004-2008 Shawn Tan <shawn.tan@aeste.net>
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** Copyright (C) 2004-2008 Shawn Tan <shawn.tan@aeste.net>
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**
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**
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** This file is part of AEMB.
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** This file is part of AEMB.
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**
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**
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** AEMB is free software: you can redistribute it and/or modify it
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** AEMB is free software: you can redistribute it and/or modify it
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** under the terms of the GNU Lesser General Public License as
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** under the terms of the GNU Lesser General Public License as
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** published by the Free Software Foundation, either version 3 of the
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** published by the Free Software Foundation, either version 3 of the
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** License, or (at your option) any later version.
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** License, or (at your option) any later version.
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**
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**
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** AEMB is distributed in the hope that it will be useful, but WITHOUT
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** AEMB is distributed in the hope that it will be useful, but WITHOUT
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** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General
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** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General
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** Public License for more details.
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** Public License for more details.
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**
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**
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** You should have received a copy of the GNU Lesser General Public
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** You should have received a copy of the GNU Lesser General Public
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** License along with AEMB. If not, see <http:**www.gnu.org/licenses/>.
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** License along with AEMB. If not, see <http:**www.gnu.org/licenses/>.
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*/
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*/
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/**
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/**
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* Two Cycle Multiplier Unit
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* Two Cycle Multiplier Unit
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* @file aeMB2_mult.v
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* @file aeMB2_mult.v
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* This implements a 2 cycle multipler to increase clock speed. The
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* This implements a 2 cycle multipler to increase clock speed. The
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multiplier architecture is left to the synthesis tool. Modify this
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multiplier architecture is left to the synthesis tool. Modify this
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to instantiate specific multipliers.
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to instantiate specific multipliers.
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*/
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*/
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// 30 LUTS @ 20 MHZ
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// 30 LUTS @ 20 MHZ
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module aeMB2_mult (/*AUTOARG*/
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module aeMB2_mult (/*AUTOARG*/
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// Outputs
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// Outputs
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mul_mx,
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mul_mx,
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// Inputs
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// Inputs
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opa_of, opb_of, opc_of, gclk, grst, dena, gpha
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opa_of, opb_of, opc_of, gclk, grst, dena, gpha
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);
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);
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parameter AEMB_MUL = 1; ///< implement multiplier
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parameter AEMB_MUL = 1; ///< implement multiplier
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output [31:0] mul_mx;
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output [31:0] mul_mx;
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input [31:0] opa_of;
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input [31:0] opa_of;
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input [31:0] opb_of;
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input [31:0] opb_of;
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input [5:0] opc_of;
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input [5:0] opc_of;
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// SYS signals
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// SYS signals
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input gclk,
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input gclk,
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grst,
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grst,
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dena,
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dena,
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gpha;
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gpha;
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/*AUTOREG*/
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/*AUTOREG*/
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reg [31:0] rOPA, rOPB;
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reg [31:0] rOPA, rOPB;
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reg [31:0] rMUL0,
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reg [31:0] rMUL0,
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rMUL1;
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rMUL1;
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always @(posedge gclk)
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always @(posedge gclk)
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if (grst) begin
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if (grst) begin
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/*AUTORESET*/
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/*AUTORESET*/
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// Beginning of autoreset for uninitialized flops
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// Beginning of autoreset for uninitialized flops
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rMUL0 <= 32'h0;
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rMUL0 <= 32'h0;
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rMUL1 <= 32'h0;
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rMUL1 <= 32'h0;
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rOPA <= 32'h0;
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rOPA <= 32'h0;
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rOPB <= 32'h0;
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rOPB <= 32'h0;
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// End of automatics
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// End of automatics
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end else if (dena) begin
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end else if (dena) begin
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//rMUL1 <= #1 rMUL0;
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//rMUL1 <= #1 rMUL0;
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rMUL1 <= #1 rMUL0; //rOPA * rOPB;
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rMUL1 <= #1 rMUL0; //rOPA * rOPB;
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rMUL0 <= #1 (opa_of * opb_of);
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rMUL0 <= #1 (opa_of * opb_of);
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rOPA <= #1 opa_of;
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rOPA <= #1 opa_of;
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rOPB <= #1 opb_of;
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rOPB <= #1 opb_of;
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end
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end
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assign mul_mx = (AEMB_MUL[0]) ? rMUL1 : 32'hX;
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assign mul_mx = (AEMB_MUL[0]) ? rMUL1 : 32'hX;
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endmodule // aeMB2_mult
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endmodule // aeMB2_mult
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/*
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/*
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$Log: not supported by cvs2svn $
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$Log: not supported by cvs2svn $
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Revision 1.4 2008/04/26 17:57:43 sybreon
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Revision 1.4 2008/04/26 17:57:43 sybreon
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Minor performance improvements.
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Minor performance improvements.
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Revision 1.3 2008/04/26 01:09:06 sybreon
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Revision 1.3 2008/04/26 01:09:06 sybreon
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Passes basic tests. Minor documentation changes to make it compatible with iverilog pre-processor.
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Passes basic tests. Minor documentation changes to make it compatible with iverilog pre-processor.
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Revision 1.2 2008/04/20 16:34:32 sybreon
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Revision 1.2 2008/04/20 16:34:32 sybreon
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Basic version with some features left out.
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Basic version with some features left out.
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Revision 1.1 2008/04/18 00:21:52 sybreon
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Revision 1.1 2008/04/18 00:21:52 sybreon
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Initial import.
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Initial import.
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