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[/] [aemb/] [trunk/] [rtl/] [verilog/] [aeMB2_pipe.v] - Diff between revs 191 and 204

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/* $Id: aeMB2_pipe.v,v 1.4 2008-05-01 08:32:58 sybreon Exp $
/* $Id: aeMB2_pipe.v,v 1.4 2008-05-01 08:32:58 sybreon Exp $
**
**
** AEMB2 EDK 6.2 COMPATIBLE CORE
** AEMB2 EDK 6.2 COMPATIBLE CORE
** Copyright (C) 2004-2008 Shawn Tan <shawn.tan@aeste.net>
** Copyright (C) 2004-2008 Shawn Tan <shawn.tan@aeste.net>
**
**
** This file is part of AEMB.
** This file is part of AEMB.
**
**
** AEMB is free software: you can redistribute it and/or modify it
** AEMB is free software: you can redistribute it and/or modify it
** under the terms of the GNU Lesser General Public License as
** under the terms of the GNU Lesser General Public License as
** published by the Free Software Foundation, either version 3 of the
** published by the Free Software Foundation, either version 3 of the
** License, or (at your option) any later version.
** License, or (at your option) any later version.
**
**
** AEMB is distributed in the hope that it will be useful, but WITHOUT
** AEMB is distributed in the hope that it will be useful, but WITHOUT
** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
** or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
** or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
** Public License for more details.
** Public License for more details.
**
**
** You should have received a copy of the GNU Lesser General Public
** You should have received a copy of the GNU Lesser General Public
** License along with AEMB. If not, see <http:**www.gnu.org/licenses/>.
** License along with AEMB. If not, see <http:**www.gnu.org/licenses/>.
*/
*/
/**
/**
 * System signal controller
 * System signal controller
 * @file aeMB2_pipe.v
 * @file aeMB2_pipe.v
 
 
 * Generates clock, reset, and enable signals. Hardware clock/reset
 * Generates clock, reset, and enable signals. Hardware clock/reset
   managers can be instantiated here.
   managers can be instantiated here.
 
 
 */
 */
 
 
module aeMB2_pipe (/*AUTOARG*/
module aeMB2_pipe (/*AUTOARG*/
   // Outputs
   // Outputs
   brk_if, gpha, gclk, grst, dena, iena,
   brk_if, gpha, gclk, grst, dena, iena,
   // Inputs
   // Inputs
   bra_ex, dwb_fb, xwb_fb, ich_fb, fet_fb, msr_ex, sys_clk_i,
   bra_ex, dwb_fb, xwb_fb, ich_fb, fet_fb, msr_ex, exc_dwb, exc_iwb,
   sys_int_i, sys_rst_i, sys_ena_i
   exc_ill, sys_clk_i, sys_int_i, sys_rst_i, sys_ena_i
   );
   );
   parameter AEMB_HTX = 1;
   parameter AEMB_HTX = 1;
 
 
   output [1:0] brk_if;
   output [1:0] brk_if;
   input [1:0]   bra_ex;
   input [1:0]   bra_ex;
   input        dwb_fb;
   input        dwb_fb;
   input        xwb_fb;
   input        xwb_fb;
   input        ich_fb;
   input        ich_fb;
   input        fet_fb;
   input        fet_fb;
   input [3:0]   msr_ex;
   input [9:0]   msr_ex;
 
 
   output       gpha,
   output       gpha,
                gclk,
                gclk,
                grst,
                grst,
                dena,
                dena,
                iena;
                iena;
 
 
 
   input [1:0]   exc_dwb;
 
   input        exc_iwb;
 
   input        exc_ill;
 
 
   input        sys_clk_i,
   input        sys_clk_i,
                sys_int_i,
                sys_int_i,
                sys_rst_i,
                sys_rst_i,
                sys_ena_i;
                sys_ena_i;
 
 
   /*AUTOREG*/
   /*AUTOREG*/
   // Beginning of automatic regs (for this module's undeclared outputs)
   // Beginning of automatic regs (for this module's undeclared outputs)
   reg [1:0]             brk_if;
   reg [1:0]             brk_if;
   reg                  gpha;
   reg                  gpha;
   // End of automatics
   // End of automatics
   reg [1:0]             rst;
   reg [1:0]             rst;
   reg                  por;
   reg                  por;
   reg                  fet;
   reg                  fet;
   reg                  hit;
   reg                  hit;
 
 
   // Instantiate clock/reset managers
   // Instantiate clock/reset managers
   assign               gclk = sys_clk_i;
   assign               gclk = sys_clk_i;
   assign               grst = !rst[1];
   assign               grst = !rst[1];
 
 
   // run instruction side pipeline
   // run instruction side pipeline
   assign               iena = ich_fb &
   assign               iena = ich_fb &
                               xwb_fb &
                               xwb_fb &
                               dwb_fb &
                               dwb_fb &
                               sys_ena_i;
                               sys_ena_i;
   // run data side pipeline
   // run data side pipeline
   assign               dena = iena;
   assign               dena = iena;
 
 
   // interrupt process
   // interrupt process - latches onto any interrupt until it is handled
   reg                  int_lat; ///< interrupt latch
   reg                  int_lat; ///< interrupt latch
 
 
   always @(posedge sys_clk_i)
   always @(posedge sys_clk_i)
     if (sys_rst_i) begin
     if (sys_rst_i) begin
        /*AUTORESET*/
        /*AUTORESET*/
        // Beginning of autoreset for uninitialized flops
        // Beginning of autoreset for uninitialized flops
        int_lat <= 1'h0;
        int_lat <= 1'h0;
        // End of automatics
        // End of automatics
     end else begin
     end else begin
        int_lat <= #1 msr_ex[1] & (int_lat | sys_int_i);
        int_lat <= #1 msr_ex[1] & (int_lat | sys_int_i);
     end
     end
 
 
 
   // exception process - exceptions handled immediately
 
   wire                 exc_lat; ///< exception latch
 
   assign exc_lat = exc_ill | exc_dwb[1];
 
 
   always @(posedge gclk)
   always @(posedge gclk)
     if (grst) begin
     if (grst) begin
        /*AUTORESET*/
        /*AUTORESET*/
        // Beginning of autoreset for uninitialized flops
        // Beginning of autoreset for uninitialized flops
        brk_if <= 2'h0;
        brk_if <= 2'h0;
        // End of automatics
        // End of automatics
     end else if (dena) begin
     end else if (dena) begin
        brk_if[0] <= #1 !msr_ex[3] & int_lat; // interrupt & not BIP     
        // TODO: consider MSR[9:8]
 
        brk_if[1] <= #1 exc_lat; // HIGH PRIORITY - exception
 
        brk_if[0] <= #1 !exc_lat & !msr_ex[9] & !msr_ex[3] & int_lat; // LOW PRIORITY - interrupt (not BIP/EIP)
     end
     end
 
 
   // RESET DELAY
   // RESET DELAY
   always @(posedge sys_clk_i)
   always @(posedge sys_clk_i)
     if (sys_rst_i) begin
     if (sys_rst_i) begin
        /*AUTORESET*/
        /*AUTORESET*/
        // Beginning of autoreset for uninitialized flops
        // Beginning of autoreset for uninitialized flops
        rst <= 2'h0;
        rst <= 2'h0;
        // End of automatics
        // End of automatics
     end else begin
     end else begin
        rst <= #1 {rst[0], !sys_rst_i};
        rst <= #1 {rst[0], !sys_rst_i};
     end
     end
 
 
   // PHASE TOGGLE
   // PHASE TOGGLE
   always @(posedge sys_clk_i)
   always @(posedge sys_clk_i)
     if (sys_rst_i) begin
     if (sys_rst_i) begin
        /*AUTORESET*/
        /*AUTORESET*/
        // Beginning of autoreset for uninitialized flops
        // Beginning of autoreset for uninitialized flops
        gpha <= 1'h0;
        gpha <= 1'h0;
        // End of automatics
        // End of automatics
     end else if (dena | grst) begin
     end else if (dena | grst) begin
        gpha <= #1 !gpha;
        gpha <= #1 !gpha;
     end
     end
 
 
endmodule // aeMB2_pipe
endmodule // aeMB2_pipe
 
 
/*
 
 $Log: not supported by cvs2svn $
 
 Revision 1.3  2008/04/26 01:09:06  sybreon
 
 Passes basic tests. Minor documentation changes to make it compatible with iverilog pre-processor.
 
 
 
 Revision 1.2  2008/04/20 16:34:32  sybreon
 
 Basic version with some features left out.
 
 
 
 Revision 1.1  2008/04/18 00:21:52  sybreon
 
 Initial import.
 
*/
 
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