/* $Id: aeMB2_spsram.v,v 1.1 2008-04-20 16:33:39 sybreon Exp $
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/* $Id: aeMB2_spsram.v,v 1.1 2008-04-20 16:33:39 sybreon Exp $
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**
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**
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** AEMB2 EDK 6.2 COMPATIBLE CORE
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** AEMB2 EDK 6.2 COMPATIBLE CORE
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** Copyright (C) 2004-2008 Shawn Tan <shawn.tan@aeste.net>
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** Copyright (C) 2004-2008 Shawn Tan <shawn.tan@aeste.net>
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**
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**
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** This file is part of AEMB.
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** This file is part of AEMB.
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**
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**
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** AEMB is free software: you can redistribute it and/or modify it
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** AEMB is free software: you can redistribute it and/or modify it
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** under the terms of the GNU Lesser General Public License as
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** under the terms of the GNU Lesser General Public License as
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** published by the Free Software Foundation, either version 3 of the
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** published by the Free Software Foundation, either version 3 of the
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** License, or (at your option) any later version.
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** License, or (at your option) any later version.
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**
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**
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** AEMB is distributed in the hope that it will be useful, but WITHOUT
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** AEMB is distributed in the hope that it will be useful, but WITHOUT
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** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General
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** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General
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** Public License for more details.
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** Public License for more details.
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**
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**
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** You should have received a copy of the GNU Lesser General Public
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** You should have received a copy of the GNU Lesser General Public
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** License along with AEMB. If not, see <http:**www.gnu.org/licenses/>.
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** License along with AEMB. If not, see <http:**www.gnu.org/licenses/>.
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*/
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*/
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/**
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/**
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* @file aeMB2_spsram.v
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* @file aeMB2_spsram.v
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* @brief On-chip singla-port synchronous SRAM.
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* @brief On-chip singla-port synchronous SRAM.
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* Infer a write-before-read block RAM.
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* Infer a write-before-read block RAM.
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* NOTES: Quartus (<=7.2) does not infer a block RAM with read enable.
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* NOTES: Quartus (<=7.2) does not infer a block RAM with read enable.
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*/
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*/
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module aeMB2_spsram (/*AUTOARG*/
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module aeMB2_spsram (/*AUTOARG*/
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// Outputs
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// Outputs
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dat_o,
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dat_o,
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// Inputs
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// Inputs
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adr_i, dat_i, wre_i, ena_i, rst_i, clk_i
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adr_i, dat_i, wre_i, ena_i, rst_i, clk_i
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) ;
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) ;
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parameter AW = 8;
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parameter AW = 8;
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parameter DW = 32;
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parameter DW = 32;
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// PORT A - READ/WRITE
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// PORT A - READ/WRITE
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output [DW-1:0] dat_o;
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output [DW-1:0] dat_o;
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input [AW-1:0] adr_i;
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input [AW-1:0] adr_i;
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input [DW-1:0] dat_i;
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input [DW-1:0] dat_i;
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input wre_i,
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input wre_i,
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ena_i,
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ena_i,
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rst_i,
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rst_i,
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clk_i;
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clk_i;
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/*AUTOREG*/
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/*AUTOREG*/
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// Beginning of automatic regs (for this module's undeclared outputs)
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// Beginning of automatic regs (for this module's undeclared outputs)
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reg [DW-1:0] dat_o;
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reg [DW-1:0] dat_o;
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// End of automatics
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// End of automatics
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reg [DW:1] rRAM [(1<<AW)-1:0];
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reg [DW:1] rRAM [(1<<AW)-1:0];
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reg [AW:1] rADR;
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reg [AW:1] rADR;
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always @(posedge clk_i)
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always @(posedge clk_i)
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if (wre_i) rRAM[adr_i] <= #1 dat_i;
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if (wre_i) rRAM[adr_i] <= #1 dat_i;
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always @(posedge clk_i)
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always @(posedge clk_i)
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if (rst_i)
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if (rst_i)
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/*AUTORESET*/
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/*AUTORESET*/
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// Beginning of autoreset for uninitialized flops
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// Beginning of autoreset for uninitialized flops
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dat_o <= {(1+(DW-1)){1'b0}};
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dat_o <= {(1+(DW-1)){1'b0}};
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// End of automatics
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// End of automatics
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else if (ena_i)
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else if (ena_i)
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dat_o <= #1 rRAM[adr_i];
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dat_o <= #1 rRAM[adr_i];
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// --- SIMULATION ONLY ------------------------------------
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// --- SIMULATION ONLY ------------------------------------
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// synopsys translate_off
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// synopsys translate_off
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integer i;
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integer i;
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initial begin
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initial begin
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for (i=0; i<(1<<AW); i=i+1) begin
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for (i=0; i<(1<<AW); i=i+1) begin
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rRAM[i] <= $random;
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rRAM[i] <= $random;
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end
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end
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end
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end
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// synopsys translate_on
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// synopsys translate_on
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endmodule // aeMB2_spsram
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endmodule // aeMB2_spsram
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