// $Id: aeMB_ctrl.v,v 1.10 2007-11-30 16:44:40 sybreon Exp $
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// $Id: aeMB_ctrl.v,v 1.10 2007-11-30 16:44:40 sybreon Exp $
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//
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//
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// AEMB CONTROL UNIT
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// AEMB CONTROL UNIT
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//
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//
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// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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//
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//
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// This file is part of AEMB.
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// This file is part of AEMB.
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//
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//
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// AEMB is free software: you can redistribute it and/or modify it
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// AEMB is free software: you can redistribute it and/or modify it
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// under the terms of the GNU Lesser General Public License as
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// under the terms of the GNU Lesser General Public License as
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// published by the Free Software Foundation, either version 3 of the
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// published by the Free Software Foundation, either version 3 of the
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// License, or (at your option) any later version.
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// License, or (at your option) any later version.
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//
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//
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// AEMB is distributed in the hope that it will be useful, but WITHOUT
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// AEMB is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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// or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General
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// or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General
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// Public License for more details.
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// Public License for more details.
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//
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//
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// You should have received a copy of the GNU Lesser General Public
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// You should have received a copy of the GNU Lesser General Public
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// License along with AEMB. If not, see <http://www.gnu.org/licenses/>.
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// License along with AEMB. If not, see <http://www.gnu.org/licenses/>.
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.9 2007/11/15 09:26:43 sybreon
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// Revision 1.9 2007/11/15 09:26:43 sybreon
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// Fixed minor typo causing synthesis failure.
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// Fixed minor typo causing synthesis failure.
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//
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//
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// Revision 1.8 2007/11/14 23:19:24 sybreon
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// Revision 1.8 2007/11/14 23:19:24 sybreon
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// Fixed minor typo.
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// Fixed minor typo.
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//
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//
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// Revision 1.7 2007/11/14 22:14:34 sybreon
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// Revision 1.7 2007/11/14 22:14:34 sybreon
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// Changed interrupt handling system (reported by M. Ettus).
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// Changed interrupt handling system (reported by M. Ettus).
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//
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//
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// Revision 1.6 2007/11/10 16:39:38 sybreon
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// Revision 1.6 2007/11/10 16:39:38 sybreon
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// Upgraded license to LGPLv3.
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// Upgraded license to LGPLv3.
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// Significant performance optimisations.
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// Significant performance optimisations.
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//
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//
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// Revision 1.5 2007/11/09 20:51:52 sybreon
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// Revision 1.5 2007/11/09 20:51:52 sybreon
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// Added GET/PUT support through a FSL bus.
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// Added GET/PUT support through a FSL bus.
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//
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//
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// Revision 1.4 2007/11/08 17:48:14 sybreon
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// Revision 1.4 2007/11/08 17:48:14 sybreon
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// Fixed data WISHBONE arbitration problem (reported by J Lee).
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// Fixed data WISHBONE arbitration problem (reported by J Lee).
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//
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//
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// Revision 1.3 2007/11/08 14:17:47 sybreon
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// Revision 1.3 2007/11/08 14:17:47 sybreon
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// Parameterised optional components.
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// Parameterised optional components.
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//
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//
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// Revision 1.2 2007/11/02 19:20:58 sybreon
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// Revision 1.2 2007/11/02 19:20:58 sybreon
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// Added better (beta) interrupt support.
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// Added better (beta) interrupt support.
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// Changed MSR_IE to disabled at reset as per MB docs.
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// Changed MSR_IE to disabled at reset as per MB docs.
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//
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//
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// Revision 1.1 2007/11/02 03:25:40 sybreon
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// Revision 1.1 2007/11/02 03:25:40 sybreon
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// New EDK 3.2 compatible design with optional barrel-shifter and multiplier.
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// New EDK 3.2 compatible design with optional barrel-shifter and multiplier.
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// Fixed various minor data hazard bugs.
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// Fixed various minor data hazard bugs.
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// Code compatible with -O0/1/2/3/s generated code.
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// Code compatible with -O0/1/2/3/s generated code.
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//
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//
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module aeMB_ctrl (/*AUTOARG*/
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module aeMB_ctrl (/*AUTOARG*/
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// Outputs
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// Outputs
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rMXDST, rMXSRC, rMXTGT, rMXALT, rMXALU, rRW, dwb_stb_o, dwb_wre_o,
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rMXDST, rMXSRC, rMXTGT, rMXALT, rMXALU, rRW, dwb_stb_o, dwb_wre_o,
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fsl_stb_o, fsl_wre_o,
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fsl_stb_o, fsl_wre_o,
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// Inputs
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// Inputs
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rDLY, rIMM, rALT, rOPC, rRD, rRA, rRB, rPC, rBRA, rMSR_IE, xIREG,
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rDLY, rIMM, rALT, rOPC, rRD, rRA, rRB, rPC, rBRA, rMSR_IE, xIREG,
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dwb_ack_i, iwb_ack_i, fsl_ack_i, gclk, grst, gena
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dwb_ack_i, iwb_ack_i, fsl_ack_i, gclk, grst, gena
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);
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);
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// INTERNAL
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// INTERNAL
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//output [31:2] rPCLNK;
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//output [31:2] rPCLNK;
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output [1:0] rMXDST;
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output [1:0] rMXDST;
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output [1:0] rMXSRC, rMXTGT, rMXALT;
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output [1:0] rMXSRC, rMXTGT, rMXALT;
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output [2:0] rMXALU;
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output [2:0] rMXALU;
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output [4:0] rRW;
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output [4:0] rRW;
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input rDLY;
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input rDLY;
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input [15:0] rIMM;
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input [15:0] rIMM;
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input [10:0] rALT;
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input [10:0] rALT;
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input [5:0] rOPC;
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input [5:0] rOPC;
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input [4:0] rRD, rRA, rRB;
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input [4:0] rRD, rRA, rRB;
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input [31:2] rPC;
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input [31:2] rPC;
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input rBRA;
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input rBRA;
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input rMSR_IE;
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input rMSR_IE;
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input [31:0] xIREG;
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input [31:0] xIREG;
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// DATA WISHBONE
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// DATA WISHBONE
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output dwb_stb_o;
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output dwb_stb_o;
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output dwb_wre_o;
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output dwb_wre_o;
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input dwb_ack_i;
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input dwb_ack_i;
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// INST WISHBONE
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// INST WISHBONE
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input iwb_ack_i;
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input iwb_ack_i;
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// FSL WISHBONE
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// FSL WISHBONE
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output fsl_stb_o;
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output fsl_stb_o;
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output fsl_wre_o;
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output fsl_wre_o;
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input fsl_ack_i;
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input fsl_ack_i;
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// SYSTEM
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// SYSTEM
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input gclk, grst, gena;
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input gclk, grst, gena;
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// --- DECODE INSTRUCTIONS
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// --- DECODE INSTRUCTIONS
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// TODO: Simplify
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// TODO: Simplify
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wire [5:0] wOPC;
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wire [5:0] wOPC;
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wire [4:0] wRD, wRA, wRB;
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wire [4:0] wRD, wRA, wRB;
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wire [10:0] wALT;
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wire [10:0] wALT;
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assign {wOPC, wRD, wRA, wRB, wALT} = xIREG; // FIXME: Endian
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assign {wOPC, wRD, wRA, wRB, wALT} = xIREG; // FIXME: Endian
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wire fSFT = (rOPC == 6'o44);
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wire fSFT = (rOPC == 6'o44);
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wire fLOG = ({rOPC[5:4],rOPC[2]} == 3'o4);
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wire fLOG = ({rOPC[5:4],rOPC[2]} == 3'o4);
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wire fMUL = (rOPC == 6'o20) | (rOPC == 6'o30);
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wire fMUL = (rOPC == 6'o20) | (rOPC == 6'o30);
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wire fBSF = (rOPC == 6'o21) | (rOPC == 6'o31);
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wire fBSF = (rOPC == 6'o21) | (rOPC == 6'o31);
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wire fDIV = (rOPC == 6'o22);
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wire fDIV = (rOPC == 6'o22);
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wire fRTD = (rOPC == 6'o55);
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wire fRTD = (rOPC == 6'o55);
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wire fBCC = (rOPC == 6'o47) | (rOPC == 6'o57);
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wire fBCC = (rOPC == 6'o47) | (rOPC == 6'o57);
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wire fBRU = (rOPC == 6'o46) | (rOPC == 6'o56);
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wire fBRU = (rOPC == 6'o46) | (rOPC == 6'o56);
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wire fBRA = fBRU & rRA[3];
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wire fBRA = fBRU & rRA[3];
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wire fIMM = (rOPC == 6'o54);
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wire fIMM = (rOPC == 6'o54);
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wire fMOV = (rOPC == 6'o45);
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wire fMOV = (rOPC == 6'o45);
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wire fLOD = ({rOPC[5:4],rOPC[2]} == 3'o6);
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wire fLOD = ({rOPC[5:4],rOPC[2]} == 3'o6);
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wire fSTR = ({rOPC[5:4],rOPC[2]} == 3'o7);
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wire fSTR = ({rOPC[5:4],rOPC[2]} == 3'o7);
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wire fLDST = (&rOPC[5:4]);
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wire fLDST = (&rOPC[5:4]);
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wire fPUT = (rOPC == 6'o33) & rRB[4];
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wire fPUT = (rOPC == 6'o33) & rRB[4];
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wire fGET = (rOPC == 6'o33) & !rRB[4];
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wire fGET = (rOPC == 6'o33) & !rRB[4];
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wire wSFT = (wOPC == 6'o44);
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wire wSFT = (wOPC == 6'o44);
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wire wLOG = ({wOPC[5:4],wOPC[2]} == 3'o4);
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wire wLOG = ({wOPC[5:4],wOPC[2]} == 3'o4);
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wire wMUL = (wOPC == 6'o20) | (wOPC == 6'o30);
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wire wMUL = (wOPC == 6'o20) | (wOPC == 6'o30);
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wire wBSF = (wOPC == 6'o21) | (wOPC == 6'o31);
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wire wBSF = (wOPC == 6'o21) | (wOPC == 6'o31);
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wire wDIV = (wOPC == 6'o22);
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wire wDIV = (wOPC == 6'o22);
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wire wRTD = (wOPC == 6'o55);
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wire wRTD = (wOPC == 6'o55);
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wire wBCC = (wOPC == 6'o47) | (wOPC == 6'o57);
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wire wBCC = (wOPC == 6'o47) | (wOPC == 6'o57);
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wire wBRU = (wOPC == 6'o46) | (wOPC == 6'o56);
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wire wBRU = (wOPC == 6'o46) | (wOPC == 6'o56);
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wire wBRA = wBRU & wRA[3];
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wire wBRA = wBRU & wRA[3];
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wire wIMM = (wOPC == 6'o54);
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wire wIMM = (wOPC == 6'o54);
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wire wMOV = (wOPC == 6'o45);
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wire wMOV = (wOPC == 6'o45);
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wire wLOD = ({wOPC[5:4],wOPC[2]} == 3'o6);
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wire wLOD = ({wOPC[5:4],wOPC[2]} == 3'o6);
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wire wSTR = ({wOPC[5:4],wOPC[2]} == 3'o7);
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wire wSTR = ({wOPC[5:4],wOPC[2]} == 3'o7);
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wire wLDST = (&wOPC[5:4]);
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wire wLDST = (&wOPC[5:4]);
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wire wPUT = (wOPC == 6'o33) & wRB[4];
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wire wPUT = (wOPC == 6'o33) & wRB[4];
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wire wGET = (wOPC == 6'o33) & !wRB[4];
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wire wGET = (wOPC == 6'o33) & !wRB[4];
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// --- BRANCH SLOT REGISTERS ---------------------------
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// --- BRANCH SLOT REGISTERS ---------------------------
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reg [31:2] rPCLNK, xPCLNK;
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reg [31:2] rPCLNK, xPCLNK;
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reg [1:0] rMXDST, xMXDST;
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reg [1:0] rMXDST, xMXDST;
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reg [4:0] rRW, xRW;
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reg [4:0] rRW, xRW;
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reg [1:0] rMXSRC, xMXSRC;
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reg [1:0] rMXSRC, xMXSRC;
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reg [1:0] rMXTGT, xMXTGT;
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reg [1:0] rMXTGT, xMXTGT;
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reg [1:0] rMXALT, xMXALT;
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reg [1:0] rMXALT, xMXALT;
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// --- OPERAND SELECTOR ---------------------------------
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// --- OPERAND SELECTOR ---------------------------------
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wire wRDWE = |xRW;
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wire wRDWE = |xRW;
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wire wAFWD_M = (xRW == wRA) & (xMXDST == 2'o2) & wRDWE;
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wire wAFWD_M = (xRW == wRA) & (xMXDST == 2'o2) & wRDWE;
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wire wBFWD_M = (xRW == wRB) & (xMXDST == 2'o2) & wRDWE;
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wire wBFWD_M = (xRW == wRB) & (xMXDST == 2'o2) & wRDWE;
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wire wAFWD_R = (xRW == wRA) & (xMXDST == 2'o0) & wRDWE;
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wire wAFWD_R = (xRW == wRA) & (xMXDST == 2'o0) & wRDWE;
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wire wBFWD_R = (xRW == wRB) & (xMXDST == 2'o0) & wRDWE;
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wire wBFWD_R = (xRW == wRB) & (xMXDST == 2'o0) & wRDWE;
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always @(/*AUTOSENSE*/rBRA or wAFWD_M or wAFWD_R or wBCC or wBFWD_M
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always @(/*AUTOSENSE*/rBRA or wAFWD_M or wAFWD_R or wBCC or wBFWD_M
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or wBFWD_R or wBRU or wOPC)
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or wBFWD_R or wBRU or wOPC)
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//if (rBRA | |rXCE) begin
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//if (rBRA | |rXCE) begin
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if (rBRA) begin
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if (rBRA) begin
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/*AUTORESET*/
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/*AUTORESET*/
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// Beginning of autoreset for uninitialized flops
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// Beginning of autoreset for uninitialized flops
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xMXALT <= 2'h0;
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xMXALT <= 2'h0;
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xMXSRC <= 2'h0;
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xMXSRC <= 2'h0;
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xMXTGT <= 2'h0;
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xMXTGT <= 2'h0;
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// End of automatics
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// End of automatics
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end else begin
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end else begin
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xMXSRC <= (wBRU | wBCC) ? 2'o3 : // PC
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xMXSRC <= (wBRU | wBCC) ? 2'o3 : // PC
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(wAFWD_M) ? 2'o2 : // RAM
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(wAFWD_M) ? 2'o2 : // RAM
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(wAFWD_R) ? 2'o1 : // FWD
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(wAFWD_R) ? 2'o1 : // FWD
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2'o0; // REG
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2'o0; // REG
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xMXTGT <= (wOPC[3]) ? 2'o3 : // IMM
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xMXTGT <= (wOPC[3]) ? 2'o3 : // IMM
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(wBFWD_M) ? 2'o2 : // RAM
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(wBFWD_M) ? 2'o2 : // RAM
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(wBFWD_R) ? 2'o1 : // FWD
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(wBFWD_R) ? 2'o1 : // FWD
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2'o0; // REG
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2'o0; // REG
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xMXALT <= (wAFWD_M) ? 2'o2 : // RAM
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xMXALT <= (wAFWD_M) ? 2'o2 : // RAM
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(wAFWD_R) ? 2'o1 : // FWD
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(wAFWD_R) ? 2'o1 : // FWD
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2'o0; // REG
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2'o0; // REG
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end // else: !if(rBRA)
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end // else: !if(rBRA)
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// --- ALU CONTROL ---------------------------------------
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// --- ALU CONTROL ---------------------------------------
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reg [2:0] rMXALU, xMXALU;
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reg [2:0] rMXALU, xMXALU;
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always @(/*AUTOSENSE*/rBRA or wBRA or wBSF or wDIV or wLOG or wMOV
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always @(/*AUTOSENSE*/rBRA or wBRA or wBSF or wDIV or wLOG or wMOV
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or wMUL or wSFT)
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or wMUL or wSFT)
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//if (rBRA | |rXCE) begin
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//if (rBRA | |rXCE) begin
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if (rBRA) begin
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if (rBRA) begin
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/*AUTORESET*/
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/*AUTORESET*/
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// Beginning of autoreset for uninitialized flops
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// Beginning of autoreset for uninitialized flops
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xMXALU <= 3'h0;
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xMXALU <= 3'h0;
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// End of automatics
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// End of automatics
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end else begin
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end else begin
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xMXALU <= (wBRA | wMOV) ? 3'o3 :
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xMXALU <= (wBRA | wMOV) ? 3'o3 :
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(wSFT) ? 3'o2 :
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(wSFT) ? 3'o2 :
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(wLOG) ? 3'o1 :
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(wLOG) ? 3'o1 :
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(wMUL) ? 3'o4 :
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(wMUL) ? 3'o4 :
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(wBSF) ? 3'o5 :
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(wBSF) ? 3'o5 :
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(wDIV) ? 3'o6 :
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(wDIV) ? 3'o6 :
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3'o0;
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3'o0;
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end // else: !if(rBRA)
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end // else: !if(rBRA)
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// --- DELAY SLOT REGISTERS ------------------------------
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// --- DELAY SLOT REGISTERS ------------------------------
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wire fSKIP = (rBRA & !rDLY);
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wire fSKIP = (rBRA & !rDLY);
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always @(/*AUTOSENSE*/fBCC or fBRU or fGET or fLOD or fRTD or fSKIP
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always @(/*AUTOSENSE*/fBCC or fBRU or fGET or fLOD or fRTD or fSKIP
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or fSTR or rRD)
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or fSTR or rRD)
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if (fSKIP) begin
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if (fSKIP) begin
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/*AUTORESET*/
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/*AUTORESET*/
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// Beginning of autoreset for uninitialized flops
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// Beginning of autoreset for uninitialized flops
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xMXDST <= 2'h0;
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xMXDST <= 2'h0;
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xRW <= 5'h0;
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xRW <= 5'h0;
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// End of automatics
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// End of automatics
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end else begin
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end else begin
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xMXDST <= (fSTR | fRTD | fBCC) ? 2'o3 :
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xMXDST <= (fSTR | fRTD | fBCC) ? 2'o3 :
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(fLOD | fGET) ? 2'o2 :
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(fLOD | fGET) ? 2'o2 :
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(fBRU) ? 2'o1 :
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(fBRU) ? 2'o1 :
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2'o0;
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2'o0;
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xRW <= rRD;
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xRW <= rRD;
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end // else: !if(fSKIP)
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end // else: !if(fSKIP)
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// --- DATA WISHBONE ----------------------------------
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// --- DATA WISHBONE ----------------------------------
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wire fDACK = !(dwb_stb_o ^ dwb_ack_i);
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wire fDACK = !(dwb_stb_o ^ dwb_ack_i);
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reg rDWBSTB, xDWBSTB;
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reg rDWBSTB, xDWBSTB;
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reg rDWBWRE, xDWBWRE;
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reg rDWBWRE, xDWBWRE;
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assign dwb_stb_o = rDWBSTB;
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assign dwb_stb_o = rDWBSTB;
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assign dwb_wre_o = rDWBWRE;
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assign dwb_wre_o = rDWBWRE;
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always @(/*AUTOSENSE*/fLOD or fSKIP or fSTR or iwb_ack_i)
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always @(/*AUTOSENSE*/fLOD or fSKIP or fSTR or iwb_ack_i)
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//if (fSKIP | |rXCE) begin
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//if (fSKIP | |rXCE) begin
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if (fSKIP) begin
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if (fSKIP) begin
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/*AUTORESET*/
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/*AUTORESET*/
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// Beginning of autoreset for uninitialized flops
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// Beginning of autoreset for uninitialized flops
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xDWBSTB <= 1'h0;
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xDWBSTB <= 1'h0;
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xDWBWRE <= 1'h0;
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xDWBWRE <= 1'h0;
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// End of automatics
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// End of automatics
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end else begin
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end else begin
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xDWBSTB <= (fLOD | fSTR) & iwb_ack_i;
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xDWBSTB <= (fLOD | fSTR) & iwb_ack_i;
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xDWBWRE <= fSTR & iwb_ack_i;
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xDWBWRE <= fSTR & iwb_ack_i;
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end
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end
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always @(posedge gclk)
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always @(posedge gclk)
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if (grst) begin
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if (grst) begin
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/*AUTORESET*/
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/*AUTORESET*/
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// Beginning of autoreset for uninitialized flops
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// Beginning of autoreset for uninitialized flops
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rDWBSTB <= 1'h0;
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rDWBSTB <= 1'h0;
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rDWBWRE <= 1'h0;
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rDWBWRE <= 1'h0;
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// End of automatics
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// End of automatics
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end else if (fDACK) begin
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end else if (fDACK) begin
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rDWBSTB <= #1 xDWBSTB;
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rDWBSTB <= #1 xDWBSTB;
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rDWBWRE <= #1 xDWBWRE;
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rDWBWRE <= #1 xDWBWRE;
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end
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end
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// --- FSL WISHBONE -----------------------------------
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// --- FSL WISHBONE -----------------------------------
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|
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wire fFACK = !(fsl_stb_o ^ fsl_ack_i);
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wire fFACK = !(fsl_stb_o ^ fsl_ack_i);
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reg rFSLSTB, xFSLSTB;
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reg rFSLSTB, xFSLSTB;
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reg rFSLWRE, xFSLWRE;
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reg rFSLWRE, xFSLWRE;
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|
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assign fsl_stb_o = rFSLSTB;
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assign fsl_stb_o = rFSLSTB;
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assign fsl_wre_o = rFSLWRE;
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assign fsl_wre_o = rFSLWRE;
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always @(/*AUTOSENSE*/fGET or fPUT or fSKIP or iwb_ack_i)
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always @(/*AUTOSENSE*/fGET or fPUT or fSKIP or iwb_ack_i)
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//if (fSKIP | |rXCE) begin
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//if (fSKIP | |rXCE) begin
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if (fSKIP) begin
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if (fSKIP) begin
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/*AUTORESET*/
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/*AUTORESET*/
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// Beginning of autoreset for uninitialized flops
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// Beginning of autoreset for uninitialized flops
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xFSLSTB <= 1'h0;
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xFSLSTB <= 1'h0;
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xFSLWRE <= 1'h0;
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xFSLWRE <= 1'h0;
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// End of automatics
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// End of automatics
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end else begin
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end else begin
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xFSLSTB <= (fPUT | fGET) & iwb_ack_i;
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xFSLSTB <= (fPUT | fGET) & iwb_ack_i;
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xFSLWRE <= fPUT & iwb_ack_i;
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xFSLWRE <= fPUT & iwb_ack_i;
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end
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end
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|
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always @(posedge gclk)
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always @(posedge gclk)
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if (grst) begin
|
if (grst) begin
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/*AUTORESET*/
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/*AUTORESET*/
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// Beginning of autoreset for uninitialized flops
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// Beginning of autoreset for uninitialized flops
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rFSLSTB <= 1'h0;
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rFSLSTB <= 1'h0;
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rFSLWRE <= 1'h0;
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rFSLWRE <= 1'h0;
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// End of automatics
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// End of automatics
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end else if (fFACK) begin
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end else if (fFACK) begin
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rFSLSTB <= #1 xFSLSTB;
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rFSLSTB <= #1 xFSLSTB;
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rFSLWRE <= #1 xFSLWRE;
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rFSLWRE <= #1 xFSLWRE;
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end
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end
|
|
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// --- PIPELINE CONTROL DELAY ----------------------------
|
// --- PIPELINE CONTROL DELAY ----------------------------
|
|
|
always @(posedge gclk)
|
always @(posedge gclk)
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if (grst) begin
|
if (grst) begin
|
/*AUTORESET*/
|
/*AUTORESET*/
|
// Beginning of autoreset for uninitialized flops
|
// Beginning of autoreset for uninitialized flops
|
rMXALT <= 2'h0;
|
rMXALT <= 2'h0;
|
rMXALU <= 3'h0;
|
rMXALU <= 3'h0;
|
rMXDST <= 2'h0;
|
rMXDST <= 2'h0;
|
rMXSRC <= 2'h0;
|
rMXSRC <= 2'h0;
|
rMXTGT <= 2'h0;
|
rMXTGT <= 2'h0;
|
rRW <= 5'h0;
|
rRW <= 5'h0;
|
// End of automatics
|
// End of automatics
|
end else if (gena) begin // if (grst)
|
end else if (gena) begin // if (grst)
|
//rPCLNK <= #1 xPCLNK;
|
//rPCLNK <= #1 xPCLNK;
|
rMXDST <= #1 xMXDST;
|
rMXDST <= #1 xMXDST;
|
rRW <= #1 xRW;
|
rRW <= #1 xRW;
|
rMXSRC <= #1 xMXSRC;
|
rMXSRC <= #1 xMXSRC;
|
rMXTGT <= #1 xMXTGT;
|
rMXTGT <= #1 xMXTGT;
|
rMXALT <= #1 xMXALT;
|
rMXALT <= #1 xMXALT;
|
rMXALU <= #1 xMXALU;
|
rMXALU <= #1 xMXALU;
|
end
|
end
|
|
|
|
|
endmodule // aeMB_ctrl
|
endmodule // aeMB_ctrl
|
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|
