/* $Id: aeMB_ibuf.v,v 1.10 2008-01-21 01:02:26 sybreon Exp $
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/* $Id: aeMB_ibuf.v,v 1.10 2008-01-21 01:02:26 sybreon Exp $
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**
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**
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** AEMB INSTRUCTION BUFFER
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** AEMB INSTRUCTION BUFFER
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** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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**
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**
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** This file is part of AEMB.
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** This file is part of AEMB.
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**
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**
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** AEMB is free software: you can redistribute it and/or modify it
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** AEMB is free software: you can redistribute it and/or modify it
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** under the terms of the GNU Lesser General Public License as
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** under the terms of the GNU Lesser General Public License as
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** published by the Free Software Foundation, either version 3 of the
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** published by the Free Software Foundation, either version 3 of the
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** License, or (at your option) any later version.
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** License, or (at your option) any later version.
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**
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**
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** AEMB is distributed in the hope that it will be useful, but WITHOUT
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** AEMB is distributed in the hope that it will be useful, but WITHOUT
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** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General
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** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General
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** Public License for more details.
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** Public License for more details.
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**
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**
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** You should have received a copy of the GNU Lesser General Public
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** You should have received a copy of the GNU Lesser General Public
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** License along with AEMB. If not, see <http://www.gnu.org/licenses/>.
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** License along with AEMB. If not, see <http://www.gnu.org/licenses/>.
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*/
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*/
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module aeMB_ibuf (/*AUTOARG*/
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module aeMB_ibuf (/*AUTOARG*/
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// Outputs
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// Outputs
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rIMM, rRA, rRD, rRB, rALT, rOPC, rSIMM, xIREG, rSTALL, iwb_stb_o,
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rIMM, rRA, rRD, rRB, rALT, rOPC, rSIMM, xIREG, rSTALL, iwb_stb_o,
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// Inputs
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// Inputs
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rBRA, rMSR_IE, rMSR_BIP, iwb_dat_i, iwb_ack_i, sys_int_i, gclk,
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rBRA, rMSR_IE, rMSR_BIP, iwb_dat_i, iwb_ack_i, sys_int_i, gclk,
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grst, gena, oena
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grst, gena, oena
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);
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);
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// INTERNAL
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// INTERNAL
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output [15:0] rIMM;
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output [15:0] rIMM;
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output [4:0] rRA, rRD, rRB;
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output [4:0] rRA, rRD, rRB;
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output [10:0] rALT;
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output [10:0] rALT;
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output [5:0] rOPC;
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output [5:0] rOPC;
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output [31:0] rSIMM;
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output [31:0] rSIMM;
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output [31:0] xIREG;
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output [31:0] xIREG;
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output rSTALL;
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output rSTALL;
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input rBRA;
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input rBRA;
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//input [1:0] rXCE;
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//input [1:0] rXCE;
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input rMSR_IE;
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input rMSR_IE;
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input rMSR_BIP;
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input rMSR_BIP;
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// INST WISHBONE
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// INST WISHBONE
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output iwb_stb_o;
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output iwb_stb_o;
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input [31:0] iwb_dat_i;
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input [31:0] iwb_dat_i;
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input iwb_ack_i;
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input iwb_ack_i;
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// SYSTEM
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// SYSTEM
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input sys_int_i;
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input sys_int_i;
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// SYSTEM
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// SYSTEM
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input gclk, grst, gena, oena;
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input gclk, grst, gena, oena;
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reg [15:0] rIMM;
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reg [15:0] rIMM;
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reg [4:0] rRA, rRD;
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reg [4:0] rRA, rRD;
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reg [5:0] rOPC;
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reg [5:0] rOPC;
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// FIXME: Endian
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// FIXME: Endian
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wire [31:0] wIDAT = iwb_dat_i;
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wire [31:0] wIDAT = iwb_dat_i;
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assign {rRB, rALT} = rIMM;
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assign {rRB, rALT} = rIMM;
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// TODO: Assign to FIFO not full.
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// TODO: Assign to FIFO not full.
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assign iwb_stb_o = 1'b1;
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assign iwb_stb_o = 1'b1;
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reg [31:0] rSIMM, xSIMM;
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reg [31:0] rSIMM, xSIMM;
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reg rSTALL;
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reg rSTALL;
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wire [31:0] wXCEOP = 32'hBA2D0008; // Vector 0x08
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wire [31:0] wXCEOP = 32'hBA2D0008; // Vector 0x08
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wire [31:0] wINTOP = 32'hB9CE0010; // Vector 0x10
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wire [31:0] wINTOP = 32'hB9CE0010; // Vector 0x10
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wire [31:0] wBRKOP = 32'hBA0C0018; // Vector 0x18
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wire [31:0] wBRKOP = 32'hBA0C0018; // Vector 0x18
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wire [31:0] wBRAOP = 32'h88000000; // NOP for branches
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wire [31:0] wBRAOP = 32'h88000000; // NOP for branches
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wire [31:0] wIREG = {rOPC, rRD, rRA, rRB, rALT};
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wire [31:0] wIREG = {rOPC, rRD, rRA, rRB, rALT};
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reg [31:0] xIREG;
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reg [31:0] xIREG;
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// --- INTERRUPT LATCH --------------------------------------
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// --- INTERRUPT LATCH --------------------------------------
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// Debounce and latch onto the positive level. This is independent
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// Debounce and latch onto the positive level. This is independent
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// of the pipeline so that stalls do not affect it.
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// of the pipeline so that stalls do not affect it.
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reg rFINT;
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reg rFINT;
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reg [1:0] rDINT;
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reg [1:0] rDINT;
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wire wSHOT = rDINT[0];
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wire wSHOT = rDINT[0];
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always @(posedge gclk)
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always @(posedge gclk)
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if (grst) begin
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if (grst) begin
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/*AUTORESET*/
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/*AUTORESET*/
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// Beginning of autoreset for uninitialized flops
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// Beginning of autoreset for uninitialized flops
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rDINT <= 2'h0;
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rDINT <= 2'h0;
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rFINT <= 1'h0;
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rFINT <= 1'h0;
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// End of automatics
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// End of automatics
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end else begin
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end else begin
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if (rMSR_IE)
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if (rMSR_IE)
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rDINT <= #1
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rDINT <= #1
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{rDINT[0], sys_int_i};
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{rDINT[0], sys_int_i};
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rFINT <= #1
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rFINT <= #1
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//(wIREG == wINTOP) ? 1'b0 :
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//(wIREG == wINTOP) ? 1'b0 :
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(rFINT | wSHOT) & rMSR_IE;
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(rFINT | wSHOT) & rMSR_IE;
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end
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end
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wire fIMM = (rOPC == 6'o54);
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wire fIMM = (rOPC == 6'o54);
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wire fRTD = (rOPC == 6'o55);
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wire fRTD = (rOPC == 6'o55);
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wire fBRU = ((rOPC == 6'o46) | (rOPC == 6'o56));
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wire fBRU = ((rOPC == 6'o46) | (rOPC == 6'o56));
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wire fBCC = ((rOPC == 6'o47) | (rOPC == 6'o57));
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wire fBCC = ((rOPC == 6'o47) | (rOPC == 6'o57));
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// --- DELAY SLOT -------------------------------------------
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// --- DELAY SLOT -------------------------------------------
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always @(/*AUTOSENSE*/fBCC or fBRU or fIMM or fRTD or rBRA or rFINT
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always @(/*AUTOSENSE*/fBCC or fBRU or fIMM or fRTD or rBRA or rFINT
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or wBRAOP or wIDAT or wINTOP) begin
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or wBRAOP or wIDAT or wINTOP) begin
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xIREG <= (rBRA) ? wBRAOP :
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xIREG <= (rBRA) ? wBRAOP :
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(!fIMM & rFINT & !fRTD & !fBRU & !fBCC) ? wINTOP :
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(!fIMM & rFINT & !fRTD & !fBRU & !fBCC) ? wINTOP :
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wIDAT;
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wIDAT;
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end
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end
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always @(/*AUTOSENSE*/fIMM or rBRA or rIMM or wIDAT or xIREG) begin
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always @(/*AUTOSENSE*/fIMM or rBRA or rIMM or wIDAT or xIREG) begin
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xSIMM <= (!fIMM | rBRA) ? { {(16){xIREG[15]}}, xIREG[15:0]} :
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xSIMM <= (!fIMM | rBRA) ? { {(16){xIREG[15]}}, xIREG[15:0]} :
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{rIMM, wIDAT[15:0]};
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{rIMM, wIDAT[15:0]};
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end
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end
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// --- PIPELINE --------------------------------------------
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// --- PIPELINE --------------------------------------------
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always @(posedge gclk)
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always @(posedge gclk)
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if (grst) begin
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if (grst) begin
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/*AUTORESET*/
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/*AUTORESET*/
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// Beginning of autoreset for uninitialized flops
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// Beginning of autoreset for uninitialized flops
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rIMM <= 16'h0;
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rIMM <= 16'h0;
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rOPC <= 6'h0;
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rOPC <= 6'h0;
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rRA <= 5'h0;
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rRA <= 5'h0;
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rRD <= 5'h0;
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rRD <= 5'h0;
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rSIMM <= 32'h0;
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rSIMM <= 32'h0;
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// End of automatics
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// End of automatics
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end else if (gena) begin
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end else if (gena) begin
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{rOPC, rRD, rRA, rIMM} <= #1 xIREG;
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{rOPC, rRD, rRA, rIMM} <= #1 xIREG;
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rSIMM <= #1 xSIMM;
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rSIMM <= #1 xSIMM;
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end
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end
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// --- STALL FOR MUL/BSF -----------------------------------
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// --- STALL FOR MUL/BSF -----------------------------------
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wire [5:0] wOPC = xIREG[31:26];
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wire [5:0] wOPC = xIREG[31:26];
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wire fMUL = (wOPC == 6'o20) | (wOPC == 6'o30);
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wire fMUL = (wOPC == 6'o20) | (wOPC == 6'o30);
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wire fBSF = (wOPC == 6'o21) | (wOPC == 6'o31);
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wire fBSF = (wOPC == 6'o21) | (wOPC == 6'o31);
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always @(posedge gclk)
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always @(posedge gclk)
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if (grst) begin
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if (grst) begin
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/*AUTORESET*/
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/*AUTORESET*/
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// Beginning of autoreset for uninitialized flops
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// Beginning of autoreset for uninitialized flops
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rSTALL <= 1'h0;
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rSTALL <= 1'h0;
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// End of automatics
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// End of automatics
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end else begin
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end else begin
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rSTALL <= #1 (!rSTALL & (fMUL | fBSF)) | (oena & rSTALL);
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rSTALL <= #1 (!rSTALL & (fMUL | fBSF)) | (oena & rSTALL);
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end
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end
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endmodule // aeMB_ibuf
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endmodule // aeMB_ibuf
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/*
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/*
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$Log: not supported by cvs2svn $
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$Log: not supported by cvs2svn $
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Revision 1.9 2008/01/19 16:01:22 sybreon
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Revision 1.9 2008/01/19 16:01:22 sybreon
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Patched problem where memory access followed by dual cycle instructions were not stalling correctly (submitted by M. Ettus)
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Patched problem where memory access followed by dual cycle instructions were not stalling correctly (submitted by M. Ettus)
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Revision 1.8 2007/12/25 22:15:09 sybreon
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Revision 1.8 2007/12/25 22:15:09 sybreon
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Stalls pipeline on MUL/BSF instructions results in minor speed improvements.
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Stalls pipeline on MUL/BSF instructions results in minor speed improvements.
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Revision 1.7 2007/11/22 15:11:15 sybreon
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Revision 1.7 2007/11/22 15:11:15 sybreon
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Change interrupt to positive level triggered interrupts.
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Change interrupt to positive level triggered interrupts.
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Revision 1.6 2007/11/14 23:39:51 sybreon
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Revision 1.6 2007/11/14 23:39:51 sybreon
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Fixed interrupt signal synchronisation.
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Fixed interrupt signal synchronisation.
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Revision 1.5 2007/11/14 22:14:34 sybreon
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Revision 1.5 2007/11/14 22:14:34 sybreon
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Changed interrupt handling system (reported by M. Ettus).
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Changed interrupt handling system (reported by M. Ettus).
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Revision 1.4 2007/11/10 16:39:38 sybreon
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Revision 1.4 2007/11/10 16:39:38 sybreon
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Upgraded license to LGPLv3.
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Upgraded license to LGPLv3.
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Significant performance optimisations.
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Significant performance optimisations.
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Revision 1.3 2007/11/03 08:34:55 sybreon
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Revision 1.3 2007/11/03 08:34:55 sybreon
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Minor code cleanup.
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Minor code cleanup.
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Revision 1.2 2007/11/02 19:20:58 sybreon
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Revision 1.2 2007/11/02 19:20:58 sybreon
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Added better (beta) interrupt support.
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Added better (beta) interrupt support.
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Changed MSR_IE to disabled at reset as per MB docs.
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Changed MSR_IE to disabled at reset as per MB docs.
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Revision 1.1 2007/11/02 03:25:40 sybreon
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Revision 1.1 2007/11/02 03:25:40 sybreon
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New EDK 3.2 compatible design with optional barrel-shifter and multiplier.
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New EDK 3.2 compatible design with optional barrel-shifter and multiplier.
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Fixed various minor data hazard bugs.
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Fixed various minor data hazard bugs.
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Code compatible with -O0/1/2/3/s generated code.
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Code compatible with -O0/1/2/3/s generated code.
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