// $Id: aeMB_regf.v,v 1.3 2007-11-10 16:39:38 sybreon Exp $
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// $Id: aeMB_regf.v,v 1.3 2007-11-10 16:39:38 sybreon Exp $
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//
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//
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// AEMB REGISTER FILE
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// AEMB REGISTER FILE
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//
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//
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// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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//
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//
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// This file is part of AEMB.
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// This file is part of AEMB.
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//
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//
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// AEMB is free software: you can redistribute it and/or modify it
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// AEMB is free software: you can redistribute it and/or modify it
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// under the terms of the GNU Lesser General Public License as
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// under the terms of the GNU Lesser General Public License as
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// published by the Free Software Foundation, either version 3 of the
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// published by the Free Software Foundation, either version 3 of the
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// License, or (at your option) any later version.
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// License, or (at your option) any later version.
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//
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//
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// AEMB is distributed in the hope that it will be useful, but WITHOUT
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// AEMB is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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// or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General
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// or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General
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// Public License for more details.
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// Public License for more details.
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//
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//
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// You should have received a copy of the GNU Lesser General Public
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// You should have received a copy of the GNU Lesser General Public
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// License along with AEMB. If not, see <http://www.gnu.org/licenses/>.
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// License along with AEMB. If not, see <http://www.gnu.org/licenses/>.
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.2 2007/11/09 20:51:52 sybreon
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// Revision 1.2 2007/11/09 20:51:52 sybreon
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// Added GET/PUT support through a FSL bus.
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// Added GET/PUT support through a FSL bus.
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//
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//
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// Revision 1.1 2007/11/02 03:25:41 sybreon
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// Revision 1.1 2007/11/02 03:25:41 sybreon
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// New EDK 3.2 compatible design with optional barrel-shifter and multiplier.
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// New EDK 3.2 compatible design with optional barrel-shifter and multiplier.
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// Fixed various minor data hazard bugs.
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// Fixed various minor data hazard bugs.
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// Code compatible with -O0/1/2/3/s generated code.
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// Code compatible with -O0/1/2/3/s generated code.
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//
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//
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module aeMB_regf (/*AUTOARG*/
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module aeMB_regf (/*AUTOARG*/
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// Outputs
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// Outputs
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rREGA, rREGB, rDWBDI, dwb_dat_o, fsl_dat_o,
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rREGA, rREGB, rDWBDI, dwb_dat_o, fsl_dat_o,
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// Inputs
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// Inputs
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rOPC, rRA, rRB, rRW, rRD, rMXDST, rPCLNK, rRESULT, rDWBSEL, rBRA,
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rOPC, rRA, rRB, rRW, rRD, rMXDST, rPCLNK, rRESULT, rDWBSEL, rBRA,
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rDLY, dwb_dat_i, fsl_dat_i, gclk, grst, gena
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rDLY, dwb_dat_i, fsl_dat_i, gclk, grst, gena
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);
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);
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// INTERNAL
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// INTERNAL
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output [31:0] rREGA, rREGB;
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output [31:0] rREGA, rREGB;
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output [31:0] rDWBDI;
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output [31:0] rDWBDI;
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input [5:0] rOPC;
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input [5:0] rOPC;
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input [4:0] rRA, rRB, rRW, rRD;
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input [4:0] rRA, rRB, rRW, rRD;
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input [1:0] rMXDST;
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input [1:0] rMXDST;
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input [31:2] rPCLNK;
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input [31:2] rPCLNK;
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input [31:0] rRESULT;
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input [31:0] rRESULT;
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input [3:0] rDWBSEL;
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input [3:0] rDWBSEL;
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input rBRA, rDLY;
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input rBRA, rDLY;
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// DATA WISHBONE
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// DATA WISHBONE
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output [31:0] dwb_dat_o;
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output [31:0] dwb_dat_o;
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input [31:0] dwb_dat_i;
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input [31:0] dwb_dat_i;
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// FSL WISHBONE
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// FSL WISHBONE
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output [31:0] fsl_dat_o;
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output [31:0] fsl_dat_o;
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input [31:0] fsl_dat_i;
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input [31:0] fsl_dat_i;
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// SYSTEM
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// SYSTEM
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input gclk, grst, gena;
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input gclk, grst, gena;
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// --- LOAD SIZER ----------------------------------------------
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// --- LOAD SIZER ----------------------------------------------
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// Moves the data bytes around depending on the size of the
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// Moves the data bytes around depending on the size of the
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// operation.
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// operation.
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wire [31:0] wDWBDI = dwb_dat_i; // FIXME: Endian
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wire [31:0] wDWBDI = dwb_dat_i; // FIXME: Endian
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wire [31:0] wFSLDI = fsl_dat_i; // FIXME: Endian
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wire [31:0] wFSLDI = fsl_dat_i; // FIXME: Endian
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reg [31:0] rDWBDI;
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reg [31:0] rDWBDI;
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reg [1:0] rSIZ;
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reg [1:0] rSIZ;
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always @(/*AUTOSENSE*/rDWBSEL or wDWBDI or wFSLDI) begin
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always @(/*AUTOSENSE*/rDWBSEL or wDWBDI or wFSLDI) begin
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/* 51.2
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/* 51.2
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case (rSIZ)
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case (rSIZ)
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// FSL
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// FSL
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2'o3: rDWBDI <= wFSLDI;
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2'o3: rDWBDI <= wFSLDI;
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// 32'bit
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// 32'bit
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2'o2: rDWBDI <= wDWBDI;
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2'o2: rDWBDI <= wDWBDI;
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// 16'bit
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// 16'bit
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2'o1: case (rRESULT[1])
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2'o1: case (rRESULT[1])
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1'b0: rDWBDI <= {16'd0, wDWBDI[31:16]};
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1'b0: rDWBDI <= {16'd0, wDWBDI[31:16]};
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1'b1: rDWBDI <= {16'd0, wDWBDI[15:0]};
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1'b1: rDWBDI <= {16'd0, wDWBDI[15:0]};
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endcase // case (rRESULT[1])
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endcase // case (rRESULT[1])
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// 8'bit
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// 8'bit
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2'o0: case (rRESULT[1:0])
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2'o0: case (rRESULT[1:0])
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2'o0: rDWBDI <= {24'd0, wDWBDI[31:24]};
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2'o0: rDWBDI <= {24'd0, wDWBDI[31:24]};
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2'o1: rDWBDI <= {24'd0, wDWBDI[23:16]};
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2'o1: rDWBDI <= {24'd0, wDWBDI[23:16]};
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2'o2: rDWBDI <= {24'd0, wDWBDI[15:8]};
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2'o2: rDWBDI <= {24'd0, wDWBDI[15:8]};
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2'o3: rDWBDI <= {24'd0, wDWBDI[7:0]};
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2'o3: rDWBDI <= {24'd0, wDWBDI[7:0]};
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endcase // case (rRESULT[1:0])
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endcase // case (rRESULT[1:0])
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endcase // case (rSIZ)
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endcase // case (rSIZ)
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*/
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*/
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/* 50.6
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/* 50.6
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case ({rSIZ, rRESULT[1:0]})
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case ({rSIZ, rRESULT[1:0]})
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// FSL
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// FSL
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4'hC, 4'hD, 4'hE, 4'hF: rDWBDI <= wFSLDI;
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4'hC, 4'hD, 4'hE, 4'hF: rDWBDI <= wFSLDI;
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// 32'bit
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// 32'bit
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4'h8: rDWBDI <= wDWBDI;
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4'h8: rDWBDI <= wDWBDI;
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// 16'bit
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// 16'bit
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4'h4: rDWBDI <= {16'd0, wDWBDI[31:16]};
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4'h4: rDWBDI <= {16'd0, wDWBDI[31:16]};
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4'h6: rDWBDI <= {16'd0, wDWBDI[15:0]};
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4'h6: rDWBDI <= {16'd0, wDWBDI[15:0]};
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// 8'bit
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// 8'bit
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4'h0: rDWBDI <= {24'd0, wDWBDI[31:24]};
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4'h0: rDWBDI <= {24'd0, wDWBDI[31:24]};
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4'h1: rDWBDI <= {24'd0, wDWBDI[23:16]};
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4'h1: rDWBDI <= {24'd0, wDWBDI[23:16]};
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4'h2: rDWBDI <= {24'd0, wDWBDI[15:8]};
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4'h2: rDWBDI <= {24'd0, wDWBDI[15:8]};
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4'h3: rDWBDI <= {24'd0, wDWBDI[7:0]};
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4'h3: rDWBDI <= {24'd0, wDWBDI[7:0]};
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default: rDWBDI <= 32'hX;
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default: rDWBDI <= 32'hX;
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endcase // case (rSIZ)
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endcase // case (rSIZ)
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*/
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*/
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// 52.0
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// 52.0
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case (rDWBSEL)
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case (rDWBSEL)
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// 8'bit
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// 8'bit
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4'h8: rDWBDI <= {24'd0, wDWBDI[31:24]};
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4'h8: rDWBDI <= {24'd0, wDWBDI[31:24]};
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4'h4: rDWBDI <= {24'd0, wDWBDI[23:16]};
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4'h4: rDWBDI <= {24'd0, wDWBDI[23:16]};
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4'h2: rDWBDI <= {24'd0, wDWBDI[15:8]};
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4'h2: rDWBDI <= {24'd0, wDWBDI[15:8]};
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4'h1: rDWBDI <= {24'd0, wDWBDI[7:0]};
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4'h1: rDWBDI <= {24'd0, wDWBDI[7:0]};
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// 16'bit
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// 16'bit
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4'hC: rDWBDI <= {16'd0, wDWBDI[31:16]};
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4'hC: rDWBDI <= {16'd0, wDWBDI[31:16]};
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4'h3: rDWBDI <= {16'd0, wDWBDI[15:0]};
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4'h3: rDWBDI <= {16'd0, wDWBDI[15:0]};
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// 32'bit
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// 32'bit
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4'hF: rDWBDI <= wDWBDI;
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4'hF: rDWBDI <= wDWBDI;
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// FSL
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// FSL
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4'h0: rDWBDI <= wFSLDI;
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4'h0: rDWBDI <= wFSLDI;
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// Undefined
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// Undefined
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default: rDWBDI <= 32'hX;
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default: rDWBDI <= 32'hX;
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endcase
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endcase
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end
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end
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always @(posedge gclk)
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always @(posedge gclk)
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if (grst) begin
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if (grst) begin
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/*AUTORESET*/
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/*AUTORESET*/
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// Beginning of autoreset for uninitialized flops
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// Beginning of autoreset for uninitialized flops
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rSIZ <= 2'h0;
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rSIZ <= 2'h0;
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// End of automatics
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// End of automatics
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end else if (gena) begin
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end else if (gena) begin
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rSIZ <= rOPC[1:0];
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rSIZ <= rOPC[1:0];
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end
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end
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// --- GENERAL PURPOSE REGISTERS (R0-R31) -----------------------
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// --- GENERAL PURPOSE REGISTERS (R0-R31) -----------------------
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// LUT RAM implementation is smaller and faster. R0 gets written
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// LUT RAM implementation is smaller and faster. R0 gets written
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// during reset with 0x00 and doesn't change after.
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// during reset with 0x00 and doesn't change after.
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reg [31:0] mARAM[0:31],
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reg [31:0] mARAM[0:31],
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mBRAM[0:31],
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mBRAM[0:31],
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mDRAM[0:31];
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mDRAM[0:31];
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wire [31:0] rREGW = mDRAM[rRW];
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wire [31:0] rREGW = mDRAM[rRW];
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wire [31:0] rREGD = mDRAM[rRD];
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wire [31:0] rREGD = mDRAM[rRD];
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assign rREGA = mARAM[rRA];
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assign rREGA = mARAM[rRA];
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assign rREGB = mBRAM[rRB];
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assign rREGB = mBRAM[rRB];
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wire fRDWE = |rRW;
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wire fRDWE = |rRW;
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reg [31:0] xWDAT;
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reg [31:0] xWDAT;
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always @(/*AUTOSENSE*/rDWBDI or rMXDST or rPCLNK or rREGW
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always @(/*AUTOSENSE*/rDWBDI or rMXDST or rPCLNK or rREGW
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or rRESULT)
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or rRESULT)
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case (rMXDST)
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case (rMXDST)
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2'o2: xWDAT <= rDWBDI;
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2'o2: xWDAT <= rDWBDI;
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2'o1: xWDAT <= {rPCLNK, 2'o0};
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2'o1: xWDAT <= {rPCLNK, 2'o0};
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2'o0: xWDAT <= rRESULT;
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2'o0: xWDAT <= rRESULT;
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2'o3: xWDAT <= rREGW; // No change
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2'o3: xWDAT <= rREGW; // No change
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endcase // case (rMXDST)
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endcase // case (rMXDST)
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always @(posedge gclk)
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always @(posedge gclk)
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if (grst | fRDWE) begin
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if (grst | fRDWE) begin
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mARAM[rRW] <= xWDAT;
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mARAM[rRW] <= xWDAT;
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mBRAM[rRW] <= xWDAT;
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mBRAM[rRW] <= xWDAT;
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mDRAM[rRW] <= xWDAT;
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mDRAM[rRW] <= xWDAT;
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end
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end
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// --- STORE SIZER ---------------------------------------------
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// --- STORE SIZER ---------------------------------------------
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// Replicates the data bytes across depending on the size of the
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// Replicates the data bytes across depending on the size of the
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// operation.
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// operation.
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reg [31:0] rDWBDO, xDWBDO;
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reg [31:0] rDWBDO, xDWBDO;
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wire [31:0] xFSL;
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wire [31:0] xFSL;
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wire fFFWD_M = (rRA == rRW) & (rMXDST == 2'o2) & fRDWE;
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wire fFFWD_M = (rRA == rRW) & (rMXDST == 2'o2) & fRDWE;
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wire fFFWD_R = (rRA == rRW) & (rMXDST == 2'o0) & fRDWE;
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wire fFFWD_R = (rRA == rRW) & (rMXDST == 2'o0) & fRDWE;
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assign fsl_dat_o = rDWBDO;
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assign fsl_dat_o = rDWBDO;
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assign xFSL = (fFFWD_M) ? rDWBDI :
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assign xFSL = (fFFWD_M) ? rDWBDI :
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(fFFWD_R) ? rRESULT :
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(fFFWD_R) ? rRESULT :
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rREGA;
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rREGA;
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wire [31:0] xDST;
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wire [31:0] xDST;
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wire fDFWD_M = (rRW == rRD) & (rMXDST == 2'o2) & fRDWE;
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wire fDFWD_M = (rRW == rRD) & (rMXDST == 2'o2) & fRDWE;
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wire fDFWD_R = (rRW == rRD) & (rMXDST == 2'o0) & fRDWE;
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wire fDFWD_R = (rRW == rRD) & (rMXDST == 2'o0) & fRDWE;
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assign dwb_dat_o = rDWBDO;
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assign dwb_dat_o = rDWBDO;
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assign xDST = (fDFWD_M) ? rDWBDI :
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assign xDST = (fDFWD_M) ? rDWBDI :
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(fDFWD_R) ? rRESULT :
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(fDFWD_R) ? rRESULT :
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rREGD;
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rREGD;
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always @(/*AUTOSENSE*/rOPC or xDST or xFSL)
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always @(/*AUTOSENSE*/rOPC or xDST or xFSL)
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case (rOPC[1:0])
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case (rOPC[1:0])
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// 8'bit
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// 8'bit
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2'h0: xDWBDO <= {(4){xDST[7:0]}};
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2'h0: xDWBDO <= {(4){xDST[7:0]}};
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// 16'bit
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// 16'bit
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2'h1: xDWBDO <= {(2){xDST[15:0]}};
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2'h1: xDWBDO <= {(2){xDST[15:0]}};
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// 32'bit
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// 32'bit
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2'h2: xDWBDO <= xDST;
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2'h2: xDWBDO <= xDST;
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// FSL
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// FSL
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2'h3: xDWBDO <= xFSL;
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2'h3: xDWBDO <= xFSL;
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//default: xDWBDO <= 32'hX;
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//default: xDWBDO <= 32'hX;
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endcase // case (rOPC[1:0])
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endcase // case (rOPC[1:0])
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always @(posedge gclk)
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always @(posedge gclk)
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if (grst) begin
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if (grst) begin
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/*AUTORESET*/
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/*AUTORESET*/
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// Beginning of autoreset for uninitialized flops
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// Beginning of autoreset for uninitialized flops
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rDWBDO <= 32'h0;
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rDWBDO <= 32'h0;
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// End of automatics
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// End of automatics
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end else if (gena) begin
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end else if (gena) begin
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rDWBDO <= #1 xDWBDO;
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rDWBDO <= #1 xDWBDO;
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end
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end
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// --- SIMULATION ONLY ------------------------------------------
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// --- SIMULATION ONLY ------------------------------------------
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// Randomise memory to simulate real-world memory
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// Randomise memory to simulate real-world memory
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// synopsys translate_off
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// synopsys translate_off
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integer i;
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integer i;
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initial begin
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initial begin
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for (i=0; i<32; i=i+1) begin
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for (i=0; i<32; i=i+1) begin
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mARAM[i] <= $random;
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mARAM[i] <= $random;
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mBRAM[i] <= $random;
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mBRAM[i] <= $random;
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mDRAM[i] <= $random;
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mDRAM[i] <= $random;
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end
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end
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end
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end
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// synopsys translate_on
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// synopsys translate_on
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endmodule // aeMB_regf
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endmodule // aeMB_regf
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