/* $Id: aemb2.v,v 1.3 2007-12-28 21:44:50 sybreon Exp $
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/* $Id: aemb2.v,v 1.3 2007-12-28 21:44:50 sybreon Exp $
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**
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**
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** AEMB2 TEST BENCH
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** AEMB2 TEST BENCH
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** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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**
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**
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** This file is part of AEMB.
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** This file is part of AEMB.
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**
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**
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** AEMB is free software: you can redistribute it and/or modify it
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** AEMB is free software: you can redistribute it and/or modify it
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** under the terms of the GNU Lesser General Public License as
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** under the terms of the GNU Lesser General Public License as
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** published by the Free Software Foundation, either version 3 of the
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** published by the Free Software Foundation, either version 3 of the
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** License, or (at your option) any later version.
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** License, or (at your option) any later version.
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**
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**
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** AEMB is distributed in the hope that it will be useful, but WITHOUT
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** AEMB is distributed in the hope that it will be useful, but WITHOUT
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** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General
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** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General
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** Public License for more details.
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** Public License for more details.
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**
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**
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** You should have received a copy of the GNU Lesser General Public
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** You should have received a copy of the GNU Lesser General Public
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** License along with AEMB. If not, see <http:**www.gnu.org/licenses/>.
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** License along with AEMB. If not, see <http:**www.gnu.org/licenses/>.
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*/
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*/
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module aemb2 ();
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module aemb2 ();
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parameter IWB=16;
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parameter IWB=16;
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parameter DWB=16;
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parameter DWB=16;
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parameter TXE = 0; ///< thread execution enable
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parameter TXE = 0; ///< thread execution enable
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parameter MUL = 1; ///< enable hardware multiplier
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parameter MUL = 1; ///< enable hardware multiplier
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parameter BSF = 1; ///< enable barrel shifter
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parameter BSF = 1; ///< enable barrel shifter
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parameter FSL = 1; ///< enable FSL bus
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parameter FSL = 1; ///< enable FSL bus
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parameter DIV = 0; ///< enable hardware divider
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parameter DIV = 0; ///< enable hardware divider
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`include "random.v"
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`include "random.v"
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/*AUTOWIRE*/
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire [6:2] cwb_adr_o; // From dut of aeMB2_sim.v
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wire [6:2] cwb_adr_o; // From dut of aeMB2_sim.v
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wire [31:0] cwb_dat_o; // From dut of aeMB2_sim.v
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wire [31:0] cwb_dat_o; // From dut of aeMB2_sim.v
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wire [3:0] cwb_sel_o; // From dut of aeMB2_sim.v
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wire [3:0] cwb_sel_o; // From dut of aeMB2_sim.v
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wire cwb_stb_o; // From dut of aeMB2_sim.v
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wire cwb_stb_o; // From dut of aeMB2_sim.v
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wire [1:0] cwb_tga_o; // From dut of aeMB2_sim.v
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wire [1:0] cwb_tga_o; // From dut of aeMB2_sim.v
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wire cwb_wre_o; // From dut of aeMB2_sim.v
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wire cwb_wre_o; // From dut of aeMB2_sim.v
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wire [DWB-1:2] dwb_adr_o; // From dut of aeMB2_sim.v
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wire [DWB-1:2] dwb_adr_o; // From dut of aeMB2_sim.v
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wire dwb_cyc_o; // From dut of aeMB2_sim.v
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wire dwb_cyc_o; // From dut of aeMB2_sim.v
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wire [31:0] dwb_dat_o; // From dut of aeMB2_sim.v
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wire [31:0] dwb_dat_o; // From dut of aeMB2_sim.v
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wire [3:0] dwb_sel_o; // From dut of aeMB2_sim.v
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wire [3:0] dwb_sel_o; // From dut of aeMB2_sim.v
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wire dwb_stb_o; // From dut of aeMB2_sim.v
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wire dwb_stb_o; // From dut of aeMB2_sim.v
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wire dwb_tga_o; // From dut of aeMB2_sim.v
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wire dwb_tga_o; // From dut of aeMB2_sim.v
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wire dwb_wre_o; // From dut of aeMB2_sim.v
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wire dwb_wre_o; // From dut of aeMB2_sim.v
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wire [IWB-1:2] iwb_adr_o; // From dut of aeMB2_sim.v
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wire [IWB-1:2] iwb_adr_o; // From dut of aeMB2_sim.v
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wire iwb_stb_o; // From dut of aeMB2_sim.v
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wire iwb_stb_o; // From dut of aeMB2_sim.v
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wire iwb_tga_o; // From dut of aeMB2_sim.v
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wire iwb_tga_o; // From dut of aeMB2_sim.v
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wire iwb_wre_o; // From dut of aeMB2_sim.v
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wire iwb_wre_o; // From dut of aeMB2_sim.v
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// End of automatics
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// End of automatics
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/*AUTOREGINPUT*/
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/*AUTOREGINPUT*/
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// Beginning of automatic reg inputs (for undeclared instantiated-module inputs)
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// Beginning of automatic reg inputs (for undeclared instantiated-module inputs)
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reg cwb_ack_i; // To dut of aeMB2_sim.v
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reg cwb_ack_i; // To dut of aeMB2_sim.v
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reg dwb_ack_i; // To dut of aeMB2_sim.v
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reg dwb_ack_i; // To dut of aeMB2_sim.v
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reg iwb_ack_i; // To dut of aeMB2_sim.v
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reg iwb_ack_i; // To dut of aeMB2_sim.v
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reg sys_clk_i; // To dut of aeMB2_sim.v
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reg sys_clk_i; // To dut of aeMB2_sim.v
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reg sys_int_i; // To dut of aeMB2_sim.v
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reg sys_int_i; // To dut of aeMB2_sim.v
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reg sys_rst_i; // To dut of aeMB2_sim.v
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reg sys_rst_i; // To dut of aeMB2_sim.v
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// End of automatics
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// End of automatics
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// INITIAL SETUP //////////////////////////////////////////////////////
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// INITIAL SETUP //////////////////////////////////////////////////////
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//reg sys_clk_i, sys_rst_i, sys_int_i, sys_exc_i;
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//reg sys_clk_i, sys_rst_i, sys_int_i, sys_exc_i;
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reg svc;
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reg svc;
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integer inttime;
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integer inttime;
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integer seed;
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integer seed;
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integer theend;
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integer theend;
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always #5 sys_clk_i = ~sys_clk_i;
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always #5 sys_clk_i = ~sys_clk_i;
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initial begin
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initial begin
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//$dumpfile("dump.vcd");
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//$dumpfile("dump.vcd");
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//$dumpvars(1,dut, dut.bpcu);
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//$dumpvars(1,dut, dut.bpcu);
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end
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end
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initial begin
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initial begin
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seed = randseed;
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seed = randseed;
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theend = 0;
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theend = 0;
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svc = 0;
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svc = 0;
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sys_clk_i = $random(seed);
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sys_clk_i = $random(seed);
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sys_rst_i = 1;
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sys_rst_i = 1;
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sys_int_i = 0;
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sys_int_i = 0;
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#50 sys_rst_i = 0;
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#50 sys_rst_i = 0;
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#3500000 $finish;
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#3500000 $finish;
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end
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end
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// FAKE MEMORY ////////////////////////////////////////////////////////
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// FAKE MEMORY ////////////////////////////////////////////////////////
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reg [31:0] rom [0:65535];
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reg [31:0] rom [0:65535];
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reg [31:0] ram[0:65535];
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reg [31:0] ram[0:65535];
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reg [31:0] dwblat;
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reg [31:0] dwblat;
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reg [15:2] dadr, iadr;
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reg [15:2] dadr, iadr;
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wire [31:0] dwb_dat_t = ram[dwb_adr_o];
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wire [31:0] dwb_dat_t = ram[dwb_adr_o];
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wire [31:0] iwb_dat_i = rom[iadr];
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wire [31:0] iwb_dat_i = rom[iadr];
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wire [31:0] dwb_dat_i = ram[dadr];
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wire [31:0] dwb_dat_i = ram[dadr];
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wire [31:0] cwb_dat_i = cwb_adr_o;
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wire [31:0] cwb_dat_i = cwb_adr_o;
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`ifdef POSEDGE
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`ifdef POSEDGE
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`else // !`ifdef POSEDGE
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`else // !`ifdef POSEDGE
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always @(negedge sys_clk_i)
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always @(negedge sys_clk_i)
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if (sys_rst_i) begin
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if (sys_rst_i) begin
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/*AUTORESET*/
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/*AUTORESET*/
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// Beginning of autoreset for uninitialized flops
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// Beginning of autoreset for uninitialized flops
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cwb_ack_i <= 1'h0;
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cwb_ack_i <= 1'h0;
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dwb_ack_i <= 1'h0;
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dwb_ack_i <= 1'h0;
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iwb_ack_i <= 1'h0;
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iwb_ack_i <= 1'h0;
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// End of automatics
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// End of automatics
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end else begin
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end else begin
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iwb_ack_i <= #1 iwb_stb_o;
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iwb_ack_i <= #1 iwb_stb_o;
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dwb_ack_i <= #1 dwb_stb_o;
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dwb_ack_i <= #1 dwb_stb_o;
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cwb_ack_i <= #1 cwb_stb_o;
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cwb_ack_i <= #1 cwb_stb_o;
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end // else: !if(sys_rst_i)
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end // else: !if(sys_rst_i)
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always @(negedge sys_clk_i) begin
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always @(negedge sys_clk_i) begin
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iadr <= #1 iwb_adr_o;
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iadr <= #1 iwb_adr_o;
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dadr <= #1 dwb_adr_o;
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dadr <= #1 dwb_adr_o;
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if (dwb_wre_o & dwb_stb_o) begin
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if (dwb_wre_o & dwb_stb_o) begin
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case (dwb_sel_o)
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case (dwb_sel_o)
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4'h1: ram[dwb_adr_o] <= {dwb_dat_t[31:8], dwb_dat_o[7:0]};
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4'h1: ram[dwb_adr_o] <= {dwb_dat_t[31:8], dwb_dat_o[7:0]};
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4'h2: ram[dwb_adr_o] <= {dwb_dat_t[31:16], dwb_dat_o[15:8], dwb_dat_t[7:0]};
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4'h2: ram[dwb_adr_o] <= {dwb_dat_t[31:16], dwb_dat_o[15:8], dwb_dat_t[7:0]};
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4'h4: ram[dwb_adr_o] <= {dwb_dat_t[31:24], dwb_dat_o[23:16], dwb_dat_t[15:0]};
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4'h4: ram[dwb_adr_o] <= {dwb_dat_t[31:24], dwb_dat_o[23:16], dwb_dat_t[15:0]};
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4'h8: ram[dwb_adr_o] <= {dwb_dat_o[31:24], dwb_dat_t[23:0]};
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4'h8: ram[dwb_adr_o] <= {dwb_dat_o[31:24], dwb_dat_t[23:0]};
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4'h3: ram[dwb_adr_o] <= {dwb_dat_t[31:16], dwb_dat_o[15:0]};
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4'h3: ram[dwb_adr_o] <= {dwb_dat_t[31:16], dwb_dat_o[15:0]};
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4'hC: ram[dwb_adr_o] <= {dwb_dat_o[31:16], dwb_dat_t[15:0]};
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4'hC: ram[dwb_adr_o] <= {dwb_dat_o[31:16], dwb_dat_t[15:0]};
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4'hF: ram[dwb_adr_o] <= {dwb_dat_o};
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4'hF: ram[dwb_adr_o] <= {dwb_dat_o};
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endcase // case (dwb_sel_o)
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endcase // case (dwb_sel_o)
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end // if (dwb_we_o & dwb_stb_o)
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end // if (dwb_we_o & dwb_stb_o)
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end // always @ (negedge sys_clk_i)
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end // always @ (negedge sys_clk_i)
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`endif // !`ifdef POSEDGE
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`endif // !`ifdef POSEDGE
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integer i;
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integer i;
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initial begin
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initial begin
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for (i=0;i<65535;i=i+1) begin
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for (i=0;i<65535;i=i+1) begin
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ram[i] <= $random;
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ram[i] <= $random;
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end
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end
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#1 $readmemh("dump.vmem",rom);
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#1 $readmemh("dump.vmem",rom);
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#1 $readmemh("dump.vmem",ram);
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#1 $readmemh("dump.vmem",ram);
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end
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end
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// DISPLAY OUTPUTS ///////////////////////////////////////////////////
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// DISPLAY OUTPUTS ///////////////////////////////////////////////////
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integer rnd;
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integer rnd;
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always @(posedge sys_clk_i) begin
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always @(posedge sys_clk_i) begin
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// Interrupt Monitors
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// Interrupt Monitors
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if (!dut.sim.rMSR_IE) begin
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if (!dut.sim.rMSR_IE) begin
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rnd = $random % 30;
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rnd = $random % 30;
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inttime = $stime + 1000 + (rnd*rnd * 10);
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inttime = $stime + 1000 + (rnd*rnd * 10);
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end
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end
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if ($stime > inttime) begin
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if ($stime > inttime) begin
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sys_int_i = 1;
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sys_int_i = 1;
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svc = 0;
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svc = 0;
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end
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end
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if (($stime > inttime + 500) && !svc) begin
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if (($stime > inttime + 500) && !svc) begin
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$display("\n\t*** INTERRUPT TIMEOUT ***", inttime);
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$display("\n\t*** INTERRUPT TIMEOUT ***", inttime);
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$finish;
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$finish;
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end
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end
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if (dwb_wre_o & (dwb_dat_o == "RTNI")) sys_int_i = 0;
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if (dwb_wre_o & (dwb_dat_o == "RTNI")) sys_int_i = 0;
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/*
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/*
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if (dut.regf.fRDWE && (dut.rRD == 5'h0e) && !svc && dut.gena) begin
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if (dut.regf.fRDWE && (dut.rRD == 5'h0e) && !svc && dut.gena) begin
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svc = 1;
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svc = 1;
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//$display("\nLATENCY: ", ($stime - inttime)/10);
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//$display("\nLATENCY: ", ($stime - inttime)/10);
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end
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end
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*/
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*/
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// Pass/Fail Monitors
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// Pass/Fail Monitors
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if (dwb_wre_o & (dwb_dat_o == "FAIL")) begin
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if (dwb_wre_o & (dwb_dat_o == "FAIL")) begin
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$display("\n\tFAIL");
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$display("\n\tFAIL");
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$finish;
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$finish;
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end
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end
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if (iwb_dat_i == 32'hb8000000) begin
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if (iwb_dat_i == 32'hb8000000) begin
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theend = theend + 1;
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theend = theend + 1;
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end
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end
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if (theend == 5) begin
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if (theend == 5) begin
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$display("\n\t*** PASSED ALL TESTS ***");
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$display("\n\t*** PASSED ALL TESTS ***");
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$finish;
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$finish;
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end
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end
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end // always @ (posedge sys_clk_i)
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end // always @ (posedge sys_clk_i)
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// INTERNAL WIRING ////////////////////////////////////////////////////
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// INTERNAL WIRING ////////////////////////////////////////////////////
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aeMB2_sim
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aeMB2_sim
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#(/*AUTOINSTPARAM*/
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#(/*AUTOINSTPARAM*/
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// Parameters
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// Parameters
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.IWB (IWB),
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.IWB (IWB),
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.DWB (DWB),
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.DWB (DWB),
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.TXE (TXE),
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.TXE (TXE),
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.MUL (MUL),
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.MUL (MUL),
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.BSF (BSF),
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.BSF (BSF),
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.FSL (FSL),
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.FSL (FSL),
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.DIV (DIV))
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.DIV (DIV))
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dut (/*AUTOINST*/
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dut (/*AUTOINST*/
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// Outputs
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// Outputs
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.cwb_adr_o (cwb_adr_o[6:2]),
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.cwb_adr_o (cwb_adr_o[6:2]),
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.cwb_dat_o (cwb_dat_o[31:0]),
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.cwb_dat_o (cwb_dat_o[31:0]),
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.cwb_sel_o (cwb_sel_o[3:0]),
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.cwb_sel_o (cwb_sel_o[3:0]),
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.cwb_stb_o (cwb_stb_o),
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.cwb_stb_o (cwb_stb_o),
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.cwb_tga_o (cwb_tga_o[1:0]),
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.cwb_tga_o (cwb_tga_o[1:0]),
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.cwb_wre_o (cwb_wre_o),
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.cwb_wre_o (cwb_wre_o),
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.dwb_adr_o (dwb_adr_o[DWB-1:2]),
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.dwb_adr_o (dwb_adr_o[DWB-1:2]),
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.dwb_cyc_o (dwb_cyc_o),
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.dwb_cyc_o (dwb_cyc_o),
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.dwb_dat_o (dwb_dat_o[31:0]),
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.dwb_dat_o (dwb_dat_o[31:0]),
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.dwb_sel_o (dwb_sel_o[3:0]),
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.dwb_sel_o (dwb_sel_o[3:0]),
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.dwb_stb_o (dwb_stb_o),
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.dwb_stb_o (dwb_stb_o),
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.dwb_tga_o (dwb_tga_o),
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.dwb_tga_o (dwb_tga_o),
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.dwb_wre_o (dwb_wre_o),
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.dwb_wre_o (dwb_wre_o),
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.iwb_adr_o (iwb_adr_o[IWB-1:2]),
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.iwb_adr_o (iwb_adr_o[IWB-1:2]),
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.iwb_stb_o (iwb_stb_o),
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.iwb_stb_o (iwb_stb_o),
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.iwb_tga_o (iwb_tga_o),
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.iwb_tga_o (iwb_tga_o),
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.iwb_wre_o (iwb_wre_o),
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.iwb_wre_o (iwb_wre_o),
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// Inputs
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// Inputs
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.cwb_ack_i (cwb_ack_i),
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.cwb_ack_i (cwb_ack_i),
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.cwb_dat_i (cwb_dat_i[31:0]),
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.cwb_dat_i (cwb_dat_i[31:0]),
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.dwb_ack_i (dwb_ack_i),
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.dwb_ack_i (dwb_ack_i),
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.dwb_dat_i (dwb_dat_i[31:0]),
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.dwb_dat_i (dwb_dat_i[31:0]),
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.iwb_ack_i (iwb_ack_i),
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.iwb_ack_i (iwb_ack_i),
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.iwb_dat_i (iwb_dat_i[31:0]),
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.iwb_dat_i (iwb_dat_i[31:0]),
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.sys_clk_i (sys_clk_i),
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.sys_clk_i (sys_clk_i),
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.sys_int_i (sys_int_i),
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.sys_int_i (sys_int_i),
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.sys_rst_i (sys_rst_i));
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.sys_rst_i (sys_rst_i));
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endmodule // edk32
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endmodule // edk32
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/* $Log $ */
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/* $Log $ */
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// Local Variables:
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// Local Variables:
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// verilog-library-directories:("." "../../rtl/verilog/")
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// verilog-library-directories:("." "../../rtl/verilog/")
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// verilog-library-files:("")
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// verilog-library-files:("")
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// End:
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// End:
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