// $Id: edk32.v,v 1.9 2007-11-20 18:36:00 sybreon Exp $
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// $Id: edk32.v,v 1.10 2007-11-30 17:08:30 sybreon Exp $
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//
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//
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// AEMB EDK 3.2 Compatible Core TEST
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// AEMB EDK 3.2 Compatible Core TEST
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//
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//
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// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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//
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//
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// This file is part of AEMB.
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// This file is part of AEMB.
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//
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//
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// AEMB is free software: you can redistribute it and/or modify it
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// AEMB is free software: you can redistribute it and/or modify it
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// under the terms of the GNU Lesser General Public License as
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// under the terms of the GNU Lesser General Public License as
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// published by the Free Software Foundation, either version 3 of the
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// published by the Free Software Foundation, either version 3 of the
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// License, or (at your option) any later version.
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// License, or (at your option) any later version.
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//
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//
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// AEMB is distributed in the hope that it will be useful, but WITHOUT
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// AEMB is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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// or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General
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// or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General
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// Public License for more details.
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// Public License for more details.
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//
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//
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// You should have received a copy of the GNU Lesser General Public
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// You should have received a copy of the GNU Lesser General Public
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// License along with AEMB. If not, see <http://www.gnu.org/licenses/>.
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// License along with AEMB. If not, see <http://www.gnu.org/licenses/>.
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.9 2007/11/20 18:36:00 sybreon
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// Removed unnecessary byte acrobatics with VMEM data.
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//
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// Revision 1.8 2007/11/18 19:41:45 sybreon
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// Revision 1.8 2007/11/18 19:41:45 sybreon
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// Minor simulation fixes.
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// Minor simulation fixes.
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//
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//
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// Revision 1.7 2007/11/14 22:11:41 sybreon
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// Revision 1.7 2007/11/14 22:11:41 sybreon
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// Added posedge/negedge bus interface.
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// Added posedge/negedge bus interface.
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// Modified interrupt test system.
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// Modified interrupt test system.
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//
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//
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// Revision 1.6 2007/11/13 23:37:28 sybreon
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// Revision 1.6 2007/11/13 23:37:28 sybreon
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// Updated simulation to also check BRI 0x00 instruction.
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// Updated simulation to also check BRI 0x00 instruction.
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//
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//
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// Revision 1.5 2007/11/09 20:51:53 sybreon
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// Revision 1.5 2007/11/09 20:51:53 sybreon
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// Added GET/PUT support through a FSL bus.
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// Added GET/PUT support through a FSL bus.
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//
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//
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// Revision 1.4 2007/11/08 14:18:00 sybreon
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// Revision 1.4 2007/11/08 14:18:00 sybreon
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// Parameterised optional components.
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// Parameterised optional components.
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//
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//
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// Revision 1.3 2007/11/05 10:59:31 sybreon
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// Revision 1.3 2007/11/05 10:59:31 sybreon
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// Added random seed for simulation.
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// Added random seed for simulation.
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//
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//
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// Revision 1.2 2007/11/02 19:16:10 sybreon
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// Revision 1.2 2007/11/02 19:16:10 sybreon
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// Added interrupt simulation.
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// Added interrupt simulation.
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// Changed "human readable" simulation output.
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// Changed "human readable" simulation output.
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//
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//
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// Revision 1.1 2007/11/02 03:25:45 sybreon
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// Revision 1.1 2007/11/02 03:25:45 sybreon
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// New EDK 3.2 compatible design with optional barrel-shifter and multiplier.
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// New EDK 3.2 compatible design with optional barrel-shifter and multiplier.
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// Fixed various minor data hazard bugs.
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// Fixed various minor data hazard bugs.
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// Code compatible with -O0/1/2/3/s generated code.
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// Code compatible with -O0/1/2/3/s generated code.
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//
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//
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module edk32 ();
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module edk32 ();
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`include "random.v"
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`include "random.v"
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// INITIAL SETUP //////////////////////////////////////////////////////
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// INITIAL SETUP //////////////////////////////////////////////////////
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reg sys_clk_i, sys_rst_i, sys_int_i, sys_exc_i;
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reg sys_clk_i, sys_rst_i, sys_int_i, sys_exc_i;
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reg svc;
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reg svc;
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integer inttime;
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integer inttime;
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integer seed;
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integer seed;
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integer theend;
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integer theend;
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always #5 sys_clk_i = ~sys_clk_i;
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always #5 sys_clk_i = ~sys_clk_i;
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initial begin
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initial begin
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//$dumpfile("dump.vcd");
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//$dumpfile("dump.vcd");
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//$dumpvars(1,dut);
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//$dumpvars(1,dut);
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end
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end
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initial begin
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initial begin
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seed = randseed;
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seed = randseed;
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theend = 0;
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theend = 0;
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svc = 0;
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svc = 0;
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sys_clk_i = $random(seed);
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sys_clk_i = $random(seed);
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sys_rst_i = 1;
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sys_rst_i = 1;
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sys_int_i = 0;
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sys_int_i = 0;
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sys_exc_i = 0;
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sys_exc_i = 0;
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#50 sys_rst_i = 0;
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#50 sys_rst_i = 0;
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end
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end
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initial fork
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initial fork
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//inttime $display("FSADFASDFSDAF");
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//inttime $display("FSADFASDFSDAF");
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//#10000 sys_int_i = 1;
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//#10000 sys_int_i = 1;
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//#1100 sys_int_i = 0;
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//#1100 sys_int_i = 0;
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//#100000 $displayh("\nTest Completed.");
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//#100000 $displayh("\nTest Completed.");
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//#4000 $finish;
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//#4000 $finish;
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join
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join
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// FAKE MEMORY ////////////////////////////////////////////////////////
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// FAKE MEMORY ////////////////////////////////////////////////////////
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wire fsl_stb_o;
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wire fsl_stb_o;
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wire fsl_wre_o;
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wire fsl_wre_o;
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wire [31:0] fsl_dat_o;
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wire [31:0] fsl_dat_o;
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wire [31:0] fsl_dat_i;
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wire [31:0] fsl_dat_i;
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wire [6:2] fsl_adr_o;
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wire [6:2] fsl_adr_o;
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wire [15:2] iwb_adr_o;
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wire [15:2] iwb_adr_o;
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wire iwb_stb_o;
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wire iwb_stb_o;
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wire dwb_stb_o;
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wire dwb_stb_o;
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reg [31:0] rom [0:65535];
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reg [31:0] rom [0:65535];
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wire [31:0] iwb_dat_i;
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wire [31:0] iwb_dat_i;
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reg iwb_ack_i, dwb_ack_i, fsl_ack_i;
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reg iwb_ack_i, dwb_ack_i, fsl_ack_i;
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reg [31:0] ram[0:65535];
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reg [31:0] ram[0:65535];
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wire [31:0] dwb_dat_i;
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wire [31:0] dwb_dat_i;
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reg [31:0] dwblat;
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reg [31:0] dwblat;
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wire dwb_we_o;
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wire dwb_we_o;
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reg [15:2] dadr,iadr;
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reg [15:2] dadr,iadr;
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wire [3:0] dwb_sel_o;
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wire [3:0] dwb_sel_o;
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wire [31:0] dwb_dat_o;
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wire [31:0] dwb_dat_o;
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wire [15:2] dwb_adr_o;
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wire [15:2] dwb_adr_o;
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wire [31:0] dwb_dat_t;
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wire [31:0] dwb_dat_t;
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initial begin
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initial begin
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dwb_ack_i = 0;
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dwb_ack_i = 0;
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iwb_ack_i = 0;
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iwb_ack_i = 0;
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fsl_ack_i = 0;
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fsl_ack_i = 0;
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end
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end
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assign dwb_dat_t = ram[dwb_adr_o];
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assign dwb_dat_t = ram[dwb_adr_o];
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assign iwb_dat_i = ram[iadr];
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assign iwb_dat_i = ram[iadr];
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assign dwb_dat_i = ram[dadr];
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assign dwb_dat_i = ram[dadr];
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assign fsl_dat_i = fsl_adr_o;
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assign fsl_dat_i = fsl_adr_o;
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//`define POSEDGE
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`ifdef POSEDGE
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`ifdef POSEDGE
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always @(posedge sys_clk_i)
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always @(posedge sys_clk_i)
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if (sys_rst_i) begin
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if (sys_rst_i) begin
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/*AUTORESET*/
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/*AUTORESET*/
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// Beginning of autoreset for uninitialized flops
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// Beginning of autoreset for uninitialized flops
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dwb_ack_i <= 1'h0;
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dwb_ack_i <= 1'h0;
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fsl_ack_i <= 1'h0;
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fsl_ack_i <= 1'h0;
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iwb_ack_i <= 1'h0;
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iwb_ack_i <= 1'h0;
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// End of automatics
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// End of automatics
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end else begin
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end else begin
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iwb_ack_i <= #1 iwb_stb_o ^ iwb_ack_i;
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iwb_ack_i <= #1 iwb_stb_o ^ iwb_ack_i;
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dwb_ack_i <= #1 dwb_stb_o ^ dwb_ack_i;
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dwb_ack_i <= #1 dwb_stb_o ^ dwb_ack_i;
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fsl_ack_i <= #1 fsl_stb_o ^ fsl_ack_i;
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fsl_ack_i <= #1 fsl_stb_o ^ fsl_ack_i;
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end
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end // else: !if(sys_rst_i)
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always @(posedge sys_clk_i) begin
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always @(posedge sys_clk_i) begin
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iadr <= #1 iwb_adr_o;
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iadr <= #1 iwb_adr_o;
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dadr <= #1 dwb_adr_o;
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dadr <= #1 dwb_adr_o;
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if (dwb_we_o & dwb_stb_o) begin
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if (dwb_we_o & dwb_stb_o) begin
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case (dwb_sel_o)
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case (dwb_sel_o)
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4'h1: ram[dwb_adr_o] <= {dwb_dat_t[31:8], dwb_dat_o[7:0]};
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4'h1: ram[dwb_adr_o] <= {dwb_dat_t[31:8], dwb_dat_o[7:0]};
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4'h2: ram[dwb_adr_o] <= {dwb_dat_t[31:16], dwb_dat_o[15:8], dwb_dat_t[7:0]};
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4'h2: ram[dwb_adr_o] <= {dwb_dat_t[31:16], dwb_dat_o[15:8], dwb_dat_t[7:0]};
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4'h4: ram[dwb_adr_o] <= {dwb_dat_t[31:24], dwb_dat_o[23:16], dwb_dat_t[15:0]};
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4'h4: ram[dwb_adr_o] <= {dwb_dat_t[31:24], dwb_dat_o[23:16], dwb_dat_t[15:0]};
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4'h8: ram[dwb_adr_o] <= {dwb_dat_o[31:24], dwb_dat_t[23:0]};
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4'h8: ram[dwb_adr_o] <= {dwb_dat_o[31:24], dwb_dat_t[23:0]};
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4'h3: ram[dwb_adr_o] <= {dwb_dat_t[31:16], dwb_dat_o[15:0]};
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4'h3: ram[dwb_adr_o] <= {dwb_dat_t[31:16], dwb_dat_o[15:0]};
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4'hC: ram[dwb_adr_o] <= {dwb_dat_o[31:16], dwb_dat_t[15:0]};
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4'hC: ram[dwb_adr_o] <= {dwb_dat_o[31:16], dwb_dat_t[15:0]};
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4'hF: ram[dwb_adr_o] <= {dwb_dat_o};
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4'hF: ram[dwb_adr_o] <= {dwb_dat_o};
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endcase // case (dwb_sel_o)
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endcase // case (dwb_sel_o)
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end // if (dwb_we_o & dwb_stb_o)
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end // if (dwb_we_o & dwb_stb_o)
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end // always @ (negedge sys_clk_i)
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end // always @ (posedge sys_clk_i)
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`else // !`ifdef POSEDGE
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`else // !`ifdef POSEDGE
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always @(negedge sys_clk_i)
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always @(negedge sys_clk_i)
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if (sys_rst_i) begin
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if (sys_rst_i) begin
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/*AUTORESET*/
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/*AUTORESET*/
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// Beginning of autoreset for uninitialized flops
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// Beginning of autoreset for uninitialized flops
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dwb_ack_i <= 1'h0;
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dwb_ack_i <= 1'h0;
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fsl_ack_i <= 1'h0;
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fsl_ack_i <= 1'h0;
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iwb_ack_i <= 1'h0;
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iwb_ack_i <= 1'h0;
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// End of automatics
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// End of automatics
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end else begin
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end else begin
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iwb_ack_i <= #1 iwb_stb_o;
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iwb_ack_i <= #1 iwb_stb_o;
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dwb_ack_i <= #1 dwb_stb_o;
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dwb_ack_i <= #1 dwb_stb_o;
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fsl_ack_i <= #1 fsl_stb_o;
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fsl_ack_i <= #1 fsl_stb_o;
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end
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end // else: !if(sys_rst_i)
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always @(negedge sys_clk_i) begin
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always @(negedge sys_clk_i) begin
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iadr <= #1 iwb_adr_o;
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iadr <= #1 iwb_adr_o;
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dadr <= #1 dwb_adr_o;
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dadr <= #1 dwb_adr_o;
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if (dwb_we_o & dwb_stb_o) begin
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if (dwb_we_o & dwb_stb_o) begin
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case (dwb_sel_o)
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case (dwb_sel_o)
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4'h1: ram[dwb_adr_o] <= {dwb_dat_t[31:8], dwb_dat_o[7:0]};
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4'h1: ram[dwb_adr_o] <= {dwb_dat_t[31:8], dwb_dat_o[7:0]};
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4'h2: ram[dwb_adr_o] <= {dwb_dat_t[31:16], dwb_dat_o[15:8], dwb_dat_t[7:0]};
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4'h2: ram[dwb_adr_o] <= {dwb_dat_t[31:16], dwb_dat_o[15:8], dwb_dat_t[7:0]};
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4'h4: ram[dwb_adr_o] <= {dwb_dat_t[31:24], dwb_dat_o[23:16], dwb_dat_t[15:0]};
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4'h4: ram[dwb_adr_o] <= {dwb_dat_t[31:24], dwb_dat_o[23:16], dwb_dat_t[15:0]};
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4'h8: ram[dwb_adr_o] <= {dwb_dat_o[31:24], dwb_dat_t[23:0]};
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4'h8: ram[dwb_adr_o] <= {dwb_dat_o[31:24], dwb_dat_t[23:0]};
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4'h3: ram[dwb_adr_o] <= {dwb_dat_t[31:16], dwb_dat_o[15:0]};
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4'h3: ram[dwb_adr_o] <= {dwb_dat_t[31:16], dwb_dat_o[15:0]};
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4'hC: ram[dwb_adr_o] <= {dwb_dat_o[31:16], dwb_dat_t[15:0]};
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4'hC: ram[dwb_adr_o] <= {dwb_dat_o[31:16], dwb_dat_t[15:0]};
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4'hF: ram[dwb_adr_o] <= {dwb_dat_o};
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4'hF: ram[dwb_adr_o] <= {dwb_dat_o};
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endcase // case (dwb_sel_o)
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endcase // case (dwb_sel_o)
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end // if (dwb_we_o & dwb_stb_o)
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end // if (dwb_we_o & dwb_stb_o)
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end // always @ (negedge sys_clk_i)
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end // always @ (negedge sys_clk_i)
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`endif // !`ifdef POSEDGE
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`endif // !`ifdef POSEDGE
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integer i;
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integer i;
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initial begin
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initial begin
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for (i=0;i<65535;i=i+1) begin
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for (i=0;i<65535;i=i+1) begin
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ram[i] <= $random;
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ram[i] <= $random;
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end
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end
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#1 $readmemh("dump.rom",ram);
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#1 $readmemh("dump.rom",ram);
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end
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end
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// DISPLAY OUTPUTS ///////////////////////////////////////////////////
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// DISPLAY OUTPUTS ///////////////////////////////////////////////////
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//assign dut.rRESULT = dut.rSIMM;
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integer rnd;
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integer rnd;
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always @(posedge sys_clk_i) begin
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always @(posedge sys_clk_i) begin
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// Interrupt Monitors
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// Interrupt Monitors
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if (!dut.rMSR_IE) begin
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if (!dut.rMSR_IE) begin
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rnd = $random % 30;
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rnd = $random % 30;
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inttime = $stime + 1000 + (rnd*rnd * 10);
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inttime = $stime + 1000 + (rnd*rnd * 10);
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end
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end
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if ($stime > inttime) begin
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if ($stime > inttime) begin
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sys_int_i = 1;
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sys_int_i = 1;
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svc = 0;
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svc = 0;
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end
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end
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if (($stime > inttime + 500) && !svc) begin
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if (($stime > inttime + 500) && !svc) begin
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$display("\n\t*** INTERRUPT TIMEOUT ***", inttime);
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$display("\n\t*** INTERRUPT TIMEOUT ***", inttime);
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$finish;
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$finish;
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end
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end
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if (dwb_we_o & (dwb_dat_o == "RTNI")) sys_int_i = 0;
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if (dwb_we_o & (dwb_dat_o == "RTNI")) sys_int_i = 0;
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if (dut.regf.fRDWE && (dut.rRD == 5'h0e) && !svc && dut.gena) begin
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if (dut.regf.fRDWE && (dut.rRD == 5'h0e) && !svc && dut.gena) begin
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svc = 1;
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svc = 1;
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//$display("\nLATENCY: ", ($stime - inttime)/10);
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//$display("\nLATENCY: ", ($stime - inttime)/10);
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end
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end
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// Pass/Fail Monitors
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// Pass/Fail Monitors
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if (dwb_we_o & (dwb_dat_o == "FAIL")) begin
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if (dwb_we_o & (dwb_dat_o == "FAIL")) begin
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$display("\n\tFAIL");
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$display("\n\tFAIL");
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$finish;
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$finish;
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end
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end
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if (iwb_dat_i == 32'hb8000000) begin
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if (iwb_dat_i == 32'hb8000000) begin
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theend = theend + 1;
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theend = theend + 1;
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end
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end
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if (theend == 5) begin
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if (theend == 5) begin
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$display("\n\t*** PASSED ALL TESTS ***");
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$display("\n\t*** PASSED ALL TESTS ***");
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$finish;
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$finish;
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end
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end
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end // always @ (posedge sys_clk_i)
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end // always @ (posedge sys_clk_i)
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always @(posedge sys_clk_i) if (dut.gena) begin
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$write ("\n", ($stime/10));
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$writeh ("\tPC=", {iwb_adr_o,2'd0});
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// DECODE
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$writeh ("\t");
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case ({dut.rBRA, dut.rDLY})
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2'b00: $write(" ");
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2'b01: $write(".");
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2'b10: $write("-");
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2'b11: $write("+");
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endcase // case ({dut.rBRA, dut.rDLY})
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case (dut.rOPC)
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6'o00: if (dut.rRD == 0) $write(" "); else $write("ADD");
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6'o01: $write("RSUB");
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6'o02: $write("ADDC");
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6'o03: $write("RSUBC");
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6'o04: $write("ADDK");
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6'o05: case (dut.rIMM[1:0])
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2'o0: $write("RSUBK");
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2'o1: $write("CMP");
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2'o3: $write("CMPU");
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default: $write("XXX");
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endcase // case (dut.rIMM[1:0])
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6'o06: $write("ADDKC");
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6'o07: $write("RSUBKC");
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6'o10: $write("ADDI");
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6'o11: $write("RSUBI");
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6'o12: $write("ADDIC");
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6'o13: $write("RSUBIC");
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6'o14: $write("ADDIK");
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6'o15: $write("RSUBIK");
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6'o16: $write("ADDIKC");
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6'o17: $write("RSUBIKC");
|
|
|
|
6'o20: $write("MUL");
|
|
6'o21: case (dut.rALT[10:9])
|
|
2'o0: $write("BSRL");
|
|
2'o1: $write("BSRA");
|
|
2'o2: $write("BSLL");
|
|
default: $write("XXX");
|
|
endcase // case (dut.rALT[10:9])
|
|
6'o22: $write("IDIV");
|
|
|
|
6'o30: $write("MULI");
|
|
6'o31: case (dut.rALT[10:9])
|
|
2'o0: $write("BSRLI");
|
|
2'o1: $write("BSRAI");
|
|
2'o2: $write("BSLLI");
|
|
default: $write("XXX");
|
|
endcase // case (dut.rALT[10:9])
|
|
6'o33: case (dut.rRB[4:2])
|
|
3'o0: $write("GET");
|
|
3'o4: $write("PUT");
|
|
3'o2: $write("NGET");
|
|
3'o6: $write("NPUT");
|
|
3'o1: $write("CGET");
|
|
3'o5: $write("CPUT");
|
|
3'o3: $write("NCGET");
|
|
3'o7: $write("NCPUT");
|
|
endcase // case (dut.rRB[4:2])
|
|
|
|
|
|
6'o40: $write("OR");
|
|
6'o41: $write("AND");
|
|
6'o42: if (dut.rRD == 0) $write(" "); else $write("XOR");
|
|
6'o43: $write("ANDN");
|
|
6'o44: case (dut.rIMM[6:5])
|
|
2'o0: $write("SRA");
|
|
2'o1: $write("SRC");
|
|
2'o2: $write("SRL");
|
|
2'o3: if (dut.rIMM[0]) $write("SEXT16"); else $write("SEXT8");
|
|
endcase // case (dut.rIMM[6:5])
|
|
|
|
6'o45: $write("MOV");
|
|
6'o46: case (dut.rRA[3:2])
|
|
3'o0: $write("BR");
|
|
3'o1: $write("BRL");
|
|
3'o2: $write("BRA");
|
|
3'o3: $write("BRAL");
|
|
endcase // case (dut.rRA[3:2])
|
|
|
|
6'o47: case (dut.rRD[2:0])
|
|
3'o0: $write("BEQ");
|
|
3'o1: $write("BNE");
|
|
3'o2: $write("BLT");
|
|
3'o3: $write("BLE");
|
|
3'o4: $write("BGT");
|
|
3'o5: $write("BGE");
|
|
default: $write("XXX");
|
|
endcase // case (dut.rRD[2:0])
|
|
|
|
6'o50: $write("ORI");
|
|
6'o51: $write("ANDI");
|
|
6'o52: $write("XORI");
|
|
6'o53: $write("ANDNI");
|
|
6'o54: $write("IMMI");
|
|
6'o55: case (dut.rRD[1:0])
|
|
2'o0: $write("RTSD");
|
|
2'o1: $write("RTID");
|
|
2'o2: $write("RTBD");
|
|
default: $write("XXX");
|
|
endcase
|
|
6'o56: case (dut.rRA[3:2])
|
|
3'o0: $write("BRI");
|
|
3'o1: $write("BRLI");
|
|
3'o2: $write("BRAI");
|
|
3'o3: $write("BRALI");
|
|
endcase // case (dut.rRA[3:2])
|
|
6'o57: case (dut.rRD[2:0])
|
|
3'o0: $write("BEQI");
|
|
3'o1: $write("BNEI");
|
|
3'o2: $write("BLTI");
|
|
3'o3: $write("BLEI");
|
|
3'o4: $write("BGTI");
|
|
3'o5: $write("BGEI");
|
|
default: $write("XXX");
|
|
endcase // case (dut.rRD[2:0])
|
|
|
|
6'o60: $write("LBU");
|
|
6'o61: $write("LHU");
|
|
6'o62: $write("LW");
|
|
6'o64: $write("SB");
|
|
6'o65: $write("SH");
|
|
6'o66: $write("SW");
|
|
|
|
6'o70: $write("LBUI");
|
|
6'o71: $write("LHUI");
|
|
6'o72: $write("LWI");
|
|
6'o74: $write("SBI");
|
|
6'o75: $write("SHI");
|
|
6'o76: $write("SWI");
|
|
|
|
default: $write("XXX");
|
|
endcase // case (dut.rOPC)
|
|
|
|
case (dut.rOPC[3])
|
|
1'b1: $writeh("\tr",dut.rRD,", r",dut.rRA,", h",dut.rIMM);
|
|
1'b0: $writeh("\tr",dut.rRD,", r",dut.rRA,", r",dut.rRB," ");
|
|
endcase // case (dut.rOPC[3])
|
|
|
|
|
|
// ALU
|
|
$write("\t");
|
|
//$writeh(" I=",dut.rSIMM);
|
|
$writeh(" A=",dut.xecu.rOPA);
|
|
$writeh(" B=",dut.xecu.rOPB);
|
|
|
|
case (dut.rMXALU)
|
|
3'o0: $write(" ADD");
|
|
3'o1: $write(" LOG");
|
|
3'o2: $write(" SFT");
|
|
3'o3: $write(" MOV");
|
|
3'o4: $write(" MUL");
|
|
3'o5: $write(" BSF");
|
|
default: $write(" XXX");
|
|
endcase // case (dut.rMXALU)
|
|
$writeh("=h",dut.xecu.xRESULT);
|
|
|
|
// WRITEBACK
|
|
$writeh("\tSR=", {dut.xecu.rMSR_BIP, dut.xecu.rMSR_C, dut.xecu.rMSR_IE, dut.xecu.rMSR_BE}," ");
|
|
|
|
if (dut.regf.fRDWE) begin
|
|
case (dut.rMXDST)
|
|
2'o2: begin
|
|
if (dut.dwb_stb_o) $writeh("R",dut.rRW,"=RAM(h",dut.regf.xWDAT,")");
|
|
if (dut.fsl_stb_o) $writeh("R",dut.rRW,"=FSL(h",dut.regf.xWDAT,")");
|
|
end
|
|
2'o1: $writeh("R",dut.rRW,"=LNK(h",dut.regf.xWDAT,")");
|
|
2'o0: $writeh("R",dut.rRW,"=ALU(h",dut.regf.xWDAT,")");
|
|
endcase // case (dut.rMXDST)
|
|
end
|
|
|
|
// STORE
|
|
if (dwb_stb_o & dwb_we_o) $writeh("RAM(",{dwb_adr_o,2'd0},")=",dwb_dat_o,":",dwb_sel_o);
|
|
|
|
end // if (dut.gena)
|
|
|
|
|
|
// INTERNAL WIRING ////////////////////////////////////////////////////
|
// INTERNAL WIRING ////////////////////////////////////////////////////
|
|
|
aeMB_edk32 #(16,16)
|
aeMB_edk32 #(16,16)
|
dut (
|
dut (
|
.sys_int_i(sys_int_i),
|
.sys_int_i(sys_int_i),
|
.dwb_ack_i(dwb_ack_i),
|
.dwb_ack_i(dwb_ack_i),
|
.dwb_stb_o(dwb_stb_o),
|
.dwb_stb_o(dwb_stb_o),
|
.dwb_adr_o(dwb_adr_o),
|
.dwb_adr_o(dwb_adr_o),
|
.dwb_dat_o(dwb_dat_o),
|
.dwb_dat_o(dwb_dat_o),
|
.dwb_dat_i(dwb_dat_i),
|
.dwb_dat_i(dwb_dat_i),
|
.dwb_wre_o(dwb_we_o),
|
.dwb_wre_o(dwb_we_o),
|
.dwb_sel_o(dwb_sel_o),
|
.dwb_sel_o(dwb_sel_o),
|
|
|
.fsl_ack_i(fsl_ack_i),
|
.fsl_ack_i(fsl_ack_i),
|
.fsl_stb_o(fsl_stb_o),
|
.fsl_stb_o(fsl_stb_o),
|
.fsl_adr_o(fsl_adr_o),
|
.fsl_adr_o(fsl_adr_o),
|
.fsl_dat_o(fsl_dat_o),
|
.fsl_dat_o(fsl_dat_o),
|
.fsl_dat_i(fsl_dat_i),
|
.fsl_dat_i(fsl_dat_i),
|
.fsl_wre_o(fsl_we_o),
|
.fsl_wre_o(fsl_we_o),
|
|
|
.iwb_adr_o(iwb_adr_o),
|
.iwb_adr_o(iwb_adr_o),
|
.iwb_dat_i(iwb_dat_i),
|
.iwb_dat_i(iwb_dat_i),
|
.iwb_stb_o(iwb_stb_o),
|
.iwb_stb_o(iwb_stb_o),
|
.iwb_ack_i(iwb_ack_i),
|
.iwb_ack_i(iwb_ack_i),
|
.sys_clk_i(sys_clk_i),
|
.sys_clk_i(sys_clk_i),
|
.sys_rst_i(sys_rst_i)
|
.sys_rst_i(sys_rst_i)
|
);
|
);
|
|
|
|
|
|
|
|
|
|
|
endmodule // edk32
|
endmodule // edk32
|
|
|
