/*
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/*
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** AEMB2 EDK 6.3 COMPATIBLE CORE
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** AEMB2 EDK 6.3 COMPATIBLE CORE
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** Copyright (C) 2004-2008 Shawn Tan <shawn.tan@aeste.net>
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** Copyright (C) 2004-2008 Shawn Tan <shawn.tan@aeste.net>
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**
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**
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** This file is part of AEMB.
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** This file is part of AEMB.
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**
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**
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** AEMB is free software: you can redistribute it and/or modify it
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** AEMB is free software: you can redistribute it and/or modify it
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** under the terms of the GNU Lesser General Public License as
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** under the terms of the GNU Lesser General Public License as
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** published by the Free Software Foundation, either version 3 of the
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** published by the Free Software Foundation, either version 3 of the
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** License, or (at your option) any later version.
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** License, or (at your option) any later version.
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**
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**
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** AEMB is distributed in the hope that it will be useful, but WITHOUT
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** AEMB is distributed in the hope that it will be useful, but WITHOUT
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** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General
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** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General
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** Public License for more details.
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** Public License for more details.
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**
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**
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** You should have received a copy of the GNU Lesser General Public
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** You should have received a copy of the GNU Lesser General Public
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** License along with AEMB. If not, see <http:**www.gnu.org/licenses/>.
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** License along with AEMB. If not, see <http:**www.gnu.org/licenses/>.
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*/
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*/
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/**
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/**
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Simulation Test Bench
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Simulation Test Bench
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@file edk62.v
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@file edk62.v
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*/
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*/
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`include "random.v"
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`include "random.v"
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module edk63();
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module edk63();
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localparam AEMB_DWB = 18;
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localparam AEMB_DWB = 18;
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localparam AEMB_XWB = 5;
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localparam AEMB_XWB = 5;
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localparam AEMB_IWB = 18;
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localparam AEMB_IWB = 18;
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localparam AEMB_ICH = 11;
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localparam AEMB_ICH = 11;
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localparam AEMB_IDX = 6;
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localparam AEMB_IDX = 6;
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localparam AEMB_HTX = 1;
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localparam AEMB_HTX = 1;
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localparam AEMB_BSF = 1;
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localparam AEMB_BSF = 1;
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localparam AEMB_MUL = 1;
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localparam AEMB_MUL = 1;
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localparam AEMB_XSL = 1;
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localparam AEMB_XSL = 1;
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localparam AEMB_DIV = 0;
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localparam AEMB_DIV = 0;
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localparam AEMB_FPU = 0;
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localparam AEMB_FPU = 0;
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/*AUTOREGINPUT*/
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/*AUTOREGINPUT*/
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// Beginning of automatic reg inputs (for undeclared instantiated-module inputs)
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// Beginning of automatic reg inputs (for undeclared instantiated-module inputs)
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reg dwb_ack_i; // To uut of aeMB2_edk63.v
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reg dwb_ack_i; // To uut of aeMB2_edk63.v
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reg iwb_ack_i; // To uut of aeMB2_edk63.v
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reg iwb_ack_i; // To uut of aeMB2_edk63.v
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reg sys_clk_i; // To uut of aeMB2_edk63.v
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reg sys_clk_i; // To uut of aeMB2_edk63.v
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reg sys_ena_i; // To uut of aeMB2_edk63.v
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reg sys_ena_i; // To uut of aeMB2_edk63.v
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reg sys_int_i; // To uut of aeMB2_edk63.v
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reg sys_int_i; // To uut of aeMB2_edk63.v
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reg sys_rst_i; // To uut of aeMB2_edk63.v
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reg sys_rst_i; // To uut of aeMB2_edk63.v
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reg xwb_ack_i; // To uut of aeMB2_edk63.v
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reg xwb_ack_i; // To uut of aeMB2_edk63.v
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// End of automatics
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// End of automatics
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always #5 sys_clk_i <= !sys_clk_i;
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always #5 sys_clk_i <= !sys_clk_i;
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initial begin
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initial begin
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`ifdef VCD_DUMP
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`ifdef VCD_DUMP
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$dumpfile ("dump.vcd");
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$dumpfile ("dump.vcd");
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$dumpvars (1,uut);
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$dumpvars (1,uut);
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`endif
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`endif
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sys_clk_i = $random(`randseed);
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sys_clk_i = $random(`randseed);
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sys_rst_i = 1;
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sys_rst_i = 1;
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sys_ena_i = 1;
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sys_ena_i = 1;
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sys_int_i = 1;
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sys_int_i = 1;
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xwb_ack_i = 0;
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xwb_ack_i = 0;
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#50 sys_rst_i = 0;
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#50 sys_rst_i = 0;
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#4000000 $displayh("\n*** TIMEOUT ", $stime, " ***"); $finish;
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#4000000 $displayh("\n*** TIMEOUT ", $stime, " ***"); $finish;
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end // initial begin
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end // initial begin
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/*AUTOWIRE*/
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire [AEMB_DWB-1:2] dwb_adr_o; // From uut of aeMB2_edk63.v
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wire [AEMB_DWB-1:2] dwb_adr_o; // From uut of aeMB2_edk63.v
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wire dwb_cyc_o; // From uut of aeMB2_edk63.v
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wire dwb_cyc_o; // From uut of aeMB2_edk63.v
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wire [31:0] dwb_dat_o; // From uut of aeMB2_edk63.v
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wire [31:0] dwb_dat_o; // From uut of aeMB2_edk63.v
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wire [3:0] dwb_sel_o; // From uut of aeMB2_edk63.v
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wire [3:0] dwb_sel_o; // From uut of aeMB2_edk63.v
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wire dwb_stb_o; // From uut of aeMB2_edk63.v
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wire dwb_stb_o; // From uut of aeMB2_edk63.v
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wire dwb_tag_o; // From uut of aeMB2_edk63.v
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wire dwb_tag_o; // From uut of aeMB2_edk63.v
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wire dwb_wre_o; // From uut of aeMB2_edk63.v
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wire dwb_wre_o; // From uut of aeMB2_edk63.v
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wire [AEMB_IWB-1:2] iwb_adr_o; // From uut of aeMB2_edk63.v
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wire [AEMB_IWB-1:2] iwb_adr_o; // From uut of aeMB2_edk63.v
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wire iwb_cyc_o; // From uut of aeMB2_edk63.v
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wire iwb_cyc_o; // From uut of aeMB2_edk63.v
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wire [3:0] iwb_sel_o; // From uut of aeMB2_edk63.v
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wire [3:0] iwb_sel_o; // From uut of aeMB2_edk63.v
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wire iwb_stb_o; // From uut of aeMB2_edk63.v
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wire iwb_stb_o; // From uut of aeMB2_edk63.v
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wire iwb_tag_o; // From uut of aeMB2_edk63.v
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wire iwb_tag_o; // From uut of aeMB2_edk63.v
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wire iwb_wre_o; // From uut of aeMB2_edk63.v
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wire iwb_wre_o; // From uut of aeMB2_edk63.v
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wire [AEMB_XWB-1:2] xwb_adr_o; // From uut of aeMB2_edk63.v
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wire [AEMB_XWB-1:2] xwb_adr_o; // From uut of aeMB2_edk63.v
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wire xwb_cyc_o; // From uut of aeMB2_edk63.v
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wire xwb_cyc_o; // From uut of aeMB2_edk63.v
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wire [31:0] xwb_dat_o; // From uut of aeMB2_edk63.v
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wire [31:0] xwb_dat_o; // From uut of aeMB2_edk63.v
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wire [3:0] xwb_sel_o; // From uut of aeMB2_edk63.v
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wire [3:0] xwb_sel_o; // From uut of aeMB2_edk63.v
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wire xwb_stb_o; // From uut of aeMB2_edk63.v
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wire xwb_stb_o; // From uut of aeMB2_edk63.v
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wire xwb_tag_o; // From uut of aeMB2_edk63.v
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wire xwb_tag_o; // From uut of aeMB2_edk63.v
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wire xwb_wre_o; // From uut of aeMB2_edk63.v
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wire xwb_wre_o; // From uut of aeMB2_edk63.v
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// End of automatics
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// End of automatics
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// FAKE MEMORY ////////////////////////////////////////////////////////
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// FAKE MEMORY ////////////////////////////////////////////////////////
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reg [31:0] rom[0:65535];
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reg [31:0] rom[0:65535];
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reg [31:0] ram[0:65535];
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reg [31:0] ram[0:65535];
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reg [31:0] dwblat;
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reg [31:0] dwblat;
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reg [31:0] xwblat;
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reg [31:0] xwblat;
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reg [31:2] dadr, iadr;
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reg [31:2] dadr, iadr;
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wire [31:0] dwb_dat_t = ram[dwb_adr_o];
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wire [31:0] dwb_dat_t = ram[dwb_adr_o];
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wire [31:0] iwb_dat_i = rom[iadr];
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wire [31:0] iwb_dat_i = rom[iadr];
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wire [31:0] dwb_dat_i = ram[dadr];
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wire [31:0] dwb_dat_i = ram[dadr];
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wire [31:0] xwb_dat_i = xwblat;
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wire [31:0] xwb_dat_i = xwblat;
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always @(posedge sys_clk_i)
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always @(posedge sys_clk_i)
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if (sys_rst_i) begin
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if (sys_rst_i) begin
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/*AUTORESET*/
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/*AUTORESET*/
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// Beginning of autoreset for uninitialized flops
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// Beginning of autoreset for uninitialized flops
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dwb_ack_i <= 1'h0;
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dwb_ack_i <= 1'h0;
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iwb_ack_i <= 1'h0;
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iwb_ack_i <= 1'h0;
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xwb_ack_i <= 1'h0;
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xwb_ack_i <= 1'h0;
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// End of automatics
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// End of automatics
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end else begin
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end else begin
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iwb_ack_i <= #1 iwb_stb_o & !iwb_ack_i;
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iwb_ack_i <= #1 iwb_stb_o & !iwb_ack_i;
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dwb_ack_i <= #1 dwb_stb_o & !dwb_ack_i;
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dwb_ack_i <= #1 dwb_stb_o & !dwb_ack_i;
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xwb_ack_i <= #1 xwb_stb_o & !xwb_ack_i;
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xwb_ack_i <= #1 xwb_stb_o & !xwb_ack_i;
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end // else: !if(sys_rst_i)
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end // else: !if(sys_rst_i)
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always @(posedge sys_clk_i) begin
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always @(posedge sys_clk_i) begin
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iadr <= #1 iwb_adr_o;
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iadr <= #1 iwb_adr_o;
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dadr <= #1 dwb_adr_o;
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dadr <= #1 dwb_adr_o;
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if (xwb_wre_o & xwb_stb_o & xwb_ack_i) begin
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if (xwb_wre_o & xwb_stb_o & xwb_ack_i) begin
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xwblat <= #1 xwb_dat_o;
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xwblat <= #1 xwb_dat_o;
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end
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end
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// SPECIAL PORTS
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// SPECIAL PORTS
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if (dwb_wre_o & dwb_stb_o & dwb_ack_i) begin
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if (dwb_wre_o & dwb_stb_o & dwb_ack_i) begin
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case ({dwb_adr_o,2'o0})
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case ({dwb_adr_o,2'o0})
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32'hFFFFFFD0: $displayh(dwb_dat_o);
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32'hFFFFFFD0: $displayh(dwb_dat_o);
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32'hFFFFFFC0: $write("%c",dwb_dat_o[31:24]);
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32'hFFFFFFC0: $write("%c",dwb_dat_o[31:24]);
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32'hFFFFFFE0: sys_int_i <= #1 !sys_int_i;
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32'hFFFFFFE0: sys_int_i <= #1 !sys_int_i;
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endcase // case ({dwb_adr_o,2'o0})
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endcase // case ({dwb_adr_o,2'o0})
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case (dwb_sel_o)
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case (dwb_sel_o)
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4'h1: ram[dwb_adr_o] <= {dwb_dat_t[31:8], dwb_dat_o[7:0]};
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4'h1: ram[dwb_adr_o] <= {dwb_dat_t[31:8], dwb_dat_o[7:0]};
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4'h2: ram[dwb_adr_o] <= {dwb_dat_t[31:16], dwb_dat_o[15:8], dwb_dat_t[7:0]};
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4'h2: ram[dwb_adr_o] <= {dwb_dat_t[31:16], dwb_dat_o[15:8], dwb_dat_t[7:0]};
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4'h4: ram[dwb_adr_o] <= {dwb_dat_t[31:24], dwb_dat_o[23:16], dwb_dat_t[15:0]};
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4'h4: ram[dwb_adr_o] <= {dwb_dat_t[31:24], dwb_dat_o[23:16], dwb_dat_t[15:0]};
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4'h8: ram[dwb_adr_o] <= {dwb_dat_o[31:24], dwb_dat_t[23:0]};
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4'h8: ram[dwb_adr_o] <= {dwb_dat_o[31:24], dwb_dat_t[23:0]};
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4'h3: ram[dwb_adr_o] <= {dwb_dat_t[31:16], dwb_dat_o[15:0]};
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4'h3: ram[dwb_adr_o] <= {dwb_dat_t[31:16], dwb_dat_o[15:0]};
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4'hC: ram[dwb_adr_o] <= {dwb_dat_o[31:16], dwb_dat_t[15:0]};
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4'hC: ram[dwb_adr_o] <= {dwb_dat_o[31:16], dwb_dat_t[15:0]};
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4'hF: ram[dwb_adr_o] <= {dwb_dat_o};
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4'hF: ram[dwb_adr_o] <= {dwb_dat_o};
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default: begin
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default: begin
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$displayh("\n*** INVALID WRITE ",{dwb_adr_o,2'o0}, " ***");
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//$displayh("\n*** INVALID WRITE ",{dwb_adr_o,2'o0}, " ***");
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//$finish;
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//$finish;
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end
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end
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endcase // case (dwb_sel_o)
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endcase // case (dwb_sel_o)
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end // if (dwb_wre_o & dwb_stb_o & dwb_ack_i)
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end // if (dwb_wre_o & dwb_stb_o & dwb_ack_i)
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if (dwb_stb_o & !dwb_wre_o & dwb_ack_i) begin
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if (dwb_stb_o & !dwb_wre_o & dwb_ack_i) begin
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case (dwb_sel_o)
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case (dwb_sel_o)
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4'h1,4'h2,4'h4,4'h8,4'h3,4'hC,4'hF: begin
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4'h1,4'h2,4'h4,4'h8,4'h3,4'hC,4'hF: begin
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end
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end
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default: begin
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default: begin
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$displayh("\n*** INVALID READ ",{dwb_adr_o,2'd0}, " ***");
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//$displayh("\n*** INVALID READ ",{dwb_adr_o,2'd0}, " ***");
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//$finish;
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//$finish;
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end
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end
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endcase // case (dwb_sel_o)
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endcase // case (dwb_sel_o)
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end
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end
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end // always @ (posedge sys_clk_i)
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end // always @ (posedge sys_clk_i)
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integer i;
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integer i;
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initial begin
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initial begin
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for (i=0;i<65535;i=i+1) begin
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for (i=0;i<65535;i=i+1) begin
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ram[i] <= $random;
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ram[i] <= $random;
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end
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end
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#1 $readmemh("dump.vmem",rom);
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#1 $readmemh("dump.vmem",rom);
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#1 $readmemh("dump.vmem",ram);
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#1 $readmemh("dump.vmem",ram);
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end
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end
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// DUMP CYCLES
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// DUMP CYCLES
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always @(posedge sys_clk_i)
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always @(posedge sys_clk_i)
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if (uut.dena) begin
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if (uut.dena) begin
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//begin
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//begin
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`ifdef AEMB2_SIM_KERNEL
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`ifdef AEMB2_SIM_KERNEL
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$displayh("TME=",($stime/10),
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$displayh("TME=",($stime/10),
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",PHA=",uut.gpha,
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",PHA=",uut.gpha,
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",IWB=",{uut.rpc_if,2'o0},
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",IWB=",{uut.rpc_if,2'o0},
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",ASM=",uut.ich_dat,
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",ASM=",uut.ich_dat,
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",OPA=",uut.opa_of,
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",OPA=",uut.opa_of,
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",OPB=",uut.opb_of,
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",OPB=",uut.opb_of,
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",OPD=",uut.opd_of,
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",OPD=",uut.opd_of,
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",MSR=",uut.msr_ex,
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",MSR=",uut.msr_ex,
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",MEM=",{uut.mem_ex,2'o0},
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",MEM=",{uut.mem_ex,2'o0},
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",BRA=",uut.bra_ex,
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",BRA=",uut.bra_ex,
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",BPC=",{uut.bpc_ex,2'o0},
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",BPC=",{uut.bpc_ex,2'o0},
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",MUX=",uut.mux_ex,
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",MUX=",uut.mux_ex,
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",ALU=",uut.alu_mx,
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",ALU=",uut.alu_mx,
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//",WRE=",dwb_wre_o,
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//",WRE=",dwb_wre_o,
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",SEL=",dwb_sel_o,
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",SEL=",dwb_sel_o,
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//",DWB=",dwb_dat_o,
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//",DWB=",dwb_dat_o,
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",REG=",uut.regs0.gprf0.wRW0,
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",REG=",uut.regs0.gprf0.wRW0,
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//",DAT=",uut.regs0.gprf0.regd,
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//",DAT=",uut.regs0.gprf0.regd,
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",MUL=",uut.mul_mx,
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",MUL=",uut.mul_mx,
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",BSF=",uut.bsf_mx,
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",BSF=",uut.bsf_mx,
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",DWB=",uut.dwb_mx,
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",DWB=",uut.dwb_mx,
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",LNK=",{uut.rpc_mx,2'o0},
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",LNK=",{uut.rpc_mx,2'o0},
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",SFR=",uut.sfr_mx,
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",SFR=",uut.sfr_mx,
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",E"
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",E"
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);
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);
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`endif
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`endif
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if (uut.ich_dat == 32'hB8000000) begin
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if (uut.ich_dat == 32'hB8000000) begin
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$displayh("\n*** EXIT ", $stime, " ***");
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$displayh("\n*** EXIT ", $stime, " ***");
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$finish;
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$finish;
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end
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end
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end // if (uut.dena)
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end // if (uut.dena)
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aeMB2_edk63
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aeMB2_edk63
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#(/*AUTOINSTPARAM*/
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#(/*AUTOINSTPARAM*/
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// Parameters
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// Parameters
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.AEMB_IWB (AEMB_IWB),
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.AEMB_IWB (AEMB_IWB),
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.AEMB_DWB (AEMB_DWB),
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.AEMB_DWB (AEMB_DWB),
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.AEMB_XWB (AEMB_XWB),
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.AEMB_XWB (AEMB_XWB),
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.AEMB_ICH (AEMB_ICH),
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.AEMB_ICH (AEMB_ICH),
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.AEMB_IDX (AEMB_IDX),
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.AEMB_IDX (AEMB_IDX),
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.AEMB_BSF (AEMB_BSF),
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.AEMB_BSF (AEMB_BSF),
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.AEMB_MUL (AEMB_MUL),
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.AEMB_MUL (AEMB_MUL),
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.AEMB_DIV (AEMB_DIV),
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.AEMB_DIV (AEMB_DIV),
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.AEMB_FPU (AEMB_FPU))
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.AEMB_FPU (AEMB_FPU))
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uut
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uut
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(/*AUTOINST*/
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(/*AUTOINST*/
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// Outputs
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// Outputs
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.dwb_adr_o (dwb_adr_o[AEMB_DWB-1:2]),
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.dwb_adr_o (dwb_adr_o[AEMB_DWB-1:2]),
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.dwb_cyc_o (dwb_cyc_o),
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.dwb_cyc_o (dwb_cyc_o),
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.dwb_dat_o (dwb_dat_o[31:0]),
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.dwb_dat_o (dwb_dat_o[31:0]),
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.dwb_sel_o (dwb_sel_o[3:0]),
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.dwb_sel_o (dwb_sel_o[3:0]),
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.dwb_stb_o (dwb_stb_o),
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.dwb_stb_o (dwb_stb_o),
|
.dwb_tag_o (dwb_tag_o),
|
.dwb_tag_o (dwb_tag_o),
|
.dwb_wre_o (dwb_wre_o),
|
.dwb_wre_o (dwb_wre_o),
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.iwb_adr_o (iwb_adr_o[AEMB_IWB-1:2]),
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.iwb_adr_o (iwb_adr_o[AEMB_IWB-1:2]),
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.iwb_cyc_o (iwb_cyc_o),
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.iwb_cyc_o (iwb_cyc_o),
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.iwb_sel_o (iwb_sel_o[3:0]),
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.iwb_sel_o (iwb_sel_o[3:0]),
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.iwb_stb_o (iwb_stb_o),
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.iwb_stb_o (iwb_stb_o),
|
.iwb_tag_o (iwb_tag_o),
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.iwb_tag_o (iwb_tag_o),
|
.iwb_wre_o (iwb_wre_o),
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.iwb_wre_o (iwb_wre_o),
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.xwb_adr_o (xwb_adr_o[AEMB_XWB-1:2]),
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.xwb_adr_o (xwb_adr_o[AEMB_XWB-1:2]),
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.xwb_cyc_o (xwb_cyc_o),
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.xwb_cyc_o (xwb_cyc_o),
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.xwb_dat_o (xwb_dat_o[31:0]),
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.xwb_dat_o (xwb_dat_o[31:0]),
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.xwb_sel_o (xwb_sel_o[3:0]),
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.xwb_sel_o (xwb_sel_o[3:0]),
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.xwb_stb_o (xwb_stb_o),
|
.xwb_stb_o (xwb_stb_o),
|
.xwb_tag_o (xwb_tag_o),
|
.xwb_tag_o (xwb_tag_o),
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.xwb_wre_o (xwb_wre_o),
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.xwb_wre_o (xwb_wre_o),
|
// Inputs
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// Inputs
|
.dwb_ack_i (dwb_ack_i),
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.dwb_ack_i (dwb_ack_i),
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.dwb_dat_i (dwb_dat_i[31:0]),
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.dwb_dat_i (dwb_dat_i[31:0]),
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.iwb_ack_i (iwb_ack_i),
|
.iwb_ack_i (iwb_ack_i),
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.iwb_dat_i (iwb_dat_i[31:0]),
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.iwb_dat_i (iwb_dat_i[31:0]),
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.sys_clk_i (sys_clk_i),
|
.sys_clk_i (sys_clk_i),
|
.sys_ena_i (sys_ena_i),
|
.sys_ena_i (sys_ena_i),
|
.sys_int_i (sys_int_i),
|
.sys_int_i (sys_int_i),
|
.sys_rst_i (sys_rst_i),
|
.sys_rst_i (sys_rst_i),
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.xwb_ack_i (xwb_ack_i),
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.xwb_ack_i (xwb_ack_i),
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.xwb_dat_i (xwb_dat_i[31:0]));
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.xwb_dat_i (xwb_dat_i[31:0]));
|
|
|
endmodule // edk62
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endmodule // edk62
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|
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// Local Variables:
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// Local Variables:
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// verilog-library-directories:("." "../../rtl/verilog/")
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// verilog-library-directories:("." "../../rtl/verilog/")
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// verilog-library-files:("")
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// verilog-library-files:("")
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// End:
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// End:
|
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|
