--*************************************************************************
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--*************************************************************************
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-- Project : AES128 *
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-- Project : AES128 *
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-- *
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-- *
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-- Block Name : key_expander.vhd *
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-- Block Name : key_expander.vhd *
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-- *
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-- *
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-- Author : Hemanth Satyanarayana *
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-- Author : Hemanth Satyanarayana *
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-- *
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-- *
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-- Email : hemanth@opencores.org *
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-- Email : hemanth@opencores.org *
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-- *
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-- *
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-- Description: This block implements the key expnasion algorithm *
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-- Description: This block implements the key expnasion algorithm *
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-- to generate different keys for each of 10 rounds. *
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-- to generate different keys for each of 10 rounds. *
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-- . *
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-- . *
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-- *
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-- *
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-- Revision History *
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-- Revision History *
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-- |-----------|-------------|---------|---------------------------------|*
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-- |-----------|-------------|---------|---------------------------------|*
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-- | Name | Date | Version | Revision details |*
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-- | Name | Date | Version | Revision details |*
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-- |-----------|-------------|---------|---------------------------------|*
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-- |-----------|-------------|---------|---------------------------------|*
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-- | Hemanth | 15-Dec-2004 | 1.1.1.1 | Uploaded |*
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-- | Hemanth | 15-Dec-2004 | 1.1.1.1 | Uploaded |*
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-- |-----------|-------------|---------|---------------------------------|*
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-- |-----------|-------------|---------|---------------------------------|*
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-- *
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-- *
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-- Refer FIPS-197 document for details *
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-- Refer FIPS-197 document for details *
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--*************************************************************************
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--*************************************************************************
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-- *
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-- *
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-- Copyright (C) 2004 Author *
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-- Copyright (C) 2004 Author *
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-- *
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-- *
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-- This source file may be used and distributed without *
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-- This source file may be used and distributed without *
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-- restriction provided that this copyright statement is not *
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-- restriction provided that this copyright statement is not *
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-- removed from the file and that any derivative work contains *
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-- removed from the file and that any derivative work contains *
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-- the original copyright notice and the associated disclaimer. *
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-- the original copyright notice and the associated disclaimer. *
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-- *
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-- *
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-- This source file is free software; you can redistribute it *
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-- This source file is free software; you can redistribute it *
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-- and/or modify it under the terms of the GNU Lesser General *
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-- and/or modify it under the terms of the GNU Lesser General *
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-- Public License as published by the Free Software Foundation; *
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-- Public License as published by the Free Software Foundation; *
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-- either version 2.1 of the License, or (at your option) any *
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-- either version 2.1 of the License, or (at your option) any *
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-- later version. *
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-- later version. *
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-- *
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-- *
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-- This source is distributed in the hope that it will be *
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-- This source is distributed in the hope that it will be *
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-- useful, but WITHOUT ANY WARRANTY; without even the implied *
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-- useful, but WITHOUT ANY WARRANTY; without even the implied *
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-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR *
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-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR *
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-- PURPOSE. See the GNU Lesser General Public License for more *
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-- PURPOSE. See the GNU Lesser General Public License for more *
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-- details. *
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-- details. *
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-- *
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-- *
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-- You should have received a copy of the GNU Lesser General *
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-- You should have received a copy of the GNU Lesser General *
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-- Public License along with this source; if not, download it *
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-- Public License along with this source; if not, download it *
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-- from http://www.opencores.org/lgpl.shtml *
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-- from http://www.opencores.org/lgpl.shtml *
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-- *
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-- *
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--*************************************************************************
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--*************************************************************************
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use work.aes_package.all;
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use work.aes_package.all;
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entity key_expander is
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entity key_expander is
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port(
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port(
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clk : in std_logic;
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clk : in std_logic;
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reset : in std_logic;
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reset : in std_logic;
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key_in_c0: in state_array_type; -- given input keys
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key_in_c0: in state_array_type; -- given input keys
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key_in_c1: in state_array_type; -- given input keys
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key_in_c1: in state_array_type; -- given input keys
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key_in_c2: in state_array_type; -- given input keys
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key_in_c2: in state_array_type; -- given input keys
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key_in_c3: in state_array_type; -- given input keys
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key_in_c3: in state_array_type; -- given input keys
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count : in integer; -- to synchronise with input transformation rounds
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count : in integer; -- to synchronise with input transformation rounds
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mode : in std_logic; -- high=encrypt, low=decrypt
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mode : in std_logic; -- high=encrypt, low=decrypt
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keyout_c0: out state_array_type;-- output key value for each round
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keyout_c0: out state_array_type;-- output key value for each round
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keyout_c1: out state_array_type;-- output key value for each round
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keyout_c1: out state_array_type;-- output key value for each round
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keyout_c2: out state_array_type;-- output key value for each round
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keyout_c2: out state_array_type;-- output key value for each round
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keyout_c3: out state_array_type -- output key value for each round
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keyout_c3: out state_array_type -- output key value for each round
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);
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);
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end key_expander;
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end key_expander;
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architecture expansion of key_expander is
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architecture expansion of key_expander is
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signal X0 : state_array_type;
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signal X0 : state_array_type;
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signal X1 : state_array_type;
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signal X1 : state_array_type;
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signal X2 : state_array_type;
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signal X2 : state_array_type;
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signal X3 : state_array_type;
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signal X3 : state_array_type;
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signal w_i_nk0 : state_array_type;
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signal w_i_nk0 : state_array_type;
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signal w_i_nk1 : state_array_type;
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signal w_i_nk1 : state_array_type;
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signal w_i_nk2 : state_array_type;
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signal w_i_nk2 : state_array_type;
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signal w_i_nk3 : state_array_type;
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signal w_i_nk3 : state_array_type;
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signal temp0 : state_array_type;
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signal temp0 : state_array_type;
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signal k_rot : state_array_type;
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signal k_rot : state_array_type;
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signal key_sub : state_array_type;
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signal key_sub : state_array_type;
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signal key_xor_rcon: state_array_type;
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signal key_xor_rcon: state_array_type;
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signal rcon: std_logic_vector(7 downto 0);
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signal rcon: std_logic_vector(7 downto 0);
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begin
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begin
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-- transformation of keys
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-- transformation of keys
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process(mode,rcon,temp0,k_rot,key_sub,key_xor_rcon,X0,X1,X2,X3,w_i_nk0,w_i_nk1,w_i_nk2,w_i_nk3)
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process(mode,rcon,temp0,k_rot,key_sub,key_xor_rcon,X0,X1,X2,X3,w_i_nk0,w_i_nk1,w_i_nk2,w_i_nk3)
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begin
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begin
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if(mode = '1') then -- if encrypt
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if(mode = '1') then -- if encrypt
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k_rot <= (temp0(1),temp0(2),temp0(3),temp0(0)); -- ROTATE word
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k_rot <= (temp0(1),temp0(2),temp0(3),temp0(0)); -- ROTATE word
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-- SUB word
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-- SUB word
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key_sub(0) <= sbox_val(k_rot(0));
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key_sub(0) <= sbox_val(k_rot(0));
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key_sub(1) <= sbox_val(k_rot(1));
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key_sub(1) <= sbox_val(k_rot(1));
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key_sub(2) <= sbox_val(k_rot(2));
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key_sub(2) <= sbox_val(k_rot(2));
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key_sub(3) <= sbox_val(k_rot(3));
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key_sub(3) <= sbox_val(k_rot(3));
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-- XOR with rcon
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-- XOR with rcon
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key_xor_rcon <= ((key_sub(0) xor rcon),key_sub(1),key_sub(2),key_sub(3));
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key_xor_rcon <= ((key_sub(0) xor rcon),key_sub(1),key_sub(2),key_sub(3));
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-- XOR with Wi's
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-- XOR with Wi's
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X0 <= ( key_xor_rcon(0) xor w_i_nk0(0) ,key_xor_rcon(1) xor w_i_nk0(1),key_xor_rcon(2) xor w_i_nk0(2),key_xor_rcon(3) xor w_i_nk0(3));
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X0 <= ( key_xor_rcon(0) xor w_i_nk0(0) ,key_xor_rcon(1) xor w_i_nk0(1),key_xor_rcon(2) xor w_i_nk0(2),key_xor_rcon(3) xor w_i_nk0(3));
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X1 <= ((X0(0) xor w_i_nk1(0)) , (X0(1) xor w_i_nk1(1)) , (X0(2) xor w_i_nk1(2)) , (X0(3) xor w_i_nk1(3)));
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X1 <= ((X0(0) xor w_i_nk1(0)) , (X0(1) xor w_i_nk1(1)) , (X0(2) xor w_i_nk1(2)) , (X0(3) xor w_i_nk1(3)));
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X2 <= ((X1(0) xor w_i_nk2(0)) , (X1(1) xor w_i_nk2(1)) , (X1(2) xor w_i_nk2(2)) , (X1(3) xor w_i_nk2(3)));
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X2 <= ((X1(0) xor w_i_nk2(0)) , (X1(1) xor w_i_nk2(1)) , (X1(2) xor w_i_nk2(2)) , (X1(3) xor w_i_nk2(3)));
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X3 <= ((X2(0) xor w_i_nk3(0)) , (X2(1) xor w_i_nk3(1)) , (X2(2) xor w_i_nk3(2)) , (X2(3) xor w_i_nk3(3)));
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X3 <= ((X2(0) xor w_i_nk3(0)) , (X2(1) xor w_i_nk3(1)) , (X2(2) xor w_i_nk3(2)) , (X2(3) xor w_i_nk3(3)));
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else -- if decrypt
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else -- if decrypt
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X3 <= (w_i_nk3(0) xor w_i_nk2(0) , w_i_nk3(1) xor w_i_nk2(1) , w_i_nk3(2) xor w_i_nk2(2) , w_i_nk3(3) xor w_i_nk2(3));
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X3 <= (w_i_nk3(0) xor w_i_nk2(0) , w_i_nk3(1) xor w_i_nk2(1) , w_i_nk3(2) xor w_i_nk2(2) , w_i_nk3(3) xor w_i_nk2(3));
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X2 <= (w_i_nk2(0) xor w_i_nk1(0) , w_i_nk2(1) xor w_i_nk1(1) , w_i_nk2(2) xor w_i_nk1(2) , w_i_nk2(3) xor w_i_nk1(3));
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X2 <= (w_i_nk2(0) xor w_i_nk1(0) , w_i_nk2(1) xor w_i_nk1(1) , w_i_nk2(2) xor w_i_nk1(2) , w_i_nk2(3) xor w_i_nk1(3));
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X1 <= (w_i_nk1(0) xor w_i_nk0(0) , w_i_nk1(1) xor w_i_nk0(1) , w_i_nk1(2) xor w_i_nk0(2) , w_i_nk1(3) xor w_i_nk0(3));
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X1 <= (w_i_nk1(0) xor w_i_nk0(0) , w_i_nk1(1) xor w_i_nk0(1) , w_i_nk1(2) xor w_i_nk0(2) , w_i_nk1(3) xor w_i_nk0(3));
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X0 <= ( key_xor_rcon(0) xor w_i_nk0(0) ,key_xor_rcon(1) xor w_i_nk0(1),key_xor_rcon(2) xor w_i_nk0(2),key_xor_rcon(3) xor w_i_nk0(3));
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X0 <= ( key_xor_rcon(0) xor w_i_nk0(0) ,key_xor_rcon(1) xor w_i_nk0(1),key_xor_rcon(2) xor w_i_nk0(2),key_xor_rcon(3) xor w_i_nk0(3));
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k_rot <= (X3(1),X3(2),X3(3),X3(0));
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k_rot <= (X3(1),X3(2),X3(3),X3(0));
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key_sub(0) <= sbox_val(k_rot(0));
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key_sub(0) <= sbox_val(k_rot(0));
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key_sub(1) <= sbox_val(k_rot(1));
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key_sub(1) <= sbox_val(k_rot(1));
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key_sub(2) <= sbox_val(k_rot(2));
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key_sub(2) <= sbox_val(k_rot(2));
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key_sub(3) <= sbox_val(k_rot(3));
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key_sub(3) <= sbox_val(k_rot(3));
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key_xor_rcon <= ((key_sub(0) xor rcon),key_sub(1),key_sub(2),key_sub(3));
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key_xor_rcon <= ((key_sub(0) xor rcon),key_sub(1),key_sub(2),key_sub(3));
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end if;
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end if;
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end process;
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end process;
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-- registering key outputs for each round and generating rcon values for each round
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-- registering key outputs for each round and generating rcon values for each round
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process(clk,reset)
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process(clk,reset)
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begin
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begin
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if(reset = '1') then
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if(reset = '1') then
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temp0 <= (others =>(others => '0'));
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temp0 <= (others =>(others => '0'));
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w_i_nk0 <= (others =>(others => '0'));
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w_i_nk0 <= (others =>(others => '0'));
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w_i_nk1 <= (others =>(others => '0'));
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w_i_nk1 <= (others =>(others => '0'));
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w_i_nk2 <= (others =>(others => '0'));
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w_i_nk2 <= (others =>(others => '0'));
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w_i_nk3 <= (others =>(others => '0'));
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w_i_nk3 <= (others =>(others => '0'));
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rcon <= (others => '0');
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rcon <= (others => '0');
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elsif clk'event and clk = '1' then
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elsif clk'event and clk = '1' then
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if(count = 0) then
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if(count = 0) then
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temp0 <= key_in_c3;
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temp0 <= key_in_c3;
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w_i_nk0 <= key_in_c0;
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w_i_nk0 <= key_in_c0;
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w_i_nk1 <= key_in_c1;
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w_i_nk1 <= key_in_c1;
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w_i_nk2 <= key_in_c2;
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w_i_nk2 <= key_in_c2;
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w_i_nk3 <= key_in_c3;
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w_i_nk3 <= key_in_c3;
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else
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else
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temp0 <= X3;
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temp0 <= X3;
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w_i_nk0 <= X0;
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w_i_nk0 <= X0;
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w_i_nk1 <= X1;
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w_i_nk1 <= X1;
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w_i_nk2 <= X2;
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w_i_nk2 <= X2;
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w_i_nk3 <= X3;
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w_i_nk3 <= X3;
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end if;
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end if;
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if(mode = '1') then
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if(mode = '1') then
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case count is
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case count is
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when 0 => rcon <= "00000001";
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when 0 => rcon <= "00000001";
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when 1 => rcon <= "00000010";
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when 1 => rcon <= "00000010";
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when 2 => rcon <= "00000100";
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when 2 => rcon <= "00000100";
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when 3 => rcon <= "00001000";
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when 3 => rcon <= "00001000";
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when 4 => rcon <= "00010000";
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when 4 => rcon <= "00010000";
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when 5 => rcon <= "00100000";
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when 5 => rcon <= "00100000";
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when 6 => rcon <= "01000000";
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when 6 => rcon <= "01000000";
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when 7 => rcon <= "10000000";
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when 7 => rcon <= "10000000";
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when 8 => rcon <= "00011011";
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when 8 => rcon <= "00011011";
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when 9 => rcon <= "00110110";
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when 9 => rcon <= "00110110";
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when others => rcon <= "00000000";
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when others => rcon <= "00000000";
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end case;
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end case;
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else------------------------->>>>>>>>>>>>>>
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else------------------------->>>>>>>>>>>>>>
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case count is
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case count is
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when 0 => rcon <= "00110110";
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when 0 => rcon <= "00110110";
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when 1 => rcon <= "00011011";
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when 1 => rcon <= "00011011";
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when 2 => rcon <= "10000000";
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when 2 => rcon <= "10000000";
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when 3 => rcon <= "01000000";
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when 3 => rcon <= "01000000";
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when 4 => rcon <= "00100000";
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when 4 => rcon <= "00100000";
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when 5 => rcon <= "00010000";
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when 5 => rcon <= "00010000";
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when 6 => rcon <= "00001000";
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when 6 => rcon <= "00001000";
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when 7 => rcon <= "00000100";
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when 7 => rcon <= "00000100";
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when 8 => rcon <= "00000010";
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when 8 => rcon <= "00000010";
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when 9 => rcon <= "00000001";
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when 9 => rcon <= "00000001";
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when others => rcon <= "00000000";
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when others => rcon <= "00000000";
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end case;
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end case;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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keyout_c0 <= X0;
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keyout_c0 <= X0;
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keyout_c1 <= X1;
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keyout_c1 <= X1;
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keyout_c2 <= X2;
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keyout_c2 <= X2;
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keyout_c3 <= X3;
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keyout_c3 <= X3;
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end expansion;
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end expansion;
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