//////////////////////////////////////////////////////////////////////
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//---------------------------------------------------------------------------------------
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//// ////
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//
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//// AES top file ////
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// AES core top module
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//// ////
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//
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//// Description: ////
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// Description:
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//// AES top ////
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// AES core top module with direct interface to key and data buses.
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//// ////
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//
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//// To Do: ////
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// To Do:
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//// - done ////
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// - done
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//// ////
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//
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//// Author(s): ////
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// Author(s):
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//// - Luo Dongjun, dongjun_luo@hotmail.com ////
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// - Luo Dongjun, dongjun_luo@hotmail.com
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//// ////
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//
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//////////////////////////////////////////////////////////////////////
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//---------------------------------------------------------------------------------------
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// uncomment the following define to enable use of distributed RAM implementation
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// uncomment the following define to enable use of distributed RAM implementation
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// for XILINX FPGAs instead of block memory.
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// for XILINX FPGAs instead of block memory.
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// NOTE: when commenting the following define, core size is slightly smaller but maximum
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// achievable clock frequency is also slightly lower.
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`define XILINX 1
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`define XILINX 1
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module aes (
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module aes (
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clk,
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clk, reset,
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reset,
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i_start, i_enable,
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i_start,
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i_ende, i_key,
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i_enable,
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i_key_mode, i_data,
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i_ende,
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i_data_valid, o_ready,
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i_key,
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o_data, o_data_valid,
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i_key_mode,
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i_data,
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i_data_valid,
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o_ready,
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o_data,
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o_data_valid,
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o_key_ready
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o_key_ready
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);
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);
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input clk;
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//---------------------------------------------------------------------------------------
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input reset;
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// module interfaces
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input i_start;
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input clk; // core global clock
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input i_enable;
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input reset; // core global async reset control
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input [1:0] i_key_mode; // 0: 128; 1: 192; 2: 256
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input i_start; // key expansion start pulse
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input i_enable; // enable encryption / decryption core operation
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input [1:0] i_key_mode; // key length: 0 => 128; 1 => 192; 2 => 256
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input [255:0] i_key; // if key size is 128/192, upper bits are the inputs
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input [255:0] i_key; // if key size is 128/192, upper bits are the inputs
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input [127:0] i_data;
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input [127:0] i_data; // plain/cipher text data input
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input i_data_valid;
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input i_data_valid; // data input valid
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input i_ende; // 0: encryption; 1: decryption
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input i_ende; // core mode of operation: 0 => encryption; 1 => decryption
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output o_ready; // user shall not input data if IP is not ready
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output o_ready; // indicates core is ready for new input data at the next clock cycle
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output [127:0] o_data; // output data
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output [127:0] o_data; // data output
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output o_data_valid;
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output o_data_valid; // data output valid
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output o_key_ready; // key expansion procedure completes
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output o_key_ready; // key expansion procedure done
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//---------------------------------------------------------------------------------------
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// module registers and signals
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genvar i;
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genvar i;
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wire final_round;
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wire final_round;
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reg [3:0] max_round;
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reg [3:0] max_round;
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wire [127:0] en_sb_data,de_sb_data,sr_data,mc_data,imc_data,ark_data;
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wire [127:0] en_sb_data,de_sb_data,sr_data,mc_data,imc_data,ark_data;
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reg [127:0] sb_data,o_data,i_data_L;
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reg [127:0] sb_data,o_data,i_data_L;
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reg i_data_valid_L;
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reg i_data_valid_L;
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reg round_valid;
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reg round_valid;
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reg [2:0] sb_valid;
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reg [2:0] sb_valid;
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reg o_data_valid;
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reg o_data_valid;
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reg [3:0] round_cnt,sb_round_cnt1,sb_round_cnt2,sb_round_cnt3;
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reg [3:0] round_cnt,sb_round_cnt1,sb_round_cnt2,sb_round_cnt3;
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wire [127:0] round_key;
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wire [127:0] round_key;
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wire [63:0] rd_data0,rd_data1;
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wire [63:0] rd_data0,rd_data1;
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wire wr;
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wire wr;
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wire [4:0] wr_addr;
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wire [4:0] wr_addr;
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wire [63:0] wr_data;
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wire [63:0] wr_data;
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wire [127:0] imc_round_key,en_ark_data,de_ark_data,ark_data_final,ark_data_init;
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wire [127:0] imc_round_key,en_ark_data,de_ark_data,ark_data_final,ark_data_init;
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//---------------------------------------------------------------------------------------
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// module implementation
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assign final_round = sb_round_cnt3[3:0] == max_round[3:0];
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assign final_round = sb_round_cnt3[3:0] == max_round[3:0];
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//assign o_ready = ~sb_valid[1]; // if ready is asserted, user can input data for the same cycle
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//assign o_ready = ~sb_valid[1]; // if ready is asserted, user can input data for the same cycle
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assign o_ready = ~sb_valid[0]; // if ready is asserted, user can input data for the next cycle
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assign o_ready = ~sb_valid[0]; // if ready is asserted, user can input data for the next cycle
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// round count is Nr - 1
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// round count is Nr - 1
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always @ (*)
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always @ (*)
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begin
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begin
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case (i_key_mode)
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case (i_key_mode)
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2'b00: max_round[3:0] = 4'd10;
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2'b00: max_round[3:0] = 4'd10;
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2'b01: max_round[3:0] = 4'd12;
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2'b01: max_round[3:0] = 4'd12;
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default: max_round[3:0] = 4'd14;
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default: max_round[3:0] = 4'd14;
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endcase
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endcase
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end
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end
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/*****************************************************************************/
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//---------------------------------------------------------------------------------------
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// Sub Bytes
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// Sub Bytes
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//
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//
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//
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//
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generate
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generate
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for (i=0;i<16;i=i+1)
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for (i=0;i<16;i=i+1)
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begin : sbox_block
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begin : sbox_block
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sbox u_sbox (
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sbox u_sbox (
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.clk(clk),
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.clk(clk),
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.reset(reset),
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.reset(reset),
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.enable(i_enable),
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.enable(i_enable),
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.ende(i_ende),
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.ende(i_ende),
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.din(o_data[i*8+7:i*8]),
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.din(o_data[i*8+7:i*8]),
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.en_dout(en_sb_data[i*8+7:i*8]),
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.en_dout(en_sb_data[i*8+7:i*8]),
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.de_dout(de_sb_data[i*8+7:i*8])
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.de_dout(de_sb_data[i*8+7:i*8])
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);
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);
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end
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end
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endgenerate
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endgenerate
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always @ (posedge clk or posedge reset)
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always @ (posedge clk or posedge reset)
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begin
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begin
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if (reset)
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if (reset)
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sb_data[127:0] <= 128'b0;
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sb_data[127:0] <= 128'b0;
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else if (i_enable)
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else if (i_enable)
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sb_data[127:0] <= i_ende ? de_sb_data[127:0] : en_sb_data[127:0];
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sb_data[127:0] <= i_ende ? de_sb_data[127:0] : en_sb_data[127:0];
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end
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end
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/*****************************************************************************/
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//---------------------------------------------------------------------------------------
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// Shift Rows
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// Shift Rows
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//
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//
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//
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//
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wire [127:0] shrows, ishrows;
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wire [127:0] shrows, ishrows;
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shift_rows u_shrows (.si(sb_data[127:0]), .so(shrows));
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shift_rows u_shrows (.si(sb_data[127:0]), .so(shrows));
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inv_shift_rows u_ishrows (.si(sb_data[127:0]), .so(ishrows));
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inv_shift_rows u_ishrows (.si(sb_data[127:0]), .so(ishrows));
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assign sr_data[127:0] = i_ende ? ishrows : shrows;
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assign sr_data[127:0] = i_ende ? ishrows : shrows;
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/*****************************************************************************/
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//---------------------------------------------------------------------------------------
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// Mix Columns
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// Mix Columns
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//
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//
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//
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//
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mix_columns mxc_u (.in(sr_data), .out(mc_data));
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mix_columns mxc_u (.in(sr_data), .out(mc_data));
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always @ (posedge clk or posedge reset)
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always @ (posedge clk or posedge reset)
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begin
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begin
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if (reset)
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if (reset)
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begin
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begin
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i_data_valid_L <= 1'b0;
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i_data_valid_L <= 1'b0;
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i_data_L[127:0] <= 128'b0;
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i_data_L[127:0] <= 128'b0;
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end
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end
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else
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else
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begin
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begin
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i_data_valid_L <= i_data_valid;
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i_data_valid_L <= i_data_valid;
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i_data_L[127:0] <=i_data[127:0];
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i_data_L[127:0] <=i_data[127:0];
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end
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end
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end
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end
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/*****************************************************************************/
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//---------------------------------------------------------------------------------------
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// Inverse Mix Columns
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// Inverse Mix Columns
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//
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//
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//
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//
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inv_mix_columns imxc_u (.in(sr_data), .out(imc_data));
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inv_mix_columns imxc_u (.in(sr_data), .out(imc_data));
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/*****************************************************************************/
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//---------------------------------------------------------------------------------------
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// add round key for decryption
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// add round key for decryption
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//
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//
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inv_mix_columns imxk_u (.in(round_key), .out(imc_round_key));
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inv_mix_columns imxk_u (.in(round_key), .out(imc_round_key));
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assign ark_data_final[127:0] = sr_data[127:0] ^ round_key[127:0];
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assign ark_data_final[127:0] = sr_data[127:0] ^ round_key[127:0];
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assign ark_data_init[127:0] = i_data_L[127:0] ^ round_key[127:0];
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assign ark_data_init[127:0] = i_data_L[127:0] ^ round_key[127:0];
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assign en_ark_data[127:0] = mc_data[127:0] ^ round_key[127:0];
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assign en_ark_data[127:0] = mc_data[127:0] ^ round_key[127:0];
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assign de_ark_data[127:0] = imc_data[127:0] ^ imc_round_key[127:0];
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assign de_ark_data[127:0] = imc_data[127:0] ^ imc_round_key[127:0];
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assign ark_data[127:0] = i_data_valid_L ? ark_data_init[127:0] :
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assign ark_data[127:0] = i_data_valid_L ? ark_data_init[127:0] :
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(final_round ? ark_data_final[127:0] :
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(final_round ? ark_data_final[127:0] :
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(i_ende ? de_ark_data[127:0] : en_ark_data[127:0]));
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(i_ende ? de_ark_data[127:0] : en_ark_data[127:0]));
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/*****************************************************************************/
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//---------------------------------------------------------------------------------------
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// Data outputs after each round
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// Data outputs after each round
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//
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//
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always @ (posedge clk or posedge reset)
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always @ (posedge clk or posedge reset)
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begin
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begin
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if (reset)
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if (reset)
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o_data[127:0] <= 128'b0;
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o_data[127:0] <= 128'b0;
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else if (i_enable && (i_data_valid_L || sb_valid[2]))
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else if (i_enable && (i_data_valid_L || sb_valid[2]))
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o_data[127:0] <= ark_data[127:0];
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o_data[127:0] <= ark_data[127:0];
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end
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end
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/*****************************************************************************/
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//---------------------------------------------------------------------------------------
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// in sbox, we have 3 stages (sb_valid),
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// in sbox, we have 3 stages (sb_valid),
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// before the end of each round, we have another stage (round_valid)
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// before the end of each round, we have another stage (round_valid)
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//
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//
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always @ (posedge clk or posedge reset)
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always @ (posedge clk or posedge reset)
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begin
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begin
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if (reset)
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if (reset)
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begin
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begin
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round_valid <= 1'b0;
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round_valid <= 1'b0;
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sb_valid[2:0] <= 3'b0;
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sb_valid[2:0] <= 3'b0;
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o_data_valid <= 1'b0;
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o_data_valid <= 1'b0;
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end
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end
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else if (i_enable)
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else if (i_enable)
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begin
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begin
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o_data_valid <= sb_valid[2] && final_round;
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o_data_valid <= sb_valid[2] && final_round;
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round_valid <= (sb_valid[2] && !final_round) || i_data_valid_L;
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round_valid <= (sb_valid[2] && !final_round) || i_data_valid_L;
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sb_valid[2:0] <= {sb_valid[1:0],round_valid};
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sb_valid[2:0] <= {sb_valid[1:0],round_valid};
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end
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end
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end
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end
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always @ (posedge clk or posedge reset)
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always @ (posedge clk or posedge reset)
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begin
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begin
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if (reset) round_cnt[3:0] <= 4'd0;
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if (reset) round_cnt[3:0] <= 4'd0;
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else if (i_data_valid_L) round_cnt[3:0] <= 4'd1;
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else if (i_data_valid_L) round_cnt[3:0] <= 4'd1;
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else if (i_enable && sb_valid[2]) round_cnt[3:0] <= sb_round_cnt3[3:0] + 1'b1;
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else if (i_enable && sb_valid[2]) round_cnt[3:0] <= sb_round_cnt3[3:0] + 1'b1;
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end
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end
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always @ (posedge clk or posedge reset)
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always @ (posedge clk or posedge reset)
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begin
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begin
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if (reset)
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if (reset)
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begin
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begin
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sb_round_cnt1[3:0] <= 4'd0;
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sb_round_cnt1[3:0] <= 4'd0;
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sb_round_cnt2[3:0] <= 4'd0;
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sb_round_cnt2[3:0] <= 4'd0;
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sb_round_cnt3[3:0] <= 4'd0;
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sb_round_cnt3[3:0] <= 4'd0;
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end
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end
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else if (i_enable)
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else if (i_enable)
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begin
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begin
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if (round_valid) sb_round_cnt1[3:0] <= round_cnt[3:0];
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if (round_valid) sb_round_cnt1[3:0] <= round_cnt[3:0];
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if (sb_valid[0]) sb_round_cnt2[3:0] <= sb_round_cnt1[3:0];
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if (sb_valid[0]) sb_round_cnt2[3:0] <= sb_round_cnt1[3:0];
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if (sb_valid[1]) sb_round_cnt3[3:0] <= sb_round_cnt2[3:0];
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if (sb_valid[1]) sb_round_cnt3[3:0] <= sb_round_cnt2[3:0];
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end
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end
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end
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end
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/*****************************************************************************/
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//---------------------------------------------------------------------------------------
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// round key generation: the expansion keys are stored in 4 16*32 rams or
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// round key generation: the expansion keys are stored in 4 16*32 rams or
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// 2 16*64 rams or 1 16*128 rams
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// 2 16*64 rams or 1 16*128 rams
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//
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//
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//assign rd_addr[3:0] = i_ende ? (max_round[3:0] - sb_round_cnt2[3:0]) : sb_round_cnt2[3:0];
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//assign rd_addr[3:0] = i_ende ? (max_round[3:0] - sb_round_cnt2[3:0]) : sb_round_cnt2[3:0];
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|
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assign round_key[127:0] = {rd_data0[63:0],rd_data1[63:0]};
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assign round_key[127:0] = {rd_data0[63:0],rd_data1[63:0]};
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`ifdef XILINX
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`ifdef XILINX
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reg [3:0] rd_addr;
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reg [3:0] rd_addr;
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|
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always @ (posedge clk or posedge reset)
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always @ (posedge clk or posedge reset)
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begin
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begin
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if (reset)
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if (reset)
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rd_addr <= 4'b0;
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rd_addr <= 4'b0;
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else if (sb_valid[1] | i_data_valid)
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else if (sb_valid[1] | i_data_valid)
|
begin
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begin
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if (i_ende)
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if (i_ende)
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begin
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begin
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if (i_data_valid)
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if (i_data_valid)
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rd_addr <= max_round[3:0];
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rd_addr <= max_round[3:0];
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else
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else
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rd_addr <= max_round[3:0] - sb_round_cnt2[3:0];
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rd_addr <= max_round[3:0] - sb_round_cnt2[3:0];
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end
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end
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else
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else
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begin
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begin
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if (i_data_valid)
|
if (i_data_valid)
|
rd_addr <= 4'b0;
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rd_addr <= 4'b0;
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else
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else
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rd_addr <= sb_round_cnt2[3:0];
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rd_addr <= sb_round_cnt2[3:0];
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end
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end
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end
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end
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end
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end
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|
|
xram_16x64 u_ram_0
|
xram_16x64 u_ram_0
|
(
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(
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.clk(clk),
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.clk(clk),
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.wr(wr & ~wr_addr[0]),
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.wr(wr & ~wr_addr[0]),
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.wr_addr(wr_addr[4:1]),
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.wr_addr(wr_addr[4:1]),
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.wr_data(wr_data[63:0]),
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.wr_data(wr_data[63:0]),
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.rd_addr(rd_addr[3:0]),
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.rd_addr(rd_addr[3:0]),
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.rd_data(rd_data0[63:0])
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.rd_data(rd_data0[63:0])
|
);
|
);
|
xram_16x64 u_ram_1
|
xram_16x64 u_ram_1
|
(
|
(
|
.clk(clk),
|
.clk(clk),
|
.wr(wr & wr_addr[0]),
|
.wr(wr & wr_addr[0]),
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.wr_addr(wr_addr[4:1]),
|
.wr_addr(wr_addr[4:1]),
|
.wr_data(wr_data[63:0]),
|
.wr_data(wr_data[63:0]),
|
.rd_addr(rd_addr[3:0]),
|
.rd_addr(rd_addr[3:0]),
|
.rd_data(rd_data1[63:0])
|
.rd_data(rd_data1[63:0])
|
);
|
);
|
`else
|
`else
|
wire [3:0] rd_addr;
|
wire [3:0] rd_addr;
|
|
|
assign rd_addr[3:0] = i_ende ? (i_data_valid ? max_round[3:0] : (max_round[3:0] - sb_round_cnt2[3:0])) :
|
assign rd_addr[3:0] = i_ende ? (i_data_valid ? max_round[3:0] : (max_round[3:0] - sb_round_cnt2[3:0])) :
|
(i_data_valid ? 4'b0 : sb_round_cnt2[3:0]);
|
(i_data_valid ? 4'b0 : sb_round_cnt2[3:0]);
|
|
|
ram_16x64 u_ram_0
|
ram_16x64 u_ram_0
|
(
|
(
|
.clk(clk),
|
.clk(clk),
|
.wr(wr & ~wr_addr[0]),
|
.wr(wr & ~wr_addr[0]),
|
.wr_addr(wr_addr[4:1]),
|
.wr_addr(wr_addr[4:1]),
|
.wr_data(wr_data[63:0]),
|
.wr_data(wr_data[63:0]),
|
.rd_addr(rd_addr[3:0]),
|
.rd_addr(rd_addr[3:0]),
|
.rd_data(rd_data0[63:0]),
|
.rd_data(rd_data0[63:0]),
|
.rd(sb_valid[1] | i_data_valid)
|
.rd(sb_valid[1] | i_data_valid)
|
);
|
);
|
ram_16x64 u_ram_1
|
ram_16x64 u_ram_1
|
(
|
(
|
.clk(clk),
|
.clk(clk),
|
.wr(wr & wr_addr[0]),
|
.wr(wr & wr_addr[0]),
|
.wr_addr(wr_addr[4:1]),
|
.wr_addr(wr_addr[4:1]),
|
.wr_data(wr_data[63:0]),
|
.wr_data(wr_data[63:0]),
|
.rd_addr(rd_addr[3:0]),
|
.rd_addr(rd_addr[3:0]),
|
.rd_data(rd_data1[63:0]),
|
.rd_data(rd_data1[63:0]),
|
.rd(sb_valid[1] | i_data_valid)
|
.rd(sb_valid[1] | i_data_valid)
|
);
|
);
|
`endif
|
`endif
|
/*****************************************************************************/
|
//---------------------------------------------------------------------------------------
|
// Key Expansion module
|
// Key Expansion module
|
//
|
//
|
//
|
//
|
key_exp u_key_exp (
|
key_exp u_key_exp (
|
.clk(clk),
|
.clk(clk),
|
.reset(reset),
|
.reset(reset),
|
.key_in(i_key[255:0]),
|
.key_in(i_key[255:0]),
|
.key_mode(i_key_mode[1:0]),
|
.key_mode(i_key_mode[1:0]),
|
.key_start(i_start),
|
.key_start(i_start),
|
.wr(wr),
|
.wr(wr),
|
.wr_addr(wr_addr[4:0]),
|
.wr_addr(wr_addr[4:0]),
|
.wr_data(wr_data[63:0]),
|
.wr_data(wr_data[63:0]),
|
.key_ready(o_key_ready)
|
.key_ready(o_key_ready)
|
);
|
);
|
|
|
endmodule
|
endmodule
|
/*****************************************************************************/
|
//---------------------------------------------------------------------------------------
|
|
|
No newline at end of file
|
No newline at end of file
|
