//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Key expansion module ////
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//// Key expansion module ////
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//// ////
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//// ////
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//// Description: ////
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//// Description: ////
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//// Used to expand the key based on key expansion procudure ////
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//// Used to expand the key based on key expansion procudure ////
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//// ////
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//// ////
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//// To Do: ////
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//// To Do: ////
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//// - done ////
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//// - done ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Luo Dongjun, dongjun_luo@hotmail.com ////
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//// - Luo Dongjun, dongjun_luo@hotmail.com ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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module key_exp (
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module key_exp (
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clk,
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clk,
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reset_n,
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reset,
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key_in,
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key_in,
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key_mode,
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key_mode,
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key_start,
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key_start,
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wr,
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wr,
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wr_addr,
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wr_addr,
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wr_data,
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wr_data,
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key_ready
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key_ready
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);
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);
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input clk;
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input clk;
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input reset_n;
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input reset;
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input [255:0] key_in; // initial key value
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input [255:0] key_in; // initial key value
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input [1:0] key_mode; // 0:128, 1:192, 2:256
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input [1:0] key_mode; // 0:128, 1:192, 2:256
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input key_start;// start key expansion
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input key_start;// start key expansion
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output wr; // key expansion ram interface
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output wr; // key expansion ram interface
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output [4:0] wr_addr;
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output [4:0] wr_addr;
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output [63:0] wr_data;
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output [63:0] wr_data;
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output key_ready;
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output key_ready;
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reg [31:0] rcon;
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reg [31:0] rcon;
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reg rcon_is_1b;
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reg rcon_is_1b;
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reg [1:0] state,nstate,pstate;
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reg [1:0] state,nstate,pstate;
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reg [3:0] round;
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reg [3:0] round;
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reg sbox_in_valid;
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reg sbox_in_valid;
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reg [31:0] sbox_in;
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reg [31:0] sbox_in;
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reg [4:0] valid;
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reg [4:0] valid;
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wire sbox_out_valid;
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wire sbox_out_valid;
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wire [31:0] sbox_out;
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wire [31:0] sbox_out;
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wire [31:0] w0_next,w1_next,w2_next,w3_next,w4_next1,w5_next1,w6_next,w7_next;
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wire [31:0] w0_next,w1_next,w2_next,w3_next,w4_next1,w5_next1,w6_next,w7_next;
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wire [31:0] w4_next2,w5_next2;
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wire [31:0] w4_next2,w5_next2;
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reg [31:0] w0,w1,w2,w3,w4,w5,w6,w7;
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reg [31:0] w0,w1,w2,w3,w4,w5,w6,w7;
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wire wr1,wr2,wr3,init_wr1,init_wr2,init_wr3,init_wr4;
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wire wr1,wr2,wr3,init_wr1,init_wr2,init_wr3,init_wr4;
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reg wr;
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reg wr;
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wire [63:0] wr_data1,wr_data2,wr_data3;
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wire [63:0] wr_data1,wr_data2,wr_data3;
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reg key_start_L,key_start_L2,key_start_L3;
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reg key_start_L,key_start_L2,key_start_L3;
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reg wr_256;
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reg wr_256;
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reg [4:0] wr_addr;
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reg [4:0] wr_addr;
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reg [63:0] wr_data;
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reg [63:0] wr_data;
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reg key_ready;
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reg key_ready;
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wire [3:0] max_round_p1;
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wire [3:0] max_round_p1;
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parameter IDLE = 2'b00,
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parameter IDLE = 2'b00,
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START = 2'b01,
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START = 2'b01,
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GENKEY1 = 2'b10,
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GENKEY1 = 2'b10,
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GENKEY_256 = 2'b11;
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GENKEY_256 = 2'b11;
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assign max_round_p1[3:0] = (key_mode == 2'b00) ? 4'd11 : (key_mode == 2'b01 ? 4'd13 : 4'd15);
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assign max_round_p1[3:0] = (key_mode == 2'b00) ? 4'd11 : (key_mode == 2'b01 ? 4'd13 : 4'd15);
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// rcon generation
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// rcon generation
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always @ (posedge clk or negedge reset_n)
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always @ (posedge clk or posedge reset)
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begin
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begin
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if (!reset_n)
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if (reset)
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begin
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begin
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rcon[31:0] <= 32'h01000000;
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rcon[31:0] <= 32'h01000000;
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rcon_is_1b <= 1'b0;
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rcon_is_1b <= 1'b0;
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end
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end
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else if (key_start)
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else if (key_start)
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begin
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begin
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rcon[31:0] <= 32'h01000000;
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rcon[31:0] <= 32'h01000000;
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rcon_is_1b <= 1'b0;
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rcon_is_1b <= 1'b0;
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end
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end
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else if (sbox_out_valid && (state[1:0] == GENKEY1))
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else if (sbox_out_valid && (state[1:0] == GENKEY1))
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begin
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begin
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if (rcon[31])
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if (rcon[31])
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begin
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begin
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rcon[31:0] <= 32'h1b000000;
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rcon[31:0] <= 32'h1b000000;
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rcon_is_1b <= 1'b1;
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rcon_is_1b <= 1'b1;
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end
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end
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else if (rcon_is_1b)
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else if (rcon_is_1b)
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begin
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begin
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rcon[31:0] <= 32'h36000000;
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rcon[31:0] <= 32'h36000000;
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rcon_is_1b <= 1'b1;
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rcon_is_1b <= 1'b1;
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end
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end
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else
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else
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rcon[31:0] <= {rcon[30:0],1'b0};
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rcon[31:0] <= {rcon[30:0],1'b0};
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end
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end
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end
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end
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/*****************************************************************************/
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/*****************************************************************************/
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// State machine for Key expansion
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// State machine for Key expansion
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//
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//
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//
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//
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always @ (posedge clk or negedge reset_n)
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always @ (posedge clk or posedge reset)
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begin
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begin
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if (!reset_n)
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if (reset)
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begin
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begin
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state[1:0] <= IDLE;
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state[1:0] <= IDLE;
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pstate[1:0] <= IDLE;
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pstate[1:0] <= IDLE;
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end
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end
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else
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else
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begin
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begin
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state[1:0] <= nstate[1:0];
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state[1:0] <= nstate[1:0];
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pstate[1:0] <= state[1:0];
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pstate[1:0] <= state[1:0];
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end
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end
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end
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end
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always @ (*)
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always @ (*)
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begin
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begin
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nstate[1:0] = state[1:0];
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nstate[1:0] = state[1:0];
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case (state[1:0])
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case (state[1:0])
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IDLE:
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IDLE:
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if (key_start) nstate[1:0] = START;
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if (key_start) nstate[1:0] = START;
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START:
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START:
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begin
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begin
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nstate[1:0] = GENKEY1;
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nstate[1:0] = GENKEY1;
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end
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end
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GENKEY1:
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GENKEY1:
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begin
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begin
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if (sbox_out_valid)
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if (sbox_out_valid)
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begin
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begin
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if (key_mode == 2'b00) //128 bit mode 4 x 10 + 4
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if (key_mode == 2'b00) //128 bit mode 4 x 10 + 4
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if (round[3:0] == 4'd10) nstate[1:0] = IDLE;
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if (round[3:0] == 4'd10) nstate[1:0] = IDLE;
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else nstate[1:0] = START;
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else nstate[1:0] = START;
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else if (key_mode == 2'b01) // 192 bit mode 6 + 6 x 8 = 54 > 52
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else if (key_mode == 2'b01) // 192 bit mode 6 + 6 x 8 = 54 > 52
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if (round[3:0] == 4'd8) nstate[1:0] = IDLE;
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if (round[3:0] == 4'd8) nstate[1:0] = IDLE;
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else nstate[1:0] = START;
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else nstate[1:0] = START;
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else if (round[3:0] == 4'd7)// 256 bit mode 8 + 8 x 7 = 64 > 60
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else if (round[3:0] == 4'd7)// 256 bit mode 8 + 8 x 7 = 64 > 60
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nstate[1:0] = IDLE;
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nstate[1:0] = IDLE;
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else
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else
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nstate[1:0] = GENKEY_256;
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nstate[1:0] = GENKEY_256;
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end
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end
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end
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end
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GENKEY_256:
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GENKEY_256:
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begin
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begin
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if (sbox_out_valid)
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if (sbox_out_valid)
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nstate[1:0] = START;
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nstate[1:0] = START;
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end
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end
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endcase
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endcase
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end
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end
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// round counter: 10/12/14
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// round counter: 10/12/14
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always @ (posedge clk or negedge reset_n)
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always @ (posedge clk or posedge reset)
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begin
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begin
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if (!reset_n)
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if (reset)
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round[3:0] <= 1'b0;
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round[3:0] <= 1'b0;
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else if (nstate[1:0] == IDLE)
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else if (nstate[1:0] == IDLE)
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round[3:0] <= 4'b0;
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round[3:0] <= 4'b0;
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else if (state[1:0] == START)
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else if (state[1:0] == START)
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round[3:0] <= round[3:0] + 1'b1;
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round[3:0] <= round[3:0] + 1'b1;
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end
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end
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always @ (posedge clk or negedge reset_n)
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always @ (posedge clk or posedge reset)
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begin
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begin
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if (!reset_n)
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if (reset)
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begin
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begin
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sbox_in_valid <= 1'b0;
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sbox_in_valid <= 1'b0;
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sbox_in[31:0] <= 32'b0;
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sbox_in[31:0] <= 32'b0;
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end
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end
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else if (state[1:0] == START) // rotword
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else if (state[1:0] == START) // rotword
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begin
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begin
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sbox_in_valid <= 1'b1;
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sbox_in_valid <= 1'b1;
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if (key_mode == 2'b00) //128
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if (key_mode == 2'b00) //128
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sbox_in[31:0] <= {w3[23:0],w3[31:24]};
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sbox_in[31:0] <= {w3[23:0],w3[31:24]};
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else if (key_mode == 2'b01) //192
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else if (key_mode == 2'b01) //192
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sbox_in[31:0] <= {w5[23:0],w5[31:24]};
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sbox_in[31:0] <= {w5[23:0],w5[31:24]};
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else //256
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else //256
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sbox_in[31:0] <= {w7[23:0],w7[31:24]};
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sbox_in[31:0] <= {w7[23:0],w7[31:24]};
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end
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end
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else if ((state[1:0] == GENKEY_256) && (pstate[1:0] ==GENKEY1))
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else if ((state[1:0] == GENKEY_256) && (pstate[1:0] ==GENKEY1))
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begin
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begin
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sbox_in_valid <= 1'b1;
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sbox_in_valid <= 1'b1;
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sbox_in[31:0] <= w3[31:0];
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sbox_in[31:0] <= w3[31:0];
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end
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end
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else
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else
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sbox_in_valid <= 1'b0;
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sbox_in_valid <= 1'b0;
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end
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end
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always @ (posedge clk or negedge reset_n)
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always @ (posedge clk or posedge reset)
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begin
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begin
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if (!reset_n)
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if (reset)
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valid[4:0] <= 5'b0;
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valid[4:0] <= 5'b0;
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else
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else
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valid[4:0] <= {valid[3:0],sbox_in_valid};
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valid[4:0] <= {valid[3:0],sbox_in_valid};
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end
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end
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assign sbox_out_valid = valid[1];
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assign sbox_out_valid = valid[1];
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sbox u_0(.clk(clk),.reset_n(reset_n),.enable(1'b1),.din(sbox_in[7:0]),.ende(1'b0),.en_dout(sbox_out[7:0]),.de_dout());
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sbox u_0(.clk(clk),.reset(reset),.enable(1'b1),.din(sbox_in[7:0]),.ende(1'b0),.en_dout(sbox_out[7:0]),.de_dout());
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sbox u_1(.clk(clk),.reset_n(reset_n),.enable(1'b1),.din(sbox_in[15:8]),.ende(1'b0),.en_dout(sbox_out[15:8]),.de_dout());
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sbox u_1(.clk(clk),.reset(reset),.enable(1'b1),.din(sbox_in[15:8]),.ende(1'b0),.en_dout(sbox_out[15:8]),.de_dout());
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sbox u_2(.clk(clk),.reset_n(reset_n),.enable(1'b1),.din(sbox_in[23:16]),.ende(1'b0),.en_dout(sbox_out[23:16]),.de_dout());
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sbox u_2(.clk(clk),.reset(reset),.enable(1'b1),.din(sbox_in[23:16]),.ende(1'b0),.en_dout(sbox_out[23:16]),.de_dout());
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sbox u_3(.clk(clk),.reset_n(reset_n),.enable(1'b1),.din(sbox_in[31:24]),.ende(1'b0),.en_dout(sbox_out[31:24]),.de_dout());
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sbox u_3(.clk(clk),.reset(reset),.enable(1'b1),.din(sbox_in[31:24]),.ende(1'b0),.en_dout(sbox_out[31:24]),.de_dout());
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/*****************************************************************************/
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/*****************************************************************************/
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// key expansion calculation
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// key expansion calculation
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//
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//
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//
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//
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assign w0_next[31:0] = sbox_out[31:0]^rcon[31:0]^w0[31:0];
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assign w0_next[31:0] = sbox_out[31:0]^rcon[31:0]^w0[31:0];
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assign w1_next[31:0] = w0_next[31:0]^w1[31:0];
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assign w1_next[31:0] = w0_next[31:0]^w1[31:0];
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assign w2_next[31:0] = w1_next[31:0]^w2[31:0];
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assign w2_next[31:0] = w1_next[31:0]^w2[31:0];
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assign w3_next[31:0] = w2_next[31:0]^w3[31:0];
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assign w3_next[31:0] = w2_next[31:0]^w3[31:0];
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assign w4_next1[31:0] = w3_next[31:0] ^ w4[31:0];
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assign w4_next1[31:0] = w3_next[31:0] ^ w4[31:0];
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assign w5_next1[31:0] = w4_next1[31:0]^w5[31:0];
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assign w5_next1[31:0] = w4_next1[31:0]^w5[31:0];
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assign w4_next2[31:0] = sbox_out[31:0] ^ w4[31:0];
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assign w4_next2[31:0] = sbox_out[31:0] ^ w4[31:0];
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assign w5_next2[31:0] = w4_next2[31:0]^w5[31:0];
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assign w5_next2[31:0] = w4_next2[31:0]^w5[31:0];
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assign w6_next[31:0] = w5_next2[31:0]^w6[31:0];
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assign w6_next[31:0] = w5_next2[31:0]^w6[31:0];
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assign w7_next[31:0] = w6_next[31:0]^w7[31:0];
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assign w7_next[31:0] = w6_next[31:0]^w7[31:0];
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always @ (posedge clk or negedge reset_n)
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always @ (posedge clk or posedge reset)
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begin
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begin
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if (!reset_n)
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if (reset)
|
begin
|
begin
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{w0[31:0],w1[31:0],w2[31:0],w3[31:0],w4[31:0],w5[31:0],w6[31:0],w7[31:0]} <= 256'b0;
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{w0[31:0],w1[31:0],w2[31:0],w3[31:0],w4[31:0],w5[31:0],w6[31:0],w7[31:0]} <= 256'b0;
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end
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end
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else if (key_start)
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else if (key_start)
|
begin
|
begin
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{w0[31:0],w1[31:0],w2[31:0],w3[31:0],w4[31:0],w5[31:0],w6[31:0],w7[31:0]} <= key_in[255:0];
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{w0[31:0],w1[31:0],w2[31:0],w3[31:0],w4[31:0],w5[31:0],w6[31:0],w7[31:0]} <= key_in[255:0];
|
end
|
end
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else if ((key_mode[1:0] == 2'b10) && sbox_out_valid)
|
else if ((key_mode[1:0] == 2'b10) && sbox_out_valid)
|
begin
|
begin
|
if (state[1:0] == GENKEY1)
|
if (state[1:0] == GENKEY1)
|
begin
|
begin
|
w0[31:0] <= w0_next[31:0];
|
w0[31:0] <= w0_next[31:0];
|
w1[31:0] <= w1_next[31:0];
|
w1[31:0] <= w1_next[31:0];
|
w2[31:0] <= w2_next[31:0];
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w2[31:0] <= w2_next[31:0];
|
w3[31:0] <= w3_next[31:0];
|
w3[31:0] <= w3_next[31:0];
|
end
|
end
|
else
|
else
|
begin
|
begin
|
w4[31:0] <= w4_next2[31:0];
|
w4[31:0] <= w4_next2[31:0];
|
w5[31:0] <= w5_next2[31:0];
|
w5[31:0] <= w5_next2[31:0];
|
w6[31:0] <= w6_next[31:0];
|
w6[31:0] <= w6_next[31:0];
|
w7[31:0] <= w7_next[31:0];
|
w7[31:0] <= w7_next[31:0];
|
end
|
end
|
end
|
end
|
else if (sbox_out_valid)
|
else if (sbox_out_valid)
|
begin
|
begin
|
w0[31:0] <= w0_next[31:0];
|
w0[31:0] <= w0_next[31:0];
|
w1[31:0] <= w1_next[31:0];
|
w1[31:0] <= w1_next[31:0];
|
w2[31:0] <= w2_next[31:0];
|
w2[31:0] <= w2_next[31:0];
|
w3[31:0] <= w3_next[31:0];
|
w3[31:0] <= w3_next[31:0];
|
if (key_mode[1:0] == 2'b01)
|
if (key_mode[1:0] == 2'b01)
|
begin
|
begin
|
w4[31:0] <= w4_next1[31:0];
|
w4[31:0] <= w4_next1[31:0];
|
w5[31:0] <= w5_next1[31:0];
|
w5[31:0] <= w5_next1[31:0];
|
end
|
end
|
end
|
end
|
end
|
end
|
|
|
// write to external ram
|
// write to external ram
|
assign init_wr1 = key_start;
|
assign init_wr1 = key_start;
|
assign init_wr2 = key_start_L;
|
assign init_wr2 = key_start_L;
|
assign init_wr3 = key_start_L2 && (key_mode[1:0] != 2'b00);
|
assign init_wr3 = key_start_L2 && (key_mode[1:0] != 2'b00);
|
assign init_wr4 = key_start_L3 && (key_mode[1:0] == 2'b10);
|
assign init_wr4 = key_start_L3 && (key_mode[1:0] == 2'b10);
|
assign wr1 = valid[2];
|
assign wr1 = valid[2];
|
assign wr2 = valid[3];
|
assign wr2 = valid[3];
|
assign wr3 = valid[4] && (key_mode[1:0] == 2'b01) && (state[1:0] != IDLE); // remove the last write
|
assign wr3 = valid[4] && (key_mode[1:0] == 2'b01) && (state[1:0] != IDLE); // remove the last write
|
|
|
assign wr_data1[63:0] = wr_256 ?{w4[31:0],w5[31:0]} : {w0[31:0],w1[31:0]};
|
assign wr_data1[63:0] = wr_256 ?{w4[31:0],w5[31:0]} : {w0[31:0],w1[31:0]};
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assign wr_data2[63:0] = wr_256 ?{w6[31:0],w7[31:0]} : {w2[31:0],w3[31:0]};
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assign wr_data2[63:0] = wr_256 ?{w6[31:0],w7[31:0]} : {w2[31:0],w3[31:0]};
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assign wr_data3[63:0] = {w4[31:0],w5[31:0]};
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assign wr_data3[63:0] = {w4[31:0],w5[31:0]};
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always @ (posedge clk or negedge reset_n)
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always @ (posedge clk or posedge reset)
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begin
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begin
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if (!reset_n)
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if (reset)
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wr_256 <= 1'b0;
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wr_256 <= 1'b0;
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else if (key_start)
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else if (key_start)
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wr_256 <= 1'b0;
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wr_256 <= 1'b0;
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else if (sbox_out_valid && (state[1:0] == GENKEY_256))
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else if (sbox_out_valid && (state[1:0] == GENKEY_256))
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wr_256 <= 1'b1;
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wr_256 <= 1'b1;
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else if (sbox_out_valid)
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else if (sbox_out_valid)
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wr_256 <= 1'b0;
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wr_256 <= 1'b0;
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end
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end
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always @ (posedge clk or negedge reset_n)
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always @ (posedge clk or posedge reset)
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begin
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begin
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if (!reset_n)
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if (reset)
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{key_start_L3,key_start_L2,key_start_L} <= 3'b0;
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{key_start_L3,key_start_L2,key_start_L} <= 3'b0;
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else
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else
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{key_start_L3,key_start_L2,key_start_L} <= {key_start_L2,key_start_L,key_start};
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{key_start_L3,key_start_L2,key_start_L} <= {key_start_L2,key_start_L,key_start};
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end
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end
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|
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always @ (posedge clk or negedge reset_n)
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always @ (posedge clk or posedge reset)
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begin
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begin
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if (!reset_n)
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if (reset)
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wr <= 1'b0;
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wr <= 1'b0;
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else
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else
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wr <= wr1 || wr2 || wr3 || init_wr1 || init_wr2 || init_wr3 || init_wr4;
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wr <= wr1 || wr2 || wr3 || init_wr1 || init_wr2 || init_wr3 || init_wr4;
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end
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end
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|
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always @ (posedge clk or negedge reset_n)
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always @ (posedge clk or posedge reset)
|
begin
|
begin
|
if (!reset_n)
|
if (reset)
|
begin
|
begin
|
wr_data[63:0] <= 64'b0;
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wr_data[63:0] <= 64'b0;
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end
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end
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else
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else
|
begin
|
begin
|
if (init_wr1)
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if (init_wr1)
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wr_data[63:0] <= key_in[255:192];
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wr_data[63:0] <= key_in[255:192];
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else if (init_wr2)
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else if (init_wr2)
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wr_data[63:0] <= key_in[191:128];
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wr_data[63:0] <= key_in[191:128];
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else if (init_wr3)
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else if (init_wr3)
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wr_data[63:0] <= key_in[127:64];
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wr_data[63:0] <= key_in[127:64];
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else if (init_wr4)
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else if (init_wr4)
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wr_data[63:0] <= key_in[63:0];
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wr_data[63:0] <= key_in[63:0];
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else if (wr1)
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else if (wr1)
|
wr_data[63:0] <= wr_data1[63:0];
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wr_data[63:0] <= wr_data1[63:0];
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else if (wr2)
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else if (wr2)
|
wr_data[63:0] <= wr_data2[63:0];
|
wr_data[63:0] <= wr_data2[63:0];
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else if (wr3)
|
else if (wr3)
|
wr_data[63:0] <= wr_data3[63:0];
|
wr_data[63:0] <= wr_data3[63:0];
|
end
|
end
|
end
|
end
|
|
|
always @ (posedge clk or negedge reset_n)
|
always @ (posedge clk or posedge reset)
|
begin
|
begin
|
if (!reset_n)
|
if (reset)
|
wr_addr[4:0] <= 5'b0;
|
wr_addr[4:0] <= 5'b0;
|
else if (key_start)
|
else if (key_start)
|
wr_addr[4:0] <= 5'd0;
|
wr_addr[4:0] <= 5'd0;
|
else if (wr)
|
else if (wr)
|
wr_addr[4:0] <= wr_addr[4:0] + 1'b1;
|
wr_addr[4:0] <= wr_addr[4:0] + 1'b1;
|
end
|
end
|
|
|
always @ (posedge clk or negedge reset_n)
|
always @ (posedge clk or posedge reset)
|
begin
|
begin
|
if (!reset_n)
|
if (reset)
|
key_ready <= 1'b0;
|
key_ready <= 1'b0;
|
else if (key_start)
|
else if (key_start)
|
key_ready <= 1'b0;
|
key_ready <= 1'b0;
|
else if (wr_addr[4:1] == max_round_p1[3:0])
|
else if (wr_addr[4:1] == max_round_p1[3:0])
|
key_ready <= 1'b1;
|
key_ready <= 1'b1;
|
end
|
end
|
endmodule
|
endmodule
|
|
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