`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////////////////
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// Company: BMSTU
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// Company: BMSTU
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// Engineer: Oleg Odintsov
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// Engineer: Oleg Odintsov
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//
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//
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// Create Date: 18:21:00 01/17/2012
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// Create Date: 18:21:00 01/17/2012
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// Design Name:
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// Design Name:
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// Project Name: Agat Hardware Project
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// Project Name: Agat Hardware Project
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// Project Name:
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// Project Name:
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// Target Devices:
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// Target Devices:
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// Tool versions:
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// Tool versions:
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// Description:
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// Description:
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//
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//
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// Dependencies:
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// Dependencies:
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//
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//
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// Revision:
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// Revision:
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// Revision 0.01 - File Created
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// Revision 0.01 - File Created
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// Additional Comments:
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// Additional Comments:
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//
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//
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//////////////////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////////////////
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module chip1(
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module chip1(
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input clk,
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input clk,
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input b1,
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input b1,
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input b2,
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input b2,
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input[3:0] SW,
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input rot_a, rot_b, rot_center,
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input rot_a, rot_b, rot_center,
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output[7:0] led,
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output[7:0] led,
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output vga_red,
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output vga_red,
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output vga_green,
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output vga_green,
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output vga_blue,
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output vga_blue,
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output vga_hsync,
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output vga_hsync,
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output vga_vsync,
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output vga_vsync,
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output [3:0]j4,
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output [3:0]j4,
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input spi_miso, output spi_mosi, output spi_sck, output dac_cs, output dac_clr,
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input spi_miso, output spi_mosi, output spi_sck, output dac_cs, output dac_clr,
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output spi_rom_cs,
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output spi_rom_cs,
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output spi_amp_cs,
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output spi_amp_cs,
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output spi_adc_conv,
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output spi_adc_conv,
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output strataflash_oe,
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output strataflash_oe,
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output strataflash_ce,
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output strataflash_ce,
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output strataflash_we,
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output strataflash_we,
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output platformflash_oe,
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output platformflash_oe,
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input ps2_clk,
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input ps2_clk,
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input ps2_data
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input ps2_data
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);
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);
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// access to DAC
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// access to DAC
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assign spi_mosi = 0, spi_sck = 0, dac_cs = 0, dac_clr = 0;
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assign spi_mosi = 0, spi_sck = 0, dac_cs = 0, dac_clr = 0;
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// block other devices to access to DAC
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// block other devices to access to DAC
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assign spi_rom_cs = 1, spi_amp_cs = 1, spi_adc_conv = 0;
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assign spi_rom_cs = 1, spi_amp_cs = 1, spi_adc_conv = 0;
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assign strataflash_oe = 1, strataflash_ce = 1, strataflash_we = 1;
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assign strataflash_oe = 1, strataflash_ce = 1, strataflash_we = 1;
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assign platformflash_oe = 0;
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assign platformflash_oe = 0;
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wire[4:0] vga_bus;
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wire[4:0] vga_bus;
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assign {vga_red, vga_green, vga_blue, vga_hsync, vga_vsync} = vga_bus;
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assign {vga_red, vga_green, vga_blue, vga_hsync, vga_vsync} = vga_bus;
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wire[1:0] ps2_bus = {ps2_clk, ps2_data};
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wire[1:0] ps2_bus = {ps2_clk, ps2_data};
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// assign j4 = 0, vga_bus = 0;
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// assign j4 = 0, vga_bus = 0;
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wire[3:0] btns = {0, 0, b2, b1};
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wire[3:0] btns = {0, 0, b2, b1};
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ag_main agate(clk, btns, led, j4, vga_bus, ps2_bus);
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ag_main agate(clk, btns, SW, led, j4, vga_bus, ps2_bus);
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endmodule
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endmodule
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