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// Copyright (c) 2007 TooMuch Semiconductor Solutions Pvt Ltd.
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// Copyright (c) 2007 TooMuch Semiconductor Solutions Pvt Ltd.
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//File name : ahb2wb.v
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//File name : ahb2wb.v
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//Designer : Manish Agarwal
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//Designer : Manish Agarwal
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//Date : 18 May, 2007
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//Date : 18 May, 2007
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//Description : AHB WISHBONE BRIDGE :- This design will connect AHB master interface with Wishbone slave.
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//Description : AHB WISHBONE BRIDGE :- This design will connect AHB master interface with Wishbone slave.
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// This design will perform only single read-write operation.
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// This design will perform only single read-write operation.
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//Revision : 1.0
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//Revision : 1.0
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//******************************************************************************************************
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//******************************************************************************************************
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`timescale 1 ns/1 ns
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`timescale 1 ns/1 ns
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module ahb2wb(
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module ahb2wb(
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adr_o, dat_o, dat_i, ack_i, cyc_o,
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adr_o, dat_o, dat_i, ack_i, cyc_o,
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we_o, stb_o, hclk, hresetn, haddr, htrans, hwrite, hsize, hburst,
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we_o, stb_o, hclk, hresetn, haddr, htrans, hwrite, hsize, hburst,
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hsel, hwdata, hrdata, hresp, hready, clk_i, rst_i
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hsel, hwdata, hrdata, hresp, hready, clk_i, rst_i
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);
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);
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//parameter declaration
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//parameter declaration
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parameter AWIDTH = 16;
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parameter AWIDTH = 16;
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parameter DWIDTH = 32;
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parameter DWIDTH = 32;
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//**************************************
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//**************************************
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// input ports
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// input ports
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//**************************************
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//**************************************
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//wishbone ports
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//wishbone ports
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input [DWIDTH-1:0]dat_i; // data input from wishbone slave
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input [DWIDTH-1:0]dat_i; // data input from wishbone slave
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input ack_i; // acknowledment from wishbone slave
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input ack_i; // acknowledment from wishbone slave
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input clk_i;
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input clk_i;
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input rst_i;
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input rst_i;
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//AHB ports
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//AHB ports
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input hclk; // clock
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input hclk; // clock
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input hresetn; // active low reset
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input hresetn; // active low reset
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input [DWIDTH-1:0]hwdata; // data bus
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input [DWIDTH-1:0]hwdata; // data bus
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input hwrite; // write/read enable
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input hwrite; // write/read enable
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input [2:0]hburst; // burst type
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input [2:0]hburst; // burst type
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input [2:0]hsize; // data size
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input [2:0]hsize; // data size
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input [1:0]htrans; // type of transfer
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input [1:0]htrans; // type of transfer
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input hsel; // slave select
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input hsel; // slave select
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input [AWIDTH-1:0]haddr; // address bus
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input [AWIDTH-1:0]haddr; // address bus
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//**************************************
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//**************************************
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// output ports
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// output ports
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//**************************************
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//**************************************
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//wishbone ports
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//wishbone ports
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output [AWIDTH-1:0]adr_o; // address to wishbone slave
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output [AWIDTH-1:0]adr_o; // address to wishbone slave
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output [DWIDTH-1:0]dat_o; // data output for wishbone slave
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output [DWIDTH-1:0]dat_o; // data output for wishbone slave
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output cyc_o; // signal to indicate valid bus cycle
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output cyc_o; // signal to indicate valid bus cycle
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output we_o; // write enable
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output we_o; // write enable
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output stb_o; // strobe to indicate valid data transfer cycle
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output stb_o; // strobe to indicate valid data transfer cycle
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// AHB ports
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// AHB ports
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output [DWIDTH-1:0]hrdata; // data output for wishbone slave
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output [DWIDTH-1:0]hrdata; // data output for wishbone slave
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output [1:0]hresp; // response signal from slave
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output [1:0]hresp; // response signal from slave
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output hready; // slave ready
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output hready; // slave ready
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//**************************************
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//**************************************
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// inout ports
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// inout ports
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//**************************************
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//**************************************
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//**********************************************************************************
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//**********************************************************************************
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// datatype declaration
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// datatype declaration
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reg [DWIDTH-1:0]hrdata;
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reg [DWIDTH-1:0]hrdata;
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reg hready;
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reg hready;
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reg [1:0]hresp;
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reg [1:0]hresp;
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reg stb_o;
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reg stb_o;
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wire we_o;
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wire we_o;
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reg cyc_o;
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reg cyc_o;
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wire [AWIDTH-1:0]adr_o;
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wire [AWIDTH-1:0]adr_o;
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reg [DWIDTH-1:0]dat_o;
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reg [DWIDTH-1:0]dat_o;
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// local memory registers
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// local memory registers
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reg [AWIDTH-1 : 0]addr_temp;
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reg [AWIDTH-1 : 0]addr_temp;
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reg hwrite_temp; // to hold write enable signal temporarily
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reg hwrite_temp; // to hold write enable signal temporarily
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//*******************************************************************
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//*******************************************************************
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// AHB WISHBONE BRIDGE logic
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// AHB WISHBONE BRIDGE logic
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//*******************************************************************
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//*******************************************************************
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assign #2 we_o = hwrite_temp;
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assign #2 we_o = hwrite_temp;
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assign #2 adr_o = addr_temp;
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assign #2 adr_o = addr_temp;
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always @ (posedge hclk ) begin
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always @ (posedge hclk ) begin
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if (!hresetn) begin
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if (!hresetn) begin
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hresp <= 2'b00;
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hresp <= 2'b00;
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cyc_o <= 'b0;
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cyc_o <= 'b0;
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stb_o <= 'b0;
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stb_o <= 'b0;
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addr_temp <= 'bx;
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addr_temp <= 'bx;
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hwrite_temp <= 'bx;
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hwrite_temp <= 'bx;
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dat_o <='bx;
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dat_o <='bx;
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end
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end
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else if(hready & hsel) begin
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else if(hready & hsel) begin
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case (hburst)
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case (hburst)
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// single transfer
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// single transfer
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3'b000 : begin
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3'b000 : begin
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case (htrans)
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case (htrans)
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// idle transfer type
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// idle transfer type
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2'b00 : begin
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2'b00 : begin
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cyc_o <= 'b0;
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cyc_o <= 'b0;
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hresp <= 2'b00; // ok response
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hresp <= 2'b00; // ok response
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stb_o <= 'b0;
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stb_o <= 'b0;
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end
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end
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// busy transfer type
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// busy transfer type
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2'b01 : begin
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2'b01 : begin
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hresp <= 2'b00; // ok response
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hresp <= 2'b00; // ok response
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stb_o <= 'b0;
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stb_o <= 'b0;
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cyc_o <= 'b1;
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cyc_o <= 'b1;
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end
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end
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// Non-Sequential
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// Non-Sequential
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2'b10 : begin
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2'b10 : begin
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cyc_o <= 'b1;
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cyc_o <= 'b1;
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stb_o <= 'b1;
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stb_o <= 'b1;
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addr_temp <= haddr;
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addr_temp <= haddr;
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hwrite_temp <= hwrite; // control signal stored that was received in address phase
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hwrite_temp <= hwrite; // control signal stored that was received in address phase
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end
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end
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endcase
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endcase
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end
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end
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default : cyc_o <= 'b0;
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default : cyc_o <= 'b0;
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endcase
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endcase
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end
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end
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else if (!hsel & hready) begin
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else if (!hsel & hready) begin
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cyc_o <= 'b0; //invalid bus transfer
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cyc_o <= 'b0; //invalid bus transfer
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end
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end
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end
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end
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// combinational logic - asynchronous read/write
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// combinational logic - asynchronous read/write
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always@(hwrite_temp or hwdata or dat_i or ack_i or hresetn or stb_o ) begin
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always@(hwrite_temp or hwdata or dat_i or ack_i or hresetn or stb_o ) begin
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if (!hresetn) begin
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if (!hresetn) begin
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hready <= 'b1;
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hready <= 'b1;
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end
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end
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else begin
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else begin
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if (stb_o)
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if (stb_o)
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hready = ack_i;
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hready = ack_i;
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if ( hwrite_temp )
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if ( hwrite_temp )
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dat_o = hwdata;
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dat_o = hwdata;
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else if (!hwrite_temp)
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else if (!hwrite_temp)
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hrdata = dat_i;
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hrdata = dat_i;
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end
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end
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end
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end
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endmodule
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endmodule
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