/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Author: Eyal Hochberg ////
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//// Author: Eyal Hochberg ////
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//// eyal@provartec.com ////
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//// eyal@provartec.com ////
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//// ////
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//// ////
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//// Downloaded from: http://www.opencores.org ////
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//// Downloaded from: http://www.opencores.org ////
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2010 Provartec LTD ////
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//// Copyright (C) 2010 Provartec LTD ////
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//// www.provartec.com ////
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//// www.provartec.com ////
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//// info@provartec.com ////
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//// info@provartec.com ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation.////
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//// Public License as published by the Free Software Foundation.////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more////
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//// PURPOSE. See the GNU Lesser General Public License for more////
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//// details. http://www.gnu.org/licenses/lgpl.html ////
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//// details. http://www.gnu.org/licenses/lgpl.html ////
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//// ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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//////////////////////////////////////
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//////////////////////////////////////
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//
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//
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// General:
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// General:
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// The AHB is built of an AXI master and an AXI2AHB bridge
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// The AHB is built of an AXI master and an AXI2AHB bridge
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//
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//
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//
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//
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// I/F :
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// I/F :
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// idle - all internal masters emptied their command FIFOs
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// idle - all internal masters emptied their command FIFOs
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// scrbrd_empty - all scoreboard checks have been completed (for random testing)
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// scrbrd_empty - all scoreboard checks have been completed (for random testing)
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//
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//
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//
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//
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// Tasks:
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// Tasks:
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//
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//
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// enable()
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// enable()
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// Description: Enables AHB master
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// Description: Enables AHB master
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//
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//
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// write_single(input addr, input wdata)
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// write_single(input addr, input wdata)
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// Description: write a single AHB burst (1 data cycle)
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// Description: write a single AHB burst (1 data cycle)
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// Parameters:
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// Parameters:
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// addr - address
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// addr - address
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// wdata - write data
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// wdata - write data
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//
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//
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// read_single(input addr, output rdata)
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// read_single(input addr, output rdata)
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// Description:
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// Description:
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// Parameters:
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// Parameters:
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// addr - address
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// addr - address
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// rdata - return read data
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// rdata - return read data
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//
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//
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// check_single(input addr, input expected)
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// check_single(input addr, input expected)
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// Description: read a single AHB burst and gives an error if the data read does not match expected
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// Description: read a single AHB burst and gives an error if the data read does not match expected
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// Parameters:
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// Parameters:
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// addr - address
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// addr - address
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// expected - expected read data
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// expected - expected read data
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//
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//
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// write_and_check_single(input addr, input data)
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// write_and_check_single(input addr, input data)
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// Description: write a single AHB burst read it back and compare the write and read data
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// Description: write a single AHB burst read it back and compare the write and read data
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// Parameters:
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// Parameters:
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// addr - address
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// addr - address
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// data - data to write and expect on read
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// data - data to write and expect on read
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//
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//
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// insert_wr_cmd(input addr, input len, input size)
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// insert_wr_cmd(input addr, input len, input size)
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// Description: add an AHB write burst to command FIFO
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// Description: add an AHB write burst to command FIFO
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// Parameters:
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// Parameters:
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// addr - address
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// addr - address
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// len - AHB LEN (data strobe number)
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// len - AHB LEN (data strobe number)
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// size - AHB SIZE (data width)
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// size - AHB SIZE (data width)
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//
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//
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// insert_rd_cmd(input addr, input len, input size)
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// insert_rd_cmd(input addr, input len, input size)
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// Description: add an AHB read burst to command FIFO
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// Description: add an AHB read burst to command FIFO
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// Parameters:
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// Parameters:
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// addr - address
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// addr - address
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// len - AHB LEN (data strobe number)
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// len - AHB LEN (data strobe number)
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// size - AHB SIZE (data width)
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// size - AHB SIZE (data width)
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//
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//
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// insert_wr_data(input wdata)
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// insert_wr_data(input wdata)
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// Description: add a single data to data FIFO (to be used in write bursts)
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// Description: add a single data to data FIFO (to be used in write bursts)
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// Parameters:
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// Parameters:
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// wdata - write data
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// wdata - write data
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//
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//
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// insert_wr_incr_data(input addr, input len, input size)
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// insert_wr_incr_data(input addr, input len, input size)
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// Description: add an AHB write burst to command FIFO will use incremental data (no need to use insert_wr_data)
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// Description: add an AHB write burst to command FIFO will use incremental data (no need to use insert_wr_data)
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// Parameters:
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// Parameters:
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// addr - address
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// addr - address
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// len - AHB LEN (data strobe number)
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// len - AHB LEN (data strobe number)
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// size - AHB SIZE (data width)
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// size - AHB SIZE (data width)
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//
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//
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// insert_rand_chk(input burst_num)
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// insert_rand_chk(input burst_num)
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// Description: add multiple commands to command FIFO. Each command writes incremental data to a random address, reads the data back and checks the data. Useful for random testing.
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// Description: add multiple commands to command FIFO. Each command writes incremental data to a random address, reads the data back and checks the data. Useful for random testing.
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// Parameters:
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// Parameters:
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// burst_num - total number of bursts to check
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// burst_num - total number of bursts to check
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//
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//
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//
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//
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// Parameters:
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// Parameters:
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//
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//
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// For random testing: (changing these values automatically update interanl masters)
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// For random testing: (changing these values automatically update interanl masters)
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// len_min - minimum burst AHB LEN (length)
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// len_min - minimum burst AHB LEN (length)
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// len_max - maximum burst AHB LEN (length)
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// len_max - maximum burst AHB LEN (length)
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// size_min - minimum burst AHB SIZE (width)
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// size_min - minimum burst AHB SIZE (width)
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// size_max - maximum burst AHB SIZE (width)
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// size_max - maximum burst AHB SIZE (width)
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// addr_min - minimum address (in bytes)
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// addr_min - minimum address (in bytes)
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// addr_max - maximum address (in bytes)
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// addr_max - maximum address (in bytes)
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//
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//
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//////////////////////////////////////
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//////////////////////////////////////
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OUTFILE PREFIX.v
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OUTFILE PREFIX.v
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INCLUDE def_ahb_master.txt
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INCLUDE def_ahb_master.txt
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module PREFIX(PORTS);
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module PREFIX(PORTS);
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input clk;
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input clk;
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input reset;
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input reset;
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revport GROUP_AHB;
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revport GROUP_AHB;
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output idle;
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output idle;
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output scrbrd_empty;
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output scrbrd_empty;
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parameter LEN_BITS = 4;
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parameter LEN_BITS = 4;
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##parameter SIZE_BITS = 2;
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##parameter SIZE_BITS = 2;
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wire GROUP_AXI;
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wire GROUP_AXI;
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wire GROUP_AHB;
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wire GROUP_AHB;
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integer GROUP_AXI_MASTER_RAND = GROUP_AXI_MASTER_RAND.DEFAULT;
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integer GROUP_AXI_MASTER_RAND = GROUP_AXI_MASTER_RAND.DEFAULT;
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always @(*)
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always @(*)
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begin
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begin
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#FFD;
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#FFD;
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axi_master.GROUP_AXI_MASTER_RAND = GROUP_AXI_MASTER_RAND;
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axi_master.GROUP_AXI_MASTER_RAND = GROUP_AXI_MASTER_RAND;
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end
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end
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initial
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initial
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begin
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begin
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#100;
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#100;
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ahb_bursts=1;
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ahb_bursts=1;
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end
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end
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CREATE axi_master.v \\
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CREATE axi_master.v \\
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DEFCMD(SWAP.GLOBAL CONST(PREFIX) PREFIX_axi_master) \\
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DEFCMD(SWAP.GLOBAL CONST(PREFIX) PREFIX_axi_master) \\
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DEFCMD(SWAP.GLOBAL CONST(ID_BITS) ID_BITS) \\
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DEFCMD(SWAP.GLOBAL CONST(ID_BITS) ID_BITS) \\
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DEFCMD(SWAP.GLOBAL CONST(ADDR_BITS) ADDR_BITS) \\
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DEFCMD(SWAP.GLOBAL CONST(ADDR_BITS) ADDR_BITS) \\
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DEFCMD(SWAP.GLOBAL CONST(DATA_BITS) DATA_BITS) \\
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DEFCMD(SWAP.GLOBAL CONST(DATA_BITS) DATA_BITS) \\
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DEFCMD(SWAP.GLOBAL CONST(SIZE_BITS) SIZE_BITS) \\
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DEFCMD(GROUP.USER AXI_ID overrides {) \\
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DEFCMD(GROUP.USER AXI_ID overrides {) \\
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DEFCMD(0) \\
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DEFCMD(0) \\
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DEFCMD(})
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DEFCMD(})
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PREFIX_axi_master axi_master(
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PREFIX_axi_master axi_master(
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.clk(clk),
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.clk(clk),
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.reset(reset),
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.reset(reset),
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.GROUP_AXI(GROUP_AXI),
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.GROUP_AXI(GROUP_AXI),
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.idle(idle),
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.idle(idle),
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.scrbrd_empty(scrbrd_empty)
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.scrbrd_empty(scrbrd_empty)
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);
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);
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CREATE axi2ahb.v \\
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CREATE axi2ahb.v \\
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DEFCMD(SWAP.GLOBAL CONST(PREFIX) PREFIX_axi2ahb) \\
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DEFCMD(SWAP.GLOBAL CONST(PREFIX) PREFIX_axi2ahb) \\
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DEFCMD(SWAP.GLOBAL CONST(CMD_DEPTH) 4) \\
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DEFCMD(SWAP.GLOBAL CONST(CMD_DEPTH) 4) \\
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DEFCMD(SWAP.GLOBAL CONST(ADDR_BITS) ADDR_BITS) \\
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DEFCMD(SWAP.GLOBAL CONST(ADDR_BITS) ADDR_BITS) \\
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DEFCMD(SWAP.GLOBAL CONST(DATA_BITS) DATA_BITS) \\
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DEFCMD(SWAP.GLOBAL CONST(DATA_BITS) DATA_BITS) \\
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DEFCMD(SWAP.GLOBAL CONST(SIZE_BITS) SIZE_BITS) \\
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DEFCMD(SWAP.GLOBAL CONST(ID_BITS) ID_BITS)
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DEFCMD(SWAP.GLOBAL CONST(ID_BITS) ID_BITS)
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PREFIX_axi2ahb axi2ahb(
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PREFIX_axi2ahb axi2ahb(
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.clk(clk),
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.clk(clk),
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.reset(reset),
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.reset(reset),
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.GROUP_AXI(GROUP_AXI),
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.GROUP_AXI(GROUP_AXI),
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.GROUP_AHB(GROUP_AHB),
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.GROUP_AHB(GROUP_AHB),
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STOMP ,
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STOMP ,
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);
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);
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task enable;
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task enable;
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begin
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begin
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axi_master.enable(0);
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axi_master.enable(0);
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end
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end
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endtask
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endtask
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task write_single;
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task write_single;
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input [ADDR_BITS-1:0] addr;
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input [ADDR_BITS-1:0] addr;
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input [DATA_BITS-1:0] wdata;
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input [DATA_BITS-1:0] wdata;
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begin
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begin
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axi_master.write_single(0, addr, wdata);
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axi_master.write_single(0, addr, wdata);
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end
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end
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endtask
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endtask
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task read_single;
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task read_single;
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input [ADDR_BITS-1:0] addr;
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input [ADDR_BITS-1:0] addr;
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output [DATA_BITS-1:0] rdata;
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output [DATA_BITS-1:0] rdata;
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begin
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begin
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axi_master.read_single(0, addr, rdata);
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axi_master.read_single(0, addr, rdata);
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end
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end
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endtask
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endtask
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task check_single;
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task check_single;
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input [ADDR_BITS-1:0] addr;
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input [ADDR_BITS-1:0] addr;
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input [DATA_BITS-1:0] expected;
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input [DATA_BITS-1:0] expected;
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begin
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begin
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axi_master.check_single(0, addr, expected);
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axi_master.check_single(0, addr, expected);
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end
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end
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endtask
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endtask
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task write_and_check_single;
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task write_and_check_single;
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input [ADDR_BITS-1:0] addr;
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input [ADDR_BITS-1:0] addr;
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input [DATA_BITS-1:0] data;
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input [DATA_BITS-1:0] data;
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begin
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begin
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axi_master.write_and_check_single(0, addr, data);
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axi_master.write_and_check_single(0, addr, data);
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end
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end
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endtask
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endtask
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task insert_wr_cmd;
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task insert_wr_cmd;
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input [ADDR_BITS-1:0] addr;
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input [ADDR_BITS-1:0] addr;
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input [LEN_BITS-1:0] len;
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input [LEN_BITS-1:0] len;
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input [SIZE_BITS-1:0] size;
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input [SIZE_BITS-1:0] size;
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begin
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begin
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axi_master.insert_wr_cmd(0, addr, len, size);
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axi_master.insert_wr_cmd(0, addr, len, size);
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end
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end
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endtask
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endtask
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task insert_rd_cmd;
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task insert_rd_cmd;
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input [ADDR_BITS-1:0] addr;
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input [ADDR_BITS-1:0] addr;
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input [LEN_BITS-1:0] len;
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input [LEN_BITS-1:0] len;
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input [SIZE_BITS-1:0] size;
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input [SIZE_BITS-1:0] size;
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begin
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begin
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axi_master.insert_rd_cmd(0, addr, len, size);
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axi_master.insert_rd_cmd(0, addr, len, size);
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end
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end
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endtask
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endtask
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task insert_wr_data;
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task insert_wr_data;
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input [DATA_BITS-1:0] wdata;
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input [DATA_BITS-1:0] wdata;
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begin
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begin
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axi_master.insert_wr_data(0, wdata);
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axi_master.insert_wr_data(0, wdata);
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end
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end
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endtask
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endtask
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task insert_wr_incr_data;
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task insert_wr_incr_data;
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input [ADDR_BITS-1:0] addr;
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input [ADDR_BITS-1:0] addr;
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input [LEN_BITS-1:0] len;
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input [LEN_BITS-1:0] len;
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input [SIZE_BITS-1:0] size;
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input [SIZE_BITS-1:0] size;
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begin
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begin
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axi_master.insert_wr_incr_data(0, addr, len, size);
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axi_master.insert_wr_incr_data(0, addr, len, size);
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end
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end
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endtask
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endtask
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task insert_rand_chk;
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task insert_rand_chk;
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input [31:0] burst_num;
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input [31:0] burst_num;
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begin
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begin
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axi_master.insert_rand_chk(0, burst_num);
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axi_master.insert_rand_chk(0, burst_num);
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end
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end
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endtask
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endtask
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endmodule
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endmodule
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