/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Author: Eyal Hochberg ////
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//// Author: Eyal Hochberg ////
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//// eyal@provartec.com ////
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//// eyal@provartec.com ////
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//// ////
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//// ////
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//// Downloaded from: http://www.opencores.org ////
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//// Downloaded from: http://www.opencores.org ////
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2010 Provartec LTD ////
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//// Copyright (C) 2010 Provartec LTD ////
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//// www.provartec.com ////
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//// www.provartec.com ////
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//// info@provartec.com ////
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//// info@provartec.com ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation.////
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//// Public License as published by the Free Software Foundation.////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more////
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//// PURPOSE. See the GNU Lesser General Public License for more////
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//// details. http://www.gnu.org/licenses/lgpl.html ////
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//// details. http://www.gnu.org/licenses/lgpl.html ////
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//// ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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OUTFILE PREFIX_single.v
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OUTFILE PREFIX_single.v
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INCLUDE def_axi_master.txt
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INCLUDE def_axi_master.txt
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module PREFIX_single(PORTS);
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module PREFIX_single(PORTS);
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parameter MASTER_NUM = 0;
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parameter MASTER_NUM = 0;
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parameter MASTER_ID = 0;
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parameter MASTER_ID = 0;
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parameter MASTER_PEND = 0;
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parameter MASTER_PEND = 0;
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CREATE prgen_rand.v DEFCMD(DEFINE NOT_IN_LIST)
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CREATE prgen_rand.v DEFCMD(DEFINE NOT_IN_LIST)
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`include "prgen_rand.v"
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`include "prgen_rand.v"
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parameter MAX_CMDS = 16; //Depth of command FIFO
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parameter MAX_CMDS = 16; //Depth of command FIFO
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parameter DATA_LOG = LOG2(EXPR(DATA_BITS/8));
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parameter DATA_LOG = LOG2(EXPR(DATA_BITS/8));
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parameter PEND_BITS =
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parameter PEND_BITS =
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(MAX_CMDS <= 16) ? 4 :
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(MAX_CMDS <= 16) ? 4 :
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(MAX_CMDS <= 32) ? 5 :
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(MAX_CMDS <= 32) ? 5 :
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(MAX_CMDS <= 64) ? 6 :
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(MAX_CMDS <= 64) ? 6 :
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(MAX_CMDS <= 128) ? 7 :
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(MAX_CMDS <= 128) ? 7 :
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(MAX_CMDS <= 256) ? 8 :
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(MAX_CMDS <= 256) ? 8 :
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(MAX_CMDS <= 512) ? 9 : 0; //0 is ilegal
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(MAX_CMDS <= 512) ? 9 : 0; //0 is ilegal
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input clk;
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input clk;
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input reset;
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input reset;
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port GROUP_STUB_AXI;
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port GROUP_STUB_AXI;
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output idle;
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output idle;
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output scrbrd_empty;
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output scrbrd_empty;
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//random parameters
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//random parameters
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integer GROUP_AXI_MASTER_RAND = GROUP_AXI_MASTER_RAND.DEFAULT;
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integer GROUP_AXI_MASTER_RAND = GROUP_AXI_MASTER_RAND.DEFAULT;
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reg AWVALID_pre;
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reg AWVALID_pre;
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reg WVALID_pre;
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reg WVALID_pre;
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wire BREADY_pre;
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wire BREADY_pre;
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reg ARVALID_pre;
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reg ARVALID_pre;
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wire RREADY_pre;
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wire RREADY_pre;
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reg enable = 0;
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reg enable = 0;
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reg rd_enable = 0;
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reg rd_enable = 0;
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reg wr_enable = 0;
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reg wr_enable = 0;
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reg wait_for_write = 0;
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reg wait_for_write = 0;
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reg err_on_wr_resp = 1;
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reg err_on_wr_resp = 1;
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reg err_on_rd_resp = 1;
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reg err_on_rd_resp = 1;
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reg scrbrd_enable = 0;
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reg scrbrd_enable = 0;
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reg [LEN_BITS-1:0] wvalid_cnt;
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reg [LEN_BITS-1:0] wvalid_cnt;
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reg rd_cmd_push = 0;
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reg rd_cmd_push = 0;
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wire rd_cmd_pop;
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wire rd_cmd_pop;
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wire [PEND_BITS:0] rd_cmd_fullness;
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wire [PEND_BITS:0] rd_cmd_fullness;
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wire rd_cmd_empty;
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wire rd_cmd_empty;
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wire rd_cmd_full;
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wire rd_cmd_full;
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reg [ADDR_BITS-1:0] rd_cmd_addr_in;
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reg [ADDR_BITS-1:0] rd_cmd_addr_in;
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reg [LEN_BITS-1:0] rd_cmd_len_in;
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reg [LEN_BITS-1:0] rd_cmd_len_in;
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reg [SIZE_BITS-1:0] rd_cmd_size_in;
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reg [SIZE_BITS-1:0] rd_cmd_size_in;
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wire [ADDR_BITS-1:0] rd_cmd_addr;
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wire [ADDR_BITS-1:0] rd_cmd_addr;
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wire [LEN_BITS-1:0] rd_cmd_len;
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wire [LEN_BITS-1:0] rd_cmd_len;
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wire [SIZE_BITS-1:0] rd_cmd_size;
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wire [SIZE_BITS-1:0] rd_cmd_size;
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reg rd_resp_push = 0;
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reg rd_resp_push = 0;
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wire rd_resp_pop;
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wire rd_resp_pop;
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wire rd_resp_empty;
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wire rd_resp_empty;
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wire rd_resp_full;
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wire rd_resp_full;
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reg [ADDR_BITS-1:0] rd_resp_addr_in;
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reg [ADDR_BITS-1:0] rd_resp_addr_in;
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reg [SIZE_BITS-1:0] rd_resp_size_in;
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reg [SIZE_BITS-1:0] rd_resp_size_in;
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wire [ADDR_BITS-1:0] rd_resp_addr;
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wire [ADDR_BITS-1:0] rd_resp_addr;
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wire [SIZE_BITS-1:0] rd_resp_size;
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wire [SIZE_BITS-1:0] rd_resp_size;
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reg wr_cmd_push = 0;
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reg wr_cmd_push = 0;
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wire wr_cmd_pop;
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wire wr_cmd_pop;
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wire [PEND_BITS:0] wr_cmd_fullness;
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wire [PEND_BITS:0] wr_cmd_fullness;
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wire wr_cmd_empty;
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wire wr_cmd_empty;
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wire wr_cmd_full;
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wire wr_cmd_full;
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reg [ADDR_BITS-1:0] wr_cmd_addr_in;
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reg [ADDR_BITS-1:0] wr_cmd_addr_in;
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reg [LEN_BITS-1:0] wr_cmd_len_in;
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reg [LEN_BITS-1:0] wr_cmd_len_in;
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reg [SIZE_BITS-1:0] wr_cmd_size_in;
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reg [SIZE_BITS-1:0] wr_cmd_size_in;
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wire [ADDR_BITS-1:0] wr_cmd_addr;
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wire [ADDR_BITS-1:0] wr_cmd_addr;
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wire [LEN_BITS-1:0] wr_cmd_len;
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wire [LEN_BITS-1:0] wr_cmd_len;
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wire [SIZE_BITS-1:0] wr_cmd_size;
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wire [SIZE_BITS-1:0] wr_cmd_size;
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reg wr_data_push = 0;
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reg wr_data_push = 0;
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wire wr_data_pop;
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wire wr_data_pop;
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wire [PEND_BITS:0] wr_data_fullness;
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wire [PEND_BITS:0] wr_data_fullness;
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wire wr_data_empty;
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wire wr_data_empty;
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wire wr_data_full;
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wire wr_data_full;
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reg [ADDR_BITS-1:0] wr_data_addr_in;
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reg [ADDR_BITS-1:0] wr_data_addr_in;
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reg [LEN_BITS-1:0] wr_data_len_in;
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reg [LEN_BITS-1:0] wr_data_len_in;
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reg [SIZE_BITS-1:0] wr_data_size_in;
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reg [SIZE_BITS-1:0] wr_data_size_in;
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wire [ADDR_BITS-1:0] wr_data_addr;
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wire [ADDR_BITS-1:0] wr_data_addr;
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wire [LEN_BITS-1:0] wr_data_len;
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wire [LEN_BITS-1:0] wr_data_len;
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wire [SIZE_BITS-1:0] wr_data_size;
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wire [SIZE_BITS-1:0] wr_data_size;
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wire [DATA_BITS/8-1:0] wr_data_strb;
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wire [DATA_BITS/8-1:0] wr_data_strb;
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wire [7:0] wr_data_bytes;
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wire [7:0] wr_data_bytes;
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wire [ADDR_BITS-1:0] wr_data_addr_prog;
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wire [ADDR_BITS-1:0] wr_data_addr_prog;
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wire [7:0] wr_data_offset;
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wire [7:0] wr_data_offset;
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wire wr_resp_push;
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wire wr_resp_push;
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reg wr_resp_pop = 0;
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reg wr_resp_pop = 0;
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wire wr_resp_empty;
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wire wr_resp_empty;
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wire wr_resp_full;
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wire wr_resp_full;
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wire [1:0] wr_resp_resp_in;
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wire [1:0] wr_resp_resp_in;
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wire [1:0] wr_resp_resp;
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wire [1:0] wr_resp_resp;
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reg wr_fifo_push = 0;
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reg wr_fifo_push = 0;
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wire wr_fifo_pop;
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wire wr_fifo_pop;
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wire wr_fifo_empty;
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wire wr_fifo_empty;
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wire wr_fifo_full;
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wire wr_fifo_full;
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reg [DATA_BITS-1:0] wr_fifo_data_in;
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reg [DATA_BITS-1:0] wr_fifo_data_in;
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wire [DATA_BITS-1:0] wr_fifo_data;
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wire [DATA_BITS-1:0] wr_fifo_data;
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wire rd_fifo_push;
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wire rd_fifo_push;
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reg rd_fifo_pop = 0;
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reg rd_fifo_pop = 0;
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wire rd_fifo_empty;
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wire rd_fifo_empty;
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wire rd_fifo_full;
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wire rd_fifo_full;
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wire [DATA_BITS-1:0] rd_fifo_data_in;
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wire [DATA_BITS-1:0] rd_fifo_data_in;
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wire [1:0] rd_fifo_resp_in;
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wire [1:0] rd_fifo_resp_in;
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wire [DATA_BITS-1:0] rd_fifo_data;
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wire [DATA_BITS-1:0] rd_fifo_data;
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wire [1:0] rd_fifo_resp;
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wire [1:0] rd_fifo_resp;
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reg scrbrd_push = 0;
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reg scrbrd_push = 0;
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reg scrbrd_pop = 0;
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reg scrbrd_pop = 0;
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wire scrbrd_empty;
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wire scrbrd_empty;
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wire scrbrd_full;
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wire scrbrd_full;
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reg [ADDR_BITS-1:0] scrbrd_addr_in;
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reg [ADDR_BITS-1:0] scrbrd_addr_in;
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reg [DATA_BITS-1:0] scrbrd_data_in;
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reg [DATA_BITS-1:0] scrbrd_data_in;
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reg [DATA_BITS-1:0] scrbrd_mask_in;
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reg [DATA_BITS-1:0] scrbrd_mask_in;
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wire [ADDR_BITS-1:0] scrbrd_addr;
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wire [ADDR_BITS-1:0] scrbrd_addr;
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wire [DATA_BITS-1:0] scrbrd_data;
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wire [DATA_BITS-1:0] scrbrd_data;
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wire [DATA_BITS-1:0] scrbrd_mask;
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wire [DATA_BITS-1:0] scrbrd_mask;
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integer wr_fullness;
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integer wr_fullness;
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integer rd_fullness;
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integer rd_fullness;
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integer rd_completed;
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integer rd_completed;
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integer wr_completed;
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integer wr_completed;
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integer wr_pend_max = MASTER_PEND;
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integer wr_pend_max = MASTER_PEND;
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integer rd_pend_max = MASTER_PEND;
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integer rd_pend_max = MASTER_PEND;
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wire wr_hold;
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wire wr_hold;
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wire rd_hold;
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wire rd_hold;
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integer rand_chk_num = 0;
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integer rand_chk_num = 0;
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assign idle = rd_cmd_empty & rd_resp_empty & wr_cmd_empty & wr_data_empty & wr_resp_empty;
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assign idle = rd_cmd_empty & rd_resp_empty & wr_cmd_empty & wr_data_empty & wr_resp_empty;
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always @(rand_chk_num)
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always @(rand_chk_num)
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if (rand_chk_num > 0)
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if (rand_chk_num > 0)
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insert_rand_chk_loop(rand_chk_num);
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insert_rand_chk_loop(rand_chk_num);
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always @(posedge enable)
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always @(posedge enable)
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begin
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begin
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@(posedge clk);
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@(posedge clk);
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wr_enable = 1;
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wr_enable = 1;
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repeat (50) @(posedge clk);
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repeat (50) @(posedge clk);
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rd_enable = 1;
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rd_enable = 1;
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end
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end
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//for incremental data
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//for incremental data
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reg [DATA_BITS-1:0] base_data = 0;
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reg [DATA_BITS-1:0] base_data = 0;
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integer ww;
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integer ww;
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initial
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initial
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begin
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begin
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ww=0;
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ww=0;
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while (ww < DATA_BITS/8)
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while (ww < DATA_BITS/8)
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begin
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begin
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base_data = base_data + ((MASTER_NUM + ww) << (ww*8));
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base_data = base_data + ((MASTER_NUM + ww) << (ww*8));
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ww = ww + 1;
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ww = ww + 1;
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end
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end
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end
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end
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assign rd_cmd_pop = ARVALID & ARREADY;
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assign rd_cmd_pop = ARVALID & ARREADY;
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assign rd_resp_pop = RVALID & RREADY & RLAST;
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assign rd_resp_pop = RVALID & RREADY & RLAST;
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assign rd_fifo_push = RVALID & RREADY;
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assign rd_fifo_push = RVALID & RREADY;
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assign wr_cmd_pop = AWVALID & AWREADY;
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assign wr_cmd_pop = AWVALID & AWREADY;
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assign wr_data_pop = WVALID & WREADY & WLAST;
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assign wr_data_pop = WVALID & WREADY & WLAST;
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assign wr_fifo_pop = WVALID & WREADY;
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assign wr_fifo_pop = WVALID & WREADY;
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assign wr_resp_push = BVALID & BREADY;
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assign wr_resp_push = BVALID & BREADY;
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assign RREADY_pre = 1;
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assign RREADY_pre = 1;
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assign BREADY_pre = 1;
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assign BREADY_pre = 1;
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always @(posedge clk or posedge reset)
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always @(posedge clk or posedge reset)
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if (reset)
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if (reset)
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AWVALID_pre <= #FFD 1'b0;
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AWVALID_pre <= #FFD 1'b0;
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else if ((wr_cmd_fullness == 1) & wr_cmd_pop)
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else if ((wr_cmd_fullness == 1) & wr_cmd_pop)
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AWVALID_pre <= #FFD 1'b0;
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AWVALID_pre <= #FFD 1'b0;
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else if ((!wr_cmd_empty) & wr_enable)
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else if ((!wr_cmd_empty) & wr_enable)
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AWVALID_pre <= #FFD 1'b1;
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AWVALID_pre <= #FFD 1'b1;
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assign AWADDR = wr_cmd_addr;
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assign AWADDR = wr_cmd_addr;
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assign AWLEN = wr_cmd_len;
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assign AWLEN = wr_cmd_len;
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assign AWSIZE = wr_cmd_size;
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assign AWSIZE = wr_cmd_size;
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assign AWID = MASTER_ID;
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assign AWID = MASTER_ID;
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assign AWBURST = 2'd1; //INCR only
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assign AWBURST = 2'd1; //INCR only
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assign AWCACHE = 4'd0; //not supported
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assign AWCACHE = 4'd0; //not supported
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assign AWPROT = 4'd0; //not supported
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assign AWPROT = 4'd0; //not supported
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assign AWLOCK = 2'd0; //not supported
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assign AWLOCK = 2'd0; //not supported
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always @(posedge clk or posedge reset)
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always @(posedge clk or posedge reset)
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if (reset)
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if (reset)
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ARVALID_pre <= #FFD 1'b0;
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ARVALID_pre <= #FFD 1'b0;
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else if (((rd_cmd_fullness == 1)) & rd_cmd_pop)
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else if (((rd_cmd_fullness == 1)) & rd_cmd_pop)
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ARVALID_pre <= #FFD 1'b0;
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ARVALID_pre <= #FFD 1'b0;
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else if ((!rd_cmd_empty) & rd_enable)
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else if ((!rd_cmd_empty) & rd_enable)
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ARVALID_pre <= #FFD 1'b1;
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ARVALID_pre <= #FFD 1'b1;
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assign ARADDR = rd_cmd_addr;
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assign ARADDR = rd_cmd_addr;
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assign ARLEN = rd_cmd_len;
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assign ARLEN = rd_cmd_len;
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assign ARSIZE = rd_cmd_size;
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assign ARSIZE = rd_cmd_size;
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assign ARID = MASTER_ID;
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assign ARID = MASTER_ID;
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assign ARBURST = 2'd1; //INCR only
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assign ARBURST = 2'd1; //INCR only
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assign ARCACHE = 4'd0; //not supported
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assign ARCACHE = 4'd0; //not supported
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assign ARPROT = 4'd0; //not supported
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assign ARPROT = 4'd0; //not supported
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assign ARLOCK = 2'd0; //not supported
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assign ARLOCK = 2'd0; //not supported
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assign rd_fifo_data_in = RDATA;
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assign rd_fifo_data_in = RDATA;
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assign rd_fifo_resp_in = RRESP;
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assign rd_fifo_resp_in = RRESP;
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assign wr_data_bytes = 1'b1 << wr_data_size;
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assign wr_data_bytes = 1'b1 << wr_data_size;
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assign wr_data_strb =
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assign wr_data_strb =
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wr_data_size == 'd0 ? 1'b1 :
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wr_data_size == 'd0 ? 1'b1 :
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wr_data_size == 'd1 ? 2'b11 :
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wr_data_size == 'd1 ? 2'b11 :
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wr_data_size == 'd2 ? 4'b1111 :
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wr_data_size == 'd2 ? 4'b1111 :
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wr_data_size == 'd3 ? {8{1'b1}} :
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wr_data_size == 'd3 ? {8{1'b1}} :
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wr_data_size == 'd4 ? {16{1'b1}} : 'd0;
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wr_data_size == 'd4 ? {16{1'b1}} : 'd0;
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assign wr_data_addr_prog = wr_data_addr + (wvalid_cnt * wr_data_bytes);
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assign wr_data_addr_prog = wr_data_addr + (wvalid_cnt * wr_data_bytes);
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always @(posedge clk or posedge reset)
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always @(posedge clk or posedge reset)
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if (reset)
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if (reset)
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WVALID_pre <= #FFD 1'b0;
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WVALID_pre <= #FFD 1'b0;
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else if ((wr_data_fullness == 1) & wr_data_pop)
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else if ((wr_data_fullness == 1) & wr_data_pop)
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WVALID_pre <= #FFD 1'b0;
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WVALID_pre <= #FFD 1'b0;
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else if ((!wr_data_empty) & wr_enable)
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else if ((!wr_data_empty) & wr_enable)
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WVALID_pre <= #FFD 1'b1;
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WVALID_pre <= #FFD 1'b1;
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assign wr_data_offset = wr_data_addr_prog[DATA_LOG-1:0];
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assign wr_data_offset = wr_data_addr_prog[DATA_LOG-1:0];
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|
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assign WID = MASTER_ID;
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assign WID = MASTER_ID;
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assign WDATA = wr_fifo_empty ? 0 : wr_fifo_data;
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assign WDATA = wr_fifo_empty ? 0 : wr_fifo_data;
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assign WSTRB = wr_data_strb << wr_data_offset;
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assign WSTRB = wr_data_strb << wr_data_offset;
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always @(posedge clk or posedge reset)
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always @(posedge clk or posedge reset)
|
if (reset)
|
if (reset)
|
wvalid_cnt <= #FFD {LEN_BITS{1'b0}};
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wvalid_cnt <= #FFD {LEN_BITS{1'b0}};
|
else if (wr_data_pop)
|
else if (wr_data_pop)
|
wvalid_cnt <= #FFD {LEN_BITS{1'b0}};
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wvalid_cnt <= #FFD {LEN_BITS{1'b0}};
|
else if (WVALID & WREADY)
|
else if (WVALID & WREADY)
|
wvalid_cnt <= #FFD wvalid_cnt + 1'b1;
|
wvalid_cnt <= #FFD wvalid_cnt + 1'b1;
|
|
|
assign WLAST = WVALID & (wvalid_cnt == wr_data_len);
|
assign WLAST = WVALID & (wvalid_cnt == wr_data_len);
|
|
|
assign wr_resp_resp_in = BRESP;
|
assign wr_resp_resp_in = BRESP;
|
|
|
always @(posedge clk or posedge reset)
|
always @(posedge clk or posedge reset)
|
if (reset)
|
if (reset)
|
begin
|
begin
|
wr_fullness <= #FFD 0;
|
wr_fullness <= #FFD 0;
|
rd_fullness <= #FFD 0;
|
rd_fullness <= #FFD 0;
|
rd_completed <= #FFD 0;
|
rd_completed <= #FFD 0;
|
wr_completed <= #FFD 0;
|
wr_completed <= #FFD 0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
wr_fullness <= #FFD wr_fullness + wr_cmd_pop - wr_resp_push;
|
wr_fullness <= #FFD wr_fullness + wr_cmd_pop - wr_resp_push;
|
rd_fullness <= #FFD rd_fullness + rd_cmd_pop - rd_resp_pop;
|
rd_fullness <= #FFD rd_fullness + rd_cmd_pop - rd_resp_pop;
|
rd_completed <= #FFD rd_completed + rd_resp_pop;
|
rd_completed <= #FFD rd_completed + rd_resp_pop;
|
wr_completed <= #FFD wr_completed + wr_resp_push;
|
wr_completed <= #FFD wr_completed + wr_resp_push;
|
end
|
end
|
|
|
assign wr_hold = wr_fullness >= wr_pend_max;
|
assign wr_hold = wr_fullness >= wr_pend_max;
|
assign rd_hold = (rd_fullness >= rd_pend_max) | (wait_for_write & (wr_completed <= rd_completed + rd_fullness));
|
assign rd_hold = (rd_fullness >= rd_pend_max) | (wait_for_write & (wr_completed <= rd_completed + rd_fullness));
|
|
|
|
|
|
|
task insert_rd_cmd;
|
task insert_rd_cmd;
|
input [ADDR_BITS-1:0] addr;
|
input [ADDR_BITS-1:0] addr;
|
input [LEN_BITS-1:0] len;
|
input [LEN_BITS-1:0] len;
|
input [SIZE_BITS-1:0] size;
|
input [SIZE_BITS-1:0] size;
|
|
|
begin
|
begin
|
rd_cmd_addr_in = addr;
|
rd_cmd_addr_in = addr;
|
rd_cmd_len_in = len;
|
rd_cmd_len_in = len;
|
rd_cmd_size_in = size;
|
rd_cmd_size_in = size;
|
rd_resp_addr_in = addr;
|
rd_resp_addr_in = addr;
|
rd_resp_size_in = size;
|
rd_resp_size_in = size;
|
|
|
if (rd_cmd_full) enable = 1; //start stub not started yet
|
if (rd_cmd_full) enable = 1; //start stub not started yet
|
|
|
#FFD; wait ((!rd_cmd_full) & (!rd_resp_full));
|
#FFD; wait ((!rd_cmd_full) & (!rd_resp_full));
|
@(negedge clk); #FFD;
|
@(negedge clk); #FFD;
|
rd_cmd_push = 1;
|
rd_cmd_push = 1;
|
rd_resp_push = 1;
|
rd_resp_push = 1;
|
@(posedge clk); #FFD;
|
@(posedge clk); #FFD;
|
rd_cmd_push = 0;
|
rd_cmd_push = 0;
|
rd_resp_push = 0;
|
rd_resp_push = 0;
|
end
|
end
|
endtask
|
endtask
|
|
|
task insert_wr_cmd;
|
task insert_wr_cmd;
|
input [ADDR_BITS-1:0] addr;
|
input [ADDR_BITS-1:0] addr;
|
input [LEN_BITS-1:0] len;
|
input [LEN_BITS-1:0] len;
|
input [SIZE_BITS-1:0] size;
|
input [SIZE_BITS-1:0] size;
|
|
|
begin
|
begin
|
wr_cmd_addr_in = addr;
|
wr_cmd_addr_in = addr;
|
wr_cmd_len_in = len;
|
wr_cmd_len_in = len;
|
wr_cmd_size_in = size;
|
wr_cmd_size_in = size;
|
wr_data_addr_in = addr;
|
wr_data_addr_in = addr;
|
wr_data_len_in = len;
|
wr_data_len_in = len;
|
wr_data_size_in = size;
|
wr_data_size_in = size;
|
|
|
if (wr_cmd_full) enable = 1; //start stub not started yet
|
if (wr_cmd_full) enable = 1; //start stub not started yet
|
|
|
#FFD; wait ((!wr_cmd_full) & (!wr_data_full));
|
#FFD; wait ((!wr_cmd_full) & (!wr_data_full));
|
@(negedge clk); #FFD;
|
@(negedge clk); #FFD;
|
wr_cmd_push = 1;
|
wr_cmd_push = 1;
|
wr_data_push = 1;
|
wr_data_push = 1;
|
@(posedge clk); #FFD;
|
@(posedge clk); #FFD;
|
wr_cmd_push = 0;
|
wr_cmd_push = 0;
|
wr_data_push = 0;
|
wr_data_push = 0;
|
end
|
end
|
endtask
|
endtask
|
|
|
task insert_wr_data;
|
task insert_wr_data;
|
input [DATA_BITS-1:0] wdata;
|
input [DATA_BITS-1:0] wdata;
|
|
|
begin
|
begin
|
wr_fifo_data_in = wdata;
|
wr_fifo_data_in = wdata;
|
|
|
#FFD; wait (!wr_fifo_full);
|
#FFD; wait (!wr_fifo_full);
|
@(negedge clk); #FFD;
|
@(negedge clk); #FFD;
|
wr_fifo_push = 1;
|
wr_fifo_push = 1;
|
@(posedge clk); #FFD;
|
@(posedge clk); #FFD;
|
wr_fifo_push = 0;
|
wr_fifo_push = 0;
|
end
|
end
|
endtask
|
endtask
|
|
|
task insert_wr_incr_data;
|
task insert_wr_incr_data;
|
input [ADDR_BITS-1:0] addr;
|
input [ADDR_BITS-1:0] addr;
|
input [LEN_BITS-1:0] len;
|
input [LEN_BITS-1:0] len;
|
input [SIZE_BITS-1:0] size;
|
input [SIZE_BITS-1:0] size;
|
|
|
integer valid_cnt;
|
integer valid_cnt;
|
integer wdata_cnt;
|
integer wdata_cnt;
|
reg [7:0] data_cnt;
|
reg [7:0] data_cnt;
|
integer bytes;
|
integer bytes;
|
reg [DATA_BITS-1:0] add_data;
|
reg [DATA_BITS-1:0] add_data;
|
reg [DATA_BITS-1:0] next_data;
|
reg [DATA_BITS-1:0] next_data;
|
begin
|
begin
|
//insert data
|
//insert data
|
valid_cnt = 0;
|
valid_cnt = 0;
|
while (valid_cnt <= len)
|
while (valid_cnt <= len)
|
begin
|
begin
|
bytes = 1'b1 << size;
|
bytes = 1'b1 << size;
|
wdata_cnt = valid_cnt+(addr[DATA_LOG-1:0]/bytes);
|
wdata_cnt = valid_cnt+(addr[DATA_LOG-1:0]/bytes);
|
data_cnt = ((wdata_cnt)/(DATA_BITS/(bytes*8))) * (DATA_BITS/8);
|
data_cnt = ((wdata_cnt)/(DATA_BITS/(bytes*8))) * (DATA_BITS/8);
|
add_data = {DATA_BITS/8{data_cnt}};
|
add_data = {DATA_BITS/8{data_cnt}};
|
next_data = (use_addr_base ? addr : base_data) + add_data;
|
next_data = (use_addr_base ? addr : base_data) + add_data;
|
insert_wr_data(next_data);
|
insert_wr_data(next_data);
|
valid_cnt = valid_cnt+1;
|
valid_cnt = valid_cnt+1;
|
end
|
end
|
//insert command
|
//insert command
|
insert_wr_cmd(addr, len, size);
|
insert_wr_cmd(addr, len, size);
|
end
|
end
|
endtask
|
endtask
|
|
|
task insert_scrbrd;
|
task insert_scrbrd;
|
input [ADDR_BITS-1:0] addr;
|
input [ADDR_BITS-1:0] addr;
|
input [DATA_BITS-1:0] data;
|
input [DATA_BITS-1:0] data;
|
input [DATA_BITS-1:0] mask;
|
input [DATA_BITS-1:0] mask;
|
begin
|
begin
|
scrbrd_enable = 1;
|
scrbrd_enable = 1;
|
scrbrd_addr_in = addr;
|
scrbrd_addr_in = addr;
|
scrbrd_data_in = data;
|
scrbrd_data_in = data;
|
scrbrd_mask_in = mask;
|
scrbrd_mask_in = mask;
|
|
|
#FFD; wait (!scrbrd_full);
|
#FFD; wait (!scrbrd_full);
|
@(negedge clk); #FFD;
|
@(negedge clk); #FFD;
|
scrbrd_push = 1;
|
scrbrd_push = 1;
|
@(posedge clk); #FFD;
|
@(posedge clk); #FFD;
|
scrbrd_push = 0;
|
scrbrd_push = 0;
|
end
|
end
|
endtask
|
endtask
|
|
|
task insert_scrbrd_incr_data;
|
task insert_scrbrd_incr_data;
|
input [ADDR_BITS-1:0] addr;
|
input [ADDR_BITS-1:0] addr;
|
input [LEN_BITS-1:0] len;
|
input [LEN_BITS-1:0] len;
|
input [SIZE_BITS-1:0] size;
|
input [SIZE_BITS-1:0] size;
|
|
|
integer valid_cnt;
|
integer valid_cnt;
|
integer wdata_cnt;
|
integer wdata_cnt;
|
reg [7:0] data_cnt;
|
reg [7:0] data_cnt;
|
integer bytes;
|
integer bytes;
|
reg [DATA_BITS-1:0] add_data;
|
reg [DATA_BITS-1:0] add_data;
|
reg [DATA_BITS-1:0] next_data;
|
reg [DATA_BITS-1:0] next_data;
|
reg [DATA_BITS:0] strb;
|
reg [DATA_BITS:0] strb;
|
reg [DATA_BITS-1:0] mask;
|
reg [DATA_BITS-1:0] mask;
|
reg [ADDR_BITS-1:0] next_addr;
|
reg [ADDR_BITS-1:0] next_addr;
|
begin
|
begin
|
valid_cnt = 0;
|
valid_cnt = 0;
|
while (valid_cnt <= len)
|
while (valid_cnt <= len)
|
begin
|
begin
|
bytes = 1'b1 << size;
|
bytes = 1'b1 << size;
|
wdata_cnt = valid_cnt+(addr[DATA_LOG-1:0]/bytes);
|
wdata_cnt = valid_cnt+(addr[DATA_LOG-1:0]/bytes);
|
data_cnt = ((wdata_cnt)/(DATA_BITS/(bytes*8))) * (DATA_BITS/8);
|
data_cnt = ((wdata_cnt)/(DATA_BITS/(bytes*8))) * (DATA_BITS/8);
|
add_data = {DATA_BITS/8{data_cnt}};
|
add_data = {DATA_BITS/8{data_cnt}};
|
next_data = (use_addr_base ? addr : base_data) + add_data;
|
next_data = (use_addr_base ? addr : base_data) + add_data;
|
next_addr = addr + (bytes * valid_cnt);
|
next_addr = addr + (bytes * valid_cnt);
|
strb = (1 << (bytes*8)) - 1;
|
strb = (1 << (bytes*8)) - 1;
|
mask = strb << (next_addr[DATA_LOG-1:0]*8);
|
mask = strb << (next_addr[DATA_LOG-1:0]*8);
|
insert_scrbrd(next_addr, next_data, mask);
|
insert_scrbrd(next_addr, next_data, mask);
|
valid_cnt = valid_cnt+1;
|
valid_cnt = valid_cnt+1;
|
end
|
end
|
end
|
end
|
endtask
|
endtask
|
|
|
task insert_rd_scrbrd;
|
task insert_rd_scrbrd;
|
input [ADDR_BITS-1:0] addr;
|
input [ADDR_BITS-1:0] addr;
|
input [LEN_BITS-1:0] len;
|
input [LEN_BITS-1:0] len;
|
input [SIZE_BITS-1:0] size;
|
input [SIZE_BITS-1:0] size;
|
|
|
begin
|
begin
|
insert_scrbrd_incr_data(addr, len, size);
|
insert_scrbrd_incr_data(addr, len, size);
|
insert_rd_cmd(addr, len, size);
|
insert_rd_cmd(addr, len, size);
|
end
|
end
|
endtask
|
endtask
|
|
|
task insert_wr_rd_scrbrd;
|
task insert_wr_rd_scrbrd;
|
input [ADDR_BITS-1:0] addr;
|
input [ADDR_BITS-1:0] addr;
|
input [LEN_BITS-1:0] len;
|
input [LEN_BITS-1:0] len;
|
input [SIZE_BITS-1:0] size;
|
input [SIZE_BITS-1:0] size;
|
|
|
begin
|
begin
|
wait_for_write=1;
|
wait_for_write=1;
|
insert_wr_incr_data(addr, len, size);
|
insert_wr_incr_data(addr, len, size);
|
insert_rd_scrbrd(addr, len, size);
|
insert_rd_scrbrd(addr, len, size);
|
end
|
end
|
endtask
|
endtask
|
|
|
task insert_wr_rd_scrbrd_rand;
|
task insert_wr_rd_scrbrd_rand;
|
reg [ADDR_BITS-1:0] addr;
|
reg [ADDR_BITS-1:0] addr;
|
reg [LEN_BITS-1:0] len;
|
reg [LEN_BITS-1:0] len;
|
reg [SIZE_BITS-1:0] size;
|
reg [SIZE_BITS-1:0] size;
|
|
|
|
integer size_bytes;
|
|
integer burst_bytes;
|
begin
|
begin
|
if (DATA_BITS==32) size_max = 2'b10;
|
if (DATA_BITS==32) size_max = 2'b10;
|
len = rand(len_min, len_max);
|
len = rand(len_min, len_max);
|
size = rand(size_min, size_max);
|
size = rand(size_min, size_max);
|
addr = rand_align(addr_min, addr_max, 1 << size);
|
size_bytes = 1 << size;
|
|
burst_bytes = size_bytes * (len+1);
|
|
addr = rand_align(addr_min, addr_max, size_bytes);
|
|
if (addr[11:0] + burst_bytes > 16'h1000) //don't cross 4KByte page
|
|
begin
|
|
addr = addr - burst_bytes;
|
|
end
|
|
|
if (ahb_bursts)
|
if (ahb_bursts)
|
begin
|
begin
|
len =
|
len =
|
len[3] ? 15 :
|
len[3] ? 15 :
|
len[2] ? 7 :
|
len[2] ? 7 :
|
len[1] ? 3 : 0;
|
len[1] ? 3 : 0;
|
if (len > 0)
|
if (len > 0)
|
size = (DATA_BITS == 64) ? 2'b11 : 2'b10; //AHB bursts always full data
|
size = (DATA_BITS == 64) ? 2'b11 : 2'b10; //AHB bursts always full data
|
|
|
addr = align(addr, EXPR(DATA_BITS/8)*(len+1)); //address aligned to burst size
|
addr = align(addr, EXPR(DATA_BITS/8)*(len+1)); //address aligned to burst size
|
end
|
end
|
insert_wr_rd_scrbrd(addr, len, size);
|
insert_wr_rd_scrbrd(addr, len, size);
|
end
|
end
|
endtask
|
endtask
|
|
|
task insert_rand_chk;
|
task insert_rand_chk;
|
input [31:0] num;
|
input [31:0] num;
|
|
|
rand_chk_num = num;
|
rand_chk_num = num;
|
endtask
|
endtask
|
|
|
task insert_rand_chk_loop;
|
task insert_rand_chk_loop;
|
input [31:0] num;
|
input [31:0] num;
|
|
|
integer i;
|
integer i;
|
begin
|
begin
|
i = 0;
|
i = 0;
|
while (i < num)
|
while (i < num)
|
begin
|
begin
|
insert_wr_rd_scrbrd_rand;
|
insert_wr_rd_scrbrd_rand;
|
i = i + 1;
|
i = i + 1;
|
end
|
end
|
end
|
end
|
endtask
|
endtask
|
|
|
task insert_wr_single;
|
task insert_wr_single;
|
input [ADDR_BITS-1:0] addr;
|
input [ADDR_BITS-1:0] addr;
|
input [DATA_BITS-1:0] wdata;
|
input [DATA_BITS-1:0] wdata;
|
|
|
reg [SIZE_BITS-1:0] size;
|
reg [SIZE_BITS-1:0] size;
|
begin
|
begin
|
size = EXPR((DATA_BITS/32)+1);
|
size = EXPR((DATA_BITS/32)+1);
|
insert_wr_data(wdata);
|
insert_wr_data(wdata);
|
insert_wr_cmd(addr, 0, size);
|
insert_wr_cmd(addr, 0, size);
|
end
|
end
|
endtask
|
endtask
|
|
|
task get_rd_resp;
|
task get_rd_resp;
|
output [DATA_BITS-1:0] rdata;
|
output [DATA_BITS-1:0] rdata;
|
output [1:0] resp;
|
output [1:0] resp;
|
|
|
reg [DATA_BITS-1:0] rdata;
|
reg [DATA_BITS-1:0] rdata;
|
reg [1:0] resp;
|
reg [1:0] resp;
|
begin
|
begin
|
#FFD; wait (!rd_fifo_empty);
|
#FFD; wait (!rd_fifo_empty);
|
rdata = rd_fifo_data;
|
rdata = rd_fifo_data;
|
resp = rd_fifo_resp;
|
resp = rd_fifo_resp;
|
@(negedge clk); #FFD;
|
@(negedge clk); #FFD;
|
rd_fifo_pop = 1;
|
rd_fifo_pop = 1;
|
@(posedge clk); #FFD;
|
@(posedge clk); #FFD;
|
rd_fifo_pop = 0;
|
rd_fifo_pop = 0;
|
if ((resp != 2'b00) && (err_on_rd_resp))
|
if ((resp != 2'b00) && (err_on_rd_resp))
|
$display("PREFIX_MASTER%0d: RRESP_ERROR: Received RRESP 2'b%0b.\tTime: %0d ns.", MASTER_NUM, resp, $time);
|
$display("PREFIX_MASTER%0d: RRESP_ERROR: Received RRESP 2'b%0b.\tTime: %0d ns.", MASTER_NUM, resp, $time);
|
end
|
end
|
endtask
|
endtask
|
|
|
task get_scrbrd;
|
task get_scrbrd;
|
output [ADDR_BITS-1:0] addr;
|
output [ADDR_BITS-1:0] addr;
|
output [DATA_BITS-1:0] rdata;
|
output [DATA_BITS-1:0] rdata;
|
output [DATA_BITS-1:0] mask;
|
output [DATA_BITS-1:0] mask;
|
|
|
reg [ADDR_BITS-1:0] addr;
|
reg [ADDR_BITS-1:0] addr;
|
reg [DATA_BITS-1:0] rdata;
|
reg [DATA_BITS-1:0] rdata;
|
reg [DATA_BITS-1:0] mask;
|
reg [DATA_BITS-1:0] mask;
|
begin
|
begin
|
#FFD; wait (!scrbrd_empty);
|
#FFD; wait (!scrbrd_empty);
|
addr = scrbrd_addr;
|
addr = scrbrd_addr;
|
rdata = scrbrd_data;
|
rdata = scrbrd_data;
|
mask = scrbrd_mask;
|
mask = scrbrd_mask;
|
@(negedge clk); #FFD;
|
@(negedge clk); #FFD;
|
scrbrd_pop = 1;
|
scrbrd_pop = 1;
|
@(posedge clk); #FFD;
|
@(posedge clk); #FFD;
|
scrbrd_pop = 0;
|
scrbrd_pop = 0;
|
end
|
end
|
endtask
|
endtask
|
|
|
task get_wr_resp;
|
task get_wr_resp;
|
output [1:0] resp;
|
output [1:0] resp;
|
|
|
reg [1:0] resp;
|
reg [1:0] resp;
|
begin
|
begin
|
#FFD; wait (!wr_resp_empty);
|
#FFD; wait (!wr_resp_empty);
|
resp = wr_resp_resp;
|
resp = wr_resp_resp;
|
@(negedge clk); #FFD;
|
@(negedge clk); #FFD;
|
wr_resp_pop = 1;
|
wr_resp_pop = 1;
|
@(posedge clk); #FFD;
|
@(posedge clk); #FFD;
|
wr_resp_pop = 0;
|
wr_resp_pop = 0;
|
if ((resp != 2'b00) && (err_on_wr_resp))
|
if ((resp != 2'b00) && (err_on_wr_resp))
|
$display("PREFIX_MASTER%0d: BRESP_ERROR: Received BRESP 2'b%0b.\tTime: %0d ns.", MASTER_NUM, resp, $time);
|
$display("PREFIX_MASTER%0d: BRESP_ERROR: Received BRESP 2'b%0b.\tTime: %0d ns.", MASTER_NUM, resp, $time);
|
end
|
end
|
endtask
|
endtask
|
|
|
task insert_rd_single;
|
task insert_rd_single;
|
input [ADDR_BITS-1:0] addr;
|
input [ADDR_BITS-1:0] addr;
|
|
|
reg [SIZE_BITS-1:0] size;
|
reg [SIZE_BITS-1:0] size;
|
begin
|
begin
|
size = EXPR((DATA_BITS/32)+1);
|
size = EXPR((DATA_BITS/32)+1);
|
insert_rd_cmd(addr, 0, size);
|
insert_rd_cmd(addr, 0, size);
|
end
|
end
|
endtask
|
endtask
|
|
|
task read_single_ack;
|
task read_single_ack;
|
input [ADDR_BITS-1:0] addr;
|
input [ADDR_BITS-1:0] addr;
|
output [DATA_BITS-1:0] rdata;
|
output [DATA_BITS-1:0] rdata;
|
output [1:0] resp;
|
output [1:0] resp;
|
|
|
reg [1:0] resp;
|
reg [1:0] resp;
|
begin
|
begin
|
insert_rd_single(addr);
|
insert_rd_single(addr);
|
get_rd_resp(rdata, resp);
|
get_rd_resp(rdata, resp);
|
end
|
end
|
endtask
|
endtask
|
|
|
task write_single_ack;
|
task write_single_ack;
|
input [ADDR_BITS-1:0] addr;
|
input [ADDR_BITS-1:0] addr;
|
input [DATA_BITS-1:0] wdata;
|
input [DATA_BITS-1:0] wdata;
|
output [1:0] resp;
|
output [1:0] resp;
|
|
|
reg [1:0] resp;
|
reg [1:0] resp;
|
begin
|
begin
|
insert_wr_single(addr, wdata);
|
insert_wr_single(addr, wdata);
|
get_wr_resp(resp);
|
get_wr_resp(resp);
|
end
|
end
|
endtask
|
endtask
|
|
|
task read_single;
|
task read_single;
|
input [ADDR_BITS-1:0] addr;
|
input [ADDR_BITS-1:0] addr;
|
output [DATA_BITS-1:0] rdata;
|
output [DATA_BITS-1:0] rdata;
|
|
|
reg [1:0] resp;
|
reg [1:0] resp;
|
begin
|
begin
|
read_single_ack(addr, rdata, resp);
|
read_single_ack(addr, rdata, resp);
|
end
|
end
|
endtask
|
endtask
|
|
|
task check_single;
|
task check_single;
|
input [ADDR_BITS-1:0] addr;
|
input [ADDR_BITS-1:0] addr;
|
input [DATA_BITS-1:0] expected;
|
input [DATA_BITS-1:0] expected;
|
|
|
reg [1:0] resp;
|
reg [1:0] resp;
|
reg [DATA_BITS-1:0] rdata;
|
reg [DATA_BITS-1:0] rdata;
|
begin
|
begin
|
read_single_ack(addr, rdata, resp);
|
read_single_ack(addr, rdata, resp);
|
if (rdata !== expected)
|
if (rdata !== expected)
|
$display("PREFIX_MASTER%0d: CHK_SINGLE_ERROR: Address: 0x%0h, Expected: 0x%0h, Received: 0x%0h.\tTime: %0d ns.", MASTER_NUM, addr, expected, rdata, $time);
|
$display("PREFIX_MASTER%0d: CHK_SINGLE_ERROR: Address: 0x%0h, Expected: 0x%0h, Received: 0x%0h.\tTime: %0d ns.", MASTER_NUM, addr, expected, rdata, $time);
|
end
|
end
|
endtask
|
endtask
|
|
|
task write_and_check_single;
|
task write_and_check_single;
|
input [ADDR_BITS-1:0] addr;
|
input [ADDR_BITS-1:0] addr;
|
input [DATA_BITS-1:0] data;
|
input [DATA_BITS-1:0] data;
|
|
|
begin
|
begin
|
write_single(addr, data);
|
write_single(addr, data);
|
check_single(addr, data);
|
check_single(addr, data);
|
end
|
end
|
endtask
|
endtask
|
|
|
task write_single;
|
task write_single;
|
input [ADDR_BITS-1:0] addr;
|
input [ADDR_BITS-1:0] addr;
|
input [DATA_BITS-1:0] wdata;
|
input [DATA_BITS-1:0] wdata;
|
|
|
reg [1:0] resp;
|
reg [1:0] resp;
|
begin
|
begin
|
write_single_ack(addr, wdata, resp);
|
write_single_ack(addr, wdata, resp);
|
end
|
end
|
endtask
|
endtask
|
|
|
task chk_scrbrd;
|
task chk_scrbrd;
|
reg [ADDR_BITS-1:0] addr;
|
reg [ADDR_BITS-1:0] addr;
|
reg [DATA_BITS-1:0] mask;
|
reg [DATA_BITS-1:0] mask;
|
reg [DATA_BITS-1:0] expected_data;
|
reg [DATA_BITS-1:0] expected_data;
|
reg [DATA_BITS-1:0] rdata;
|
reg [DATA_BITS-1:0] rdata;
|
reg [DATA_BITS-1:0] rdata_masked;
|
reg [DATA_BITS-1:0] rdata_masked;
|
reg [1:0] resp;
|
reg [1:0] resp;
|
|
|
begin
|
begin
|
if (!wr_resp_empty) get_wr_resp(resp);
|
if (!wr_resp_empty) get_wr_resp(resp);
|
get_scrbrd(addr, expected_data, mask);
|
get_scrbrd(addr, expected_data, mask);
|
get_rd_resp(rdata, resp);
|
get_rd_resp(rdata, resp);
|
expected_data = expected_data & mask; //TBD insert z as dontcare (for print)
|
expected_data = expected_data & mask; //TBD insert z as dontcare (for print)
|
rdata_masked = rdata & mask;
|
rdata_masked = rdata & mask;
|
|
|
if (expected_data !== rdata_masked)
|
if (expected_data !== rdata_masked)
|
$display("PREFIX_MASTER%0d: SCRBRD_ERROR: Address: 0x%0h, Expected: 0x%0h, Received: 0x%0h.\tTime: %0d ns.", MASTER_NUM, addr, expected_data, rdata, $time);
|
$display("PREFIX_MASTER%0d: SCRBRD_ERROR: Address: 0x%0h, Expected: 0x%0h, Received: 0x%0h.\tTime: %0d ns.", MASTER_NUM, addr, expected_data, rdata, $time);
|
end
|
end
|
endtask
|
endtask
|
|
|
always @(posedge scrbrd_enable)
|
always @(posedge scrbrd_enable)
|
begin
|
begin
|
while (scrbrd_enable)
|
while (scrbrd_enable)
|
begin
|
begin
|
chk_scrbrd;
|
chk_scrbrd;
|
end
|
end
|
end
|
end
|
|
|
|
|
CREATE prgen_fifo.v DEFCMD(DEFINE STUB)
|
CREATE prgen_fifo.v DEFCMD(DEFINE STUB)
|
prgen_fifo_stub #(ADDR_BITS+LEN_BITS+SIZE_BITS, MAX_CMDS)
|
prgen_fifo_stub #(ADDR_BITS+LEN_BITS+SIZE_BITS, MAX_CMDS)
|
rd_cmd_list(
|
rd_cmd_list(
|
.clk(clk),
|
.clk(clk),
|
.reset(reset),
|
.reset(reset),
|
.push(rd_cmd_push),
|
.push(rd_cmd_push),
|
.pop(rd_cmd_pop),
|
.pop(rd_cmd_pop),
|
.din({
|
.din({
|
rd_cmd_size_in,
|
rd_cmd_size_in,
|
rd_cmd_len_in,
|
rd_cmd_len_in,
|
rd_cmd_addr_in
|
rd_cmd_addr_in
|
}),
|
}),
|
.dout({
|
.dout({
|
rd_cmd_size,
|
rd_cmd_size,
|
rd_cmd_len,
|
rd_cmd_len,
|
rd_cmd_addr
|
rd_cmd_addr
|
}),
|
}),
|
.fullness(rd_cmd_fullness),
|
.fullness(rd_cmd_fullness),
|
.empty(rd_cmd_empty),
|
.empty(rd_cmd_empty),
|
.full(rd_cmd_full)
|
.full(rd_cmd_full)
|
);
|
);
|
|
|
prgen_fifo_stub #(ADDR_BITS+SIZE_BITS, MAX_CMDS)
|
prgen_fifo_stub #(ADDR_BITS+SIZE_BITS, MAX_CMDS)
|
rd_resp_list(
|
rd_resp_list(
|
.clk(clk),
|
.clk(clk),
|
.reset(reset),
|
.reset(reset),
|
.push(rd_resp_push),
|
.push(rd_resp_push),
|
.pop(rd_resp_pop),
|
.pop(rd_resp_pop),
|
.din({
|
.din({
|
rd_resp_addr_in,
|
rd_resp_addr_in,
|
rd_resp_size_in
|
rd_resp_size_in
|
}),
|
}),
|
.dout({
|
.dout({
|
rd_resp_addr,
|
rd_resp_addr,
|
rd_resp_size
|
rd_resp_size
|
}),
|
}),
|
.empty(rd_resp_empty),
|
.empty(rd_resp_empty),
|
.full(rd_resp_full)
|
.full(rd_resp_full)
|
);
|
);
|
|
|
prgen_fifo_stub #(ADDR_BITS+LEN_BITS+SIZE_BITS, MAX_CMDS)
|
prgen_fifo_stub #(ADDR_BITS+LEN_BITS+SIZE_BITS, MAX_CMDS)
|
wr_cmd_list(
|
wr_cmd_list(
|
.clk(clk),
|
.clk(clk),
|
.reset(reset),
|
.reset(reset),
|
.push(wr_cmd_push),
|
.push(wr_cmd_push),
|
.pop(wr_cmd_pop),
|
.pop(wr_cmd_pop),
|
.din({
|
.din({
|
wr_cmd_size_in,
|
wr_cmd_size_in,
|
wr_cmd_len_in,
|
wr_cmd_len_in,
|
wr_cmd_addr_in
|
wr_cmd_addr_in
|
}),
|
}),
|
.dout({
|
.dout({
|
wr_cmd_size,
|
wr_cmd_size,
|
wr_cmd_len,
|
wr_cmd_len,
|
wr_cmd_addr
|
wr_cmd_addr
|
}),
|
}),
|
.fullness(wr_cmd_fullness),
|
.fullness(wr_cmd_fullness),
|
.empty(wr_cmd_empty),
|
.empty(wr_cmd_empty),
|
.full(wr_cmd_full)
|
.full(wr_cmd_full)
|
);
|
);
|
|
|
prgen_fifo_stub #(ADDR_BITS+LEN_BITS+SIZE_BITS, MAX_CMDS)
|
prgen_fifo_stub #(ADDR_BITS+LEN_BITS+SIZE_BITS, MAX_CMDS)
|
wr_data_list(
|
wr_data_list(
|
.clk(clk),
|
.clk(clk),
|
.reset(reset),
|
.reset(reset),
|
.push(wr_data_push),
|
.push(wr_data_push),
|
.pop(wr_data_pop),
|
.pop(wr_data_pop),
|
.din({
|
.din({
|
wr_data_size_in,
|
wr_data_size_in,
|
wr_data_len_in,
|
wr_data_len_in,
|
wr_data_addr_in
|
wr_data_addr_in
|
}),
|
}),
|
.dout({
|
.dout({
|
wr_data_size,
|
wr_data_size,
|
wr_data_len,
|
wr_data_len,
|
wr_data_addr
|
wr_data_addr
|
}),
|
}),
|
.fullness(wr_data_fullness),
|
.fullness(wr_data_fullness),
|
.empty(wr_data_empty),
|
.empty(wr_data_empty),
|
.full(wr_data_full)
|
.full(wr_data_full)
|
);
|
);
|
|
|
prgen_fifo_stub #(2, MAX_CMDS)
|
prgen_fifo_stub #(2, MAX_CMDS)
|
wr_resp_list(
|
wr_resp_list(
|
.clk(clk),
|
.clk(clk),
|
.reset(reset),
|
.reset(reset),
|
.push(wr_resp_push),
|
.push(wr_resp_push),
|
.pop(wr_resp_pop),
|
.pop(wr_resp_pop),
|
.din(wr_resp_resp_in),
|
.din(wr_resp_resp_in),
|
.dout(wr_resp_resp),
|
.dout(wr_resp_resp),
|
.empty(wr_resp_empty),
|
.empty(wr_resp_empty),
|
.full(wr_resp_full)
|
.full(wr_resp_full)
|
);
|
);
|
|
|
|
|
prgen_fifo_stub #(DATA_BITS, MAX_CMDS*EXPR(2^LEN_BITS))
|
prgen_fifo_stub #(DATA_BITS, MAX_CMDS*EXPR(2^LEN_BITS))
|
wr_data_fifo(
|
wr_data_fifo(
|
.clk(clk),
|
.clk(clk),
|
.reset(reset),
|
.reset(reset),
|
.push(wr_fifo_push),
|
.push(wr_fifo_push),
|
.pop(wr_fifo_pop),
|
.pop(wr_fifo_pop),
|
.din(wr_fifo_data_in),
|
.din(wr_fifo_data_in),
|
.dout(wr_fifo_data),
|
.dout(wr_fifo_data),
|
.empty(wr_fifo_empty),
|
.empty(wr_fifo_empty),
|
.full(wr_fifo_full)
|
.full(wr_fifo_full)
|
);
|
);
|
|
|
prgen_fifo_stub #(DATA_BITS+2, MAX_CMDS*EXPR(2^LEN_BITS))
|
prgen_fifo_stub #(DATA_BITS+2, MAX_CMDS*EXPR(2^LEN_BITS))
|
rd_data_fifo(
|
rd_data_fifo(
|
.clk(clk),
|
.clk(clk),
|
.reset(reset),
|
.reset(reset),
|
.push(rd_fifo_push),
|
.push(rd_fifo_push),
|
.pop(rd_fifo_pop),
|
.pop(rd_fifo_pop),
|
.din({
|
.din({
|
rd_fifo_data_in,
|
rd_fifo_data_in,
|
rd_fifo_resp_in
|
rd_fifo_resp_in
|
}),
|
}),
|
.dout({
|
.dout({
|
rd_fifo_data,
|
rd_fifo_data,
|
rd_fifo_resp
|
rd_fifo_resp
|
}),
|
}),
|
.empty(rd_fifo_empty),
|
.empty(rd_fifo_empty),
|
.full(rd_fifo_full)
|
.full(rd_fifo_full)
|
);
|
);
|
|
|
prgen_fifo_stub #(ADDR_BITS+2*DATA_BITS, MAX_CMDS*EXPR(2^LEN_BITS))
|
prgen_fifo_stub #(ADDR_BITS+2*DATA_BITS, MAX_CMDS*EXPR(2^LEN_BITS))
|
scrbrd_fifo(
|
scrbrd_fifo(
|
.clk(clk),
|
.clk(clk),
|
.reset(reset),
|
.reset(reset),
|
.push(scrbrd_push),
|
.push(scrbrd_push),
|
.pop(scrbrd_pop),
|
.pop(scrbrd_pop),
|
.din({
|
.din({
|
scrbrd_addr_in,
|
scrbrd_addr_in,
|
scrbrd_data_in,
|
scrbrd_data_in,
|
scrbrd_mask_in
|
scrbrd_mask_in
|
}),
|
}),
|
.dout({
|
.dout({
|
scrbrd_addr,
|
scrbrd_addr,
|
scrbrd_data,
|
scrbrd_data,
|
scrbrd_mask
|
scrbrd_mask
|
}),
|
}),
|
.empty(scrbrd_empty),
|
.empty(scrbrd_empty),
|
.full(scrbrd_full)
|
.full(scrbrd_full)
|
);
|
);
|
|
|
|
|
CREATE axi_master_stall.v
|
CREATE axi_master_stall.v
|
PREFIX_stall
|
PREFIX_stall
|
PREFIX_stall (
|
PREFIX_stall (
|
.clk(clk),
|
.clk(clk),
|
.reset(reset),
|
.reset(reset),
|
|
|
.rd_hold(rd_hold),
|
.rd_hold(rd_hold),
|
.wr_hold(wr_hold),
|
.wr_hold(wr_hold),
|
|
|
.ARVALID_pre(ARVALID_pre),
|
.ARVALID_pre(ARVALID_pre),
|
.RREADY_pre(RREADY_pre),
|
.RREADY_pre(RREADY_pre),
|
.AWVALID_pre(AWVALID_pre),
|
.AWVALID_pre(AWVALID_pre),
|
.WVALID_pre(WVALID_pre),
|
.WVALID_pre(WVALID_pre),
|
.BREADY_pre(BREADY_pre),
|
.BREADY_pre(BREADY_pre),
|
|
|
.ARREADY(ARREADY),
|
.ARREADY(ARREADY),
|
.AWREADY(AWREADY),
|
.AWREADY(AWREADY),
|
.WREADY(WREADY),
|
.WREADY(WREADY),
|
|
|
.ARVALID(ARVALID),
|
.ARVALID(ARVALID),
|
.RREADY(RREADY),
|
.RREADY(RREADY),
|
.AWVALID(AWVALID),
|
.AWVALID(AWVALID),
|
.WVALID(WVALID),
|
.WVALID(WVALID),
|
.BREADY(BREADY)
|
.BREADY(BREADY)
|
);
|
);
|
|
|
|
|
endmodule
|
endmodule
|
|
|
|
|
|
|