/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Author: Eyal Hochberg ////
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//// Author: Eyal Hochberg ////
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//// eyal@provartec.com ////
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//// eyal@provartec.com ////
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//// ////
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//// ////
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//// Downloaded from: http://www.opencores.org ////
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//// Downloaded from: http://www.opencores.org ////
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2010 Provartec LTD ////
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//// Copyright (C) 2010 Provartec LTD ////
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//// www.provartec.com ////
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//// www.provartec.com ////
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//// info@provartec.com ////
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//// info@provartec.com ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation.////
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//// Public License as published by the Free Software Foundation.////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more////
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//// PURPOSE. See the GNU Lesser General Public License for more////
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//// details. http://www.gnu.org/licenses/lgpl.html ////
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//// details. http://www.gnu.org/licenses/lgpl.html ////
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//// ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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OUTFILE PREFIX_stall.v
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OUTFILE PREFIX_stall.v
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INCLUDE def_axi_master.txt
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INCLUDE def_axi_master.txt
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module PREFIX_stall(PORTS);
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module PREFIX_stall(PORTS);
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`include "prgen_rand.v"
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`include "prgen_rand.v"
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input clk;
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input clk;
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input reset;
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input reset;
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input rd_hold;
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input rd_hold;
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input wr_hold;
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input wr_hold;
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input ARVALID_pre;
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input ARVALID_pre;
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input RREADY_pre;
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input RREADY_pre;
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input AWVALID_pre;
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input AWVALID_pre;
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input WVALID_pre;
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input WVALID_pre;
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input BREADY_pre;
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input BREADY_pre;
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input ARREADY;
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input ARREADY;
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input AWREADY;
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input AWREADY;
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input WREADY;
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input WREADY;
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output ARVALID;
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output ARVALID;
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output RREADY;
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output RREADY;
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output AWVALID;
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output AWVALID;
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output WVALID;
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output WVALID;
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output BREADY;
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output BREADY;
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reg stall_enable = 1;
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reg stall_enable = 1;
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integer burst_chance = 1;
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integer burst_chance = 1;
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integer burst_len = 10;
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integer burst_len = 10;
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integer burst_val = 90;
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integer burst_val = 90;
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integer ar_stall_chance = 10;
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integer ar_stall_chance = 10;
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integer r_stall_chance = 10;
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integer r_stall_chance = 10;
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integer aw_stall_chance = 10;
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integer aw_stall_chance = 10;
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integer w_stall_chance = 10;
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integer w_stall_chance = 10;
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integer b_stall_chance = 10;
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integer b_stall_chance = 10;
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integer burst_type;
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integer burst_type;
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reg burst_stall;
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reg burst_stall;
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integer ar_stall_chance_valid;
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integer ar_stall_chance_valid;
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integer r_stall_chance_valid;
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integer r_stall_chance_valid;
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integer aw_stall_chance_valid;
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integer aw_stall_chance_valid;
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integer w_stall_chance_valid;
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integer w_stall_chance_valid;
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integer b_stall_chance_valid;
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integer b_stall_chance_valid;
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reg ARSTALL_pre = 0;
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reg ARSTALL_pre = 0;
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reg RSTALL_pre = 0;
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reg RSTALL_pre = 0;
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reg AWSTALL_pre = 0;
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reg AWSTALL_pre = 0;
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reg WSTALL_pre = 0;
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reg WSTALL_pre = 0;
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reg BSTALL_pre = 0;
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reg BSTALL_pre = 0;
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reg ARSTALL;
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reg ARSTALL;
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reg RSTALL;
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reg RSTALL;
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reg AWSTALL;
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reg AWSTALL;
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reg WSTALL;
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reg WSTALL;
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reg BSTALL;
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reg BSTALL;
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assign ARVALID = ARVALID_pre & (~ARSTALL) & (~rd_hold);
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assign ARVALID = ARVALID_pre & (~ARSTALL) & (~rd_hold);
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assign RREADY = RREADY_pre & (~RSTALL);
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assign RREADY = RREADY_pre & (~RSTALL);
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assign AWVALID = AWVALID_pre & (~AWSTALL) & (~wr_hold);
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assign AWVALID = AWVALID_pre & (~AWSTALL) & (~wr_hold);
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assign WVALID = WVALID_pre & (~WSTALL);
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assign WVALID = WVALID_pre & (~WSTALL);
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assign BREADY = BREADY_pre & (~BSTALL);
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assign BREADY = BREADY_pre & (~BSTALL);
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task set_stall;
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task set_stall;
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reg stall;
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reg stall;
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begin
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begin
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ar_stall_chance_valid = ar_stall_chance;
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ar_stall_chance_valid = ar_stall_chance;
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r_stall_chance_valid = r_stall_chance;
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r_stall_chance_valid = r_stall_chance;
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aw_stall_chance_valid = aw_stall_chance;
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aw_stall_chance_valid = aw_stall_chance;
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w_stall_chance_valid = w_stall_chance;
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w_stall_chance_valid = w_stall_chance;
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b_stall_chance_valid = b_stall_chance;
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b_stall_chance_valid = b_stall_chance;
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end
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end
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endtask
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endtask
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initial
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initial
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begin
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begin
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#FFD;
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#FFD;
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set_stall;
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set_stall;
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if (burst_chance > 0)
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if (burst_chance > 0)
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forever
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forever
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begin
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begin
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burst_stall = rand_chance(burst_chance);
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burst_stall = rand_chance(burst_chance);
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if (burst_stall)
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if (burst_stall)
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begin
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begin
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#FFD;
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#FFD;
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burst_type = rand(1, 5);
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burst_type = rand(1, 5);
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case (burst_type)
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case (burst_type)
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1 : ar_stall_chance_valid = burst_val;
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1 : ar_stall_chance_valid = burst_val;
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2 : r_stall_chance_valid = burst_val;
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2 : r_stall_chance_valid = burst_val;
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3 : aw_stall_chance_valid = burst_val;
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3 : aw_stall_chance_valid = burst_val;
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4 : w_stall_chance_valid = burst_val;
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4 : w_stall_chance_valid = burst_val;
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5 : b_stall_chance_valid = burst_val;
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5 : b_stall_chance_valid = burst_val;
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endcase
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endcase
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repeat (burst_len) @(posedge clk);
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repeat (burst_len) @(posedge clk);
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set_stall;
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set_stall;
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end
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end
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else
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else
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begin
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begin
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@(posedge clk);
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@(posedge clk);
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end
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end
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end
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end
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end
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end
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always @(posedge clk)
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always @(posedge clk)
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begin
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begin
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#FFD;
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#FFD;
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ARSTALL_pre = rand_chance(ar_stall_chance_valid);
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ARSTALL_pre = rand_chance(ar_stall_chance_valid);
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RSTALL_pre = rand_chance(r_stall_chance_valid);
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RSTALL_pre = rand_chance(r_stall_chance_valid);
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AWSTALL_pre = rand_chance(aw_stall_chance_valid);
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AWSTALL_pre = rand_chance(aw_stall_chance_valid);
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WSTALL_pre = rand_chance(w_stall_chance_valid);
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WSTALL_pre = rand_chance(w_stall_chance_valid);
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BSTALL_pre = rand_chance(b_stall_chance_valid);
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BSTALL_pre = rand_chance(b_stall_chance_valid);
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end
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end
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always @(posedge clk or posedge reset)
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always @(posedge clk or posedge reset)
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if (reset)
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if (reset)
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begin
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begin
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ARSTALL <= #FFD 1'b0;
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ARSTALL <= #FFD 1'b0;
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RSTALL <= #FFD 1'b0;
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RSTALL <= #FFD 1'b0;
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AWSTALL <= #FFD 1'b0;
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AWSTALL <= #FFD 1'b0;
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WSTALL <= #FFD 1'b0;
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WSTALL <= #FFD 1'b0;
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BSTALL <= #FFD 1'b0;
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BSTALL <= #FFD 1'b0;
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end
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end
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else if (stall_enable)
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else if (stall_enable)
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begin
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begin
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ARSTALL <= #FFD ARSTALL_pre & ARREADY;
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ARSTALL <= #FFD ARSTALL_pre & ARREADY; //keep VALID signal stable while ~READY
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RSTALL <= #FFD RSTALL_pre;
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RSTALL <= #FFD RSTALL_pre;
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AWSTALL <= #FFD AWSTALL_pre & AWREADY;
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AWSTALL <= #FFD AWSTALL_pre & AWREADY; //keep VALID signal stable while ~READY
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WSTALL <= #FFD WSTALL_pre & WREADY;
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WSTALL <= #FFD WSTALL_pre & WREADY; //keep VALID signal stable while ~READY
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BSTALL <= #FFD BSTALL_pre;
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BSTALL <= #FFD BSTALL_pre;
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end
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end
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else
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else
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begin
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begin
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ARSTALL <= #FFD 1'b0;
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ARSTALL <= #FFD 1'b0;
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RSTALL <= #FFD 1'b0;
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RSTALL <= #FFD 1'b0;
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AWSTALL <= #FFD 1'b0;
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AWSTALL <= #FFD 1'b0;
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WSTALL <= #FFD 1'b0;
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WSTALL <= #FFD 1'b0;
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BSTALL <= #FFD 1'b0;
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BSTALL <= #FFD 1'b0;
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end
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end
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endmodule
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endmodule
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