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[/] [ahb_master/] [trunk/] [src/] [base/] [def_axi2ahb_static.txt] - Diff between revs 2 and 7
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Rev 7 |
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SWAP MODEL_NAME AXI2AHB bridge
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VERIFY ((DATA_BITS==32) || (DATA_BITS==64))
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VERIFY ((DATA_BITS==32) || (DATA_BITS==64))
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GROUP AXI_A is {
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GROUP AXI_A is {
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ID ID_BITS input
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ID ID_BITS input
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ADDR ADDR_BITS input
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ADDR ADDR_BITS input
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LEN 4 input
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LEN 4 input
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SIZE 2 input
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SIZE 2 input
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VALID 1 input
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VALID 1 input
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READY 1 output
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READY 1 output
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}
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}
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GROUP AXI_W is {
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GROUP AXI_W is {
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ID ID_BITS input
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ID ID_BITS input
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DATA DATA_BITS input
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DATA DATA_BITS input
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STRB DATA_BITS/8 input
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STRB DATA_BITS/8 input
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LAST 1 input
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LAST 1 input
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VALID 1 input
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VALID 1 input
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READY 1 output
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READY 1 output
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}
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}
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GROUP AXI_B is {
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GROUP AXI_B is {
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ID ID_BITS output
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ID ID_BITS output
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RESP 2 output
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RESP 2 output
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VALID 1 output
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VALID 1 output
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READY 1 input
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READY 1 input
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}
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}
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GROUP AXI_R is {
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GROUP AXI_R is {
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ID ID_BITS output
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ID ID_BITS output
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DATA DATA_BITS output
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DATA DATA_BITS output
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RESP 2 output
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RESP 2 output
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LAST 1 output
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LAST 1 output
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VALID 1 output
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VALID 1 output
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READY 1 input
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READY 1 input
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}
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}
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GROUP AXI joins {
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GROUP AXI joins {
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GROUP AXI_A prefix_AW
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GROUP AXI_A prefix_AW
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GROUP AXI_W prefix_W
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GROUP AXI_W prefix_W
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GROUP AXI_B prefix_B
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GROUP AXI_B prefix_B
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GROUP AXI_A prefix_AR
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GROUP AXI_A prefix_AR
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GROUP AXI_R prefix_R
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GROUP AXI_R prefix_R
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}
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}
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GROUP AHB is {
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GROUP AHB is {
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HADDR ADDR_BITS input
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HADDR ADDR_BITS input
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HBURST 3 input
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HBURST 3 input
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HSIZE 2 input
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HSIZE 2 input
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HTRANS 2 input
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HTRANS 2 input
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HWRITE 1 input
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HWRITE 1 input
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HWDATA DATA_BITS input
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HWDATA DATA_BITS input
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HRDATA DATA_BITS output
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HRDATA DATA_BITS output
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HREADY 1 output
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HREADY 1 output
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HRESP 1 output
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HRESP 1 output
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}
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}
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