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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Author: Eyal Hochberg ////
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//// eyal@provartec.com ////
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//// ////
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//// Downloaded from: http://www.opencores.org ////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2010 Provartec LTD ////
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//// www.provartec.com ////
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//// info@provartec.com ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation.////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more////
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//// details. http://www.gnu.org/licenses/lgpl.html ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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OUTFILE PREFIX_mem.v
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OUTFILE PREFIX_mem.v
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INCLUDE def_ahb_slave.txt
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INCLUDE def_ahb_slave.txt
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ITER BX EXPR(DATA_BITS/8)
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ITER BX EXPR(DATA_BITS/8)
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module PREFIX_mem (PORTS);
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module PREFIX_mem (PORTS);
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parameter MEM_WORDS = EXPR((2^ADDR_BITS)/(DATA_BITS/8));
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parameter MEM_WORDS = EXPR((2^ADDR_BITS)/(DATA_BITS/8));
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parameter ADDR_LSB = LOG2(EXPR(DATA_BITS/8));
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parameter ADDR_LSB = LOG2(EXPR(DATA_BITS/8));
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input clk;
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input clk;
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input reset;
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input reset;
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revport GROUP_STUB_MEM;
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revport GROUP_STUB_MEM;
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reg [DATA_BITS-1:0] Mem [MEM_WORDS-1:0];
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reg [DATA_BITS-1:0] Mem [MEM_WORDS-1:0];
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reg [DATA_BITS-1:0] DOUT;
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reg [DATA_BITS-1:0] DOUT;
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wire [DATA_BITS-1:0] BitSEL;
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wire [DATA_BITS-1:0] BitSEL;
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wire [ADDR_BITS-1:ADDR_LSB] ADDR_WR_word = ADDR_WR[ADDR_BITS-1:ADDR_LSB];
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wire [ADDR_BITS-1:ADDR_LSB] ADDR_WR_word = ADDR_WR[ADDR_BITS-1:ADDR_LSB];
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wire [ADDR_BITS-1:ADDR_LSB] ADDR_RD_word = ADDR_RD[ADDR_BITS-1:ADDR_LSB];
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wire [ADDR_BITS-1:ADDR_LSB] ADDR_RD_word = ADDR_RD[ADDR_BITS-1:ADDR_LSB];
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assign BitSEL = {CONCAT({8{BSEL[BX]}} ,)};
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assign BitSEL = {CONCAT({8{BSEL[BX]}} ,)};
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always @(posedge clk)
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always @(posedge clk)
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if (WR)
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if (WR)
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Mem[ADDR_WR_word] <= #FFD (Mem[ADDR_WR_word] & ~BitSEL) | (DIN & BitSEL);
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Mem[ADDR_WR_word] <= #FFD (Mem[ADDR_WR_word] & ~BitSEL) | (DIN & BitSEL);
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always @(posedge clk or posedge reset)
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always @(posedge clk or posedge reset)
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if (reset)
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if (reset)
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DOUT <= #FFD {DATA_BITS{1'b0}};
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DOUT <= #FFD {DATA_BITS{1'b0}};
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else if (RD)
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else if (RD)
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DOUT <= #FFD Mem[ADDR_RD_word];
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DOUT <= #FFD Mem[ADDR_RD_word];
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endmodule
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endmodule
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