library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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use work.ahb_package.all;
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use work.ahb_package.all;
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use work.ahb_funct.all;
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use work.ahb_funct.all;
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use work.ahb_configure.all;
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use work.ahb_configure.all;
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package ahb_components is
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package ahb_components is
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component fifo
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component fifo
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generic (
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generic (
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fifohempty_level: in integer:= 1;
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fifohempty_level: in integer:= 1;
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fifohfull_level: in integer:= 3;
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fifohfull_level: in integer:= 3;
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fifo_length: in integer:= 4);
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fifo_length: in integer:= 4);
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port (
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port (
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hresetn: in std_logic;
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hresetn: in std_logic;
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clk: in std_logic;
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clk: in std_logic;
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fifo_reset: in std_logic;
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fifo_reset: in std_logic;
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fifo_write: in std_logic;
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fifo_write: in std_logic;
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fifo_read: in std_logic;
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fifo_read: in std_logic;
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fifo_count: out std_logic_vector(nb_bits(fifo_length)-1 downto 0);
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fifo_count: out std_logic_vector(nb_bits(fifo_length)-1 downto 0);
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fifo_full: out std_logic;
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fifo_full: out std_logic;
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fifo_hfull: out std_logic;
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fifo_hfull: out std_logic;
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fifo_empty: out std_logic;
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fifo_empty: out std_logic;
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fifo_hempty: out std_logic;
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fifo_hempty: out std_logic;
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fifo_datain: in std_logic_vector(31 downto 0);
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fifo_datain: in std_logic_vector(31 downto 0);
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fifo_dataout: out std_logic_vector(31 downto 0)
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fifo_dataout: out std_logic_vector(31 downto 0)
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);
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);
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end component;
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end component;
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component ahb_master
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component ahb_master
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generic (
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generic (
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fifohempty_level: in integer;
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fifohempty_level: in integer;
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fifohfull_level: in integer;
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fifohfull_level: in integer;
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fifo_length: in integer);
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fifo_length: in integer);
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port (
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port (
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hresetn: in std_logic;
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hresetn: in std_logic;
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hclk: in std_logic;
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hclk: in std_logic;
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mst_in: in mst_in_t;
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mst_in: in mst_in_t;
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mst_out: out mst_out_t;
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mst_out: out mst_out_t;
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dma_start: in start_type_t;
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dma_start: in start_type_t;
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m_wrap_out: out wrap_out_t;
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m_wrap_out: out wrap_out_t;
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m_wrap_in: in wrap_in_t;
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m_wrap_in: in wrap_in_t;
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slv_running: in std_logic;
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slv_running: in std_logic;
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mst_running: out std_logic;
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mst_running: out std_logic;
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eot_int: out std_logic);
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eot_int: out std_logic);
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end component;
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end component;
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component ahb_arbiter
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component ahb_arbiter
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generic(
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generic(
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num_arb: in integer;
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num_arb: in integer;
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num_arb_msts: in integer range 1 to 15;
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num_arb_msts: in integer range 1 to 15;
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def_arb_mst: in integer range 0 to 15;
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def_arb_mst: in integer range 0 to 15;
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num_slvs: in integer range 1 to 15;
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num_slvs: in integer range 1 to 15;
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alg_number: in integer range 0 to 5);
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alg_number: in integer range 0 to 5);
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port(
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port(
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hresetn: in std_logic;
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hresetn: in std_logic;
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hclk: in std_logic;
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hclk: in std_logic;
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remap: in std_logic;
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remap: in std_logic;
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mst_in_v: in mst_out_v_t(num_arb_msts-1 downto 0);
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mst_in_v: in mst_out_v_t(num_arb_msts-1 downto 0);
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mst_out_v: out mst_in_v_t(num_arb_msts-1 downto 0);
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mst_out_v: out mst_in_v_t(num_arb_msts-1 downto 0);
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slv_out_v: out slv_in_v_t(num_slvs-1 downto 0);
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slv_out_v: out slv_in_v_t(num_slvs-1 downto 0);
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slv_in_v: in slv_out_v_t(num_slvs-1 downto 0));
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slv_in_v: in slv_out_v_t(num_slvs-1 downto 0));
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end component;
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end component;
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component ahb_slave_wait
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component ahb_slave_wait
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generic (
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generic (
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num_slv: in integer range 0 to 15:= 1;
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num_slv: in integer range 0 to 15:= 1;
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fifohempty_level: in integer:= 2;
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fifohempty_level: in integer:= 2;
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fifohfull_level: in integer:= 5;
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fifohfull_level: in integer:= 5;
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fifo_length: in integer:= 8);
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fifo_length: in integer:= 8);
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port(
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port(
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hresetn: in std_logic;
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hresetn: in std_logic;
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hclk: in std_logic;
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hclk: in std_logic;
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remap: in std_logic;
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remap: in std_logic;
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slv_in: in slv_in_t;
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slv_in: in slv_in_t;
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slv_out: out slv_out_t;
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slv_out: out slv_out_t;
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mst_running: in std_logic;
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mst_running: in std_logic;
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prior_in: in std_logic;
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prior_in: in std_logic;
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slv_running: out std_logic;
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slv_running: out std_logic;
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slv_err: out std_logic;
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slv_err: out std_logic;
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s_wrap_out: out wrap_out_t;
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s_wrap_out: out wrap_out_t;
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s_wrap_in: in wrap_in_t);
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s_wrap_in: in wrap_in_t);
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end component;
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end component;
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component mst_wrap
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component mst_wrap
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generic (
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generic (
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--synopsys translate_off
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--synopsys translate_off
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dump_file: in string:= "mst_wrap.log";
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dump_file: in string:= "mst_wrap.log";
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dump_type: in integer;
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dump_type: in integer;
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--synopsys translate_on
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--synopsys translate_on
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ahb_max_addr: in integer:= 4;
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ahb_max_addr: in integer:= 4;
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m_const_lat_write: in integer;
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m_const_lat_write: in integer;
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m_const_lat_read: in integer;
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m_const_lat_read: in integer;
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m_write_burst: in integer;
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m_write_burst: in integer;
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m_read_burst: in integer);
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m_read_burst: in integer);
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port (
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port (
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hresetn: in std_logic;
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hresetn: in std_logic;
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clk: in std_logic;
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clk: in std_logic;
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conf: in conf_type_t;
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conf: in conf_type_t;
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dma_start: out start_type_t;
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dma_start: out start_type_t;
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m_wrap_in: in wrap_out_t;
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m_wrap_in: in wrap_out_t;
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m_wrap_out: out wrap_in_t);
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m_wrap_out: out wrap_in_t);
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end component;
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end component;
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component slv_mem
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component slv_mem
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generic (
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generic (
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--synopsys translate_off
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--synopsys translate_off
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dump_file: in string:= "slv_wrap.log";
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dump_file: in string:= "slv_wrap.log";
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dump_type: in integer;
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dump_type: in integer;
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--synopsys translate_on
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--synopsys translate_on
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ahb_max_addr: in integer:= 8;
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ahb_max_addr: in integer:= 8;
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s_const_lat_write: in integer;
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s_const_lat_write: in integer;
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s_const_lat_read: in integer;
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s_const_lat_read: in integer;
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s_write_burst: in integer;
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s_write_burst: in integer;
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s_read_burst: in integer);
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s_read_burst: in integer);
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port (
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port (
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hresetn: in std_logic;
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hresetn: in std_logic;
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clk: in std_logic;
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clk: in std_logic;
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conf: in conf_type_t;
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conf: in conf_type_t;
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dma_start: out start_type_t;
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dma_start: out start_type_t;
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s_wrap_in: in wrap_out_t;
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s_wrap_in: in wrap_out_t;
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s_wrap_out: out wrap_in_t
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s_wrap_out: out wrap_in_t
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);
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);
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end component;
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end component;
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component uut_stimulator
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component uut_stimulator
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generic (
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generic (
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stim_type: in uut_params_t;
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stim_type: in uut_params_t;
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enable: in integer;
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enable: in integer;
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eot_enable: in integer);
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eot_enable: in integer);
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port(
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port(
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hclk : in std_logic;
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hclk : in std_logic;
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hresetn : in std_logic;
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hresetn : in std_logic;
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amba_error: in std_logic;
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amba_error: in std_logic;
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eot_int: in std_logic;
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eot_int: in std_logic;
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conf: out conf_type_t;
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conf: out conf_type_t;
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sim_end: out std_logic);
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sim_end: out std_logic);
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end component;
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end component;
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end;
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end;
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package body ahb_components is
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package body ahb_components is
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end;
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end;
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