library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_misc.all;
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use ieee.std_logic_misc.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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use work.ahb_funct.all;
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use work.ahb_funct.all;
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use work.ahb_package.all;
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use work.ahb_package.all;
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entity fifo is
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entity fifo is
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generic (
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generic (
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fifohempty_level: in integer:= 1;
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fifohempty_level: in integer:= 1;
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fifohfull_level: in integer:= 3;
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fifohfull_level: in integer:= 3;
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fifo_length: in integer:= 4);
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fifo_length: in integer:= 4);
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port (
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port (
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hresetn: in std_logic;
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hresetn: in std_logic;
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clk: in std_logic;
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clk: in std_logic;
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fifo_reset: in std_logic;
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fifo_reset: in std_logic;
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fifo_write: in std_logic;
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fifo_write: in std_logic;
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fifo_read: in std_logic;
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fifo_read: in std_logic;
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fifo_count: out std_logic_vector(nb_bits(fifo_length)-1 downto 0);
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fifo_count: out std_logic_vector(nb_bits(fifo_length)-1 downto 0);
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fifo_full: out std_logic;
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fifo_full: out std_logic;
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fifo_hfull: out std_logic;
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fifo_hfull: out std_logic;
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fifo_empty: out std_logic;
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fifo_empty: out std_logic;
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fifo_hempty: out std_logic;
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fifo_hempty: out std_logic;
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fifo_datain: in std_logic_vector(31 downto 0);
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fifo_datain: in std_logic_vector(31 downto 0);
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fifo_dataout: out std_logic_vector(31 downto 0)
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fifo_dataout: out std_logic_vector(31 downto 0)
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);
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);
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end fifo;
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end fifo;
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architecture rtl of fifo is
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architecture rtl of fifo is
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signal fifo_full_s, fifo_empty_s: std_logic;
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signal fifo_full_s, fifo_empty_s: std_logic;
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signal fifo_count_s : std_logic_vector(nb_bits(fifo_length)-1 downto 0);--log2 fifo_length + 1
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signal fifo_count_s : std_logic_vector(nb_bits(fifo_length)-1 downto 0);--log2 fifo_length + 1
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signal rptr, wptr: std_logic_vector(nb_bits(fifo_length)-1 downto 0);
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signal rptr, wptr: std_logic_vector(nb_bits(fifo_length)-1 downto 0);
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type vect_fifo_32 is array (fifo_length-1 downto 0) of std_logic_vector (31 downto 0);
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type vect_fifo_32 is array (fifo_length-1 downto 0) of std_logic_vector (31 downto 0);
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signal fifo : vect_fifo_32;
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signal fifo : vect_fifo_32;
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begin
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begin
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fifo_wr_pr:process(clk, hresetn)
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fifo_wr_pr:process(clk, hresetn)
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begin
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begin
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if hresetn='0' then
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if hresetn='0' then
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wptr <= (others => '0');
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wptr <= (others => '0');
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elsif clk'event and clk='1' then
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elsif clk'event and clk='1' then
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if fifo_reset='1' then
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if fifo_reset='1' then
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wptr <= (others => '0') after 1 ns;
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wptr <= (others => '0') after 1 ns;
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elsif (fifo_write='1') then
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elsif (fifo_write='1') then
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fifo(conv_integer(wptr(wptr'length-2 downto 0))) <= fifo_datain after 1 ns;
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fifo(conv_integer(wptr(wptr'length-2 downto 0))) <= fifo_datain after 1 ns;
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wptr <= wptr+1 after 1 ns;
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wptr <= wptr+1 after 1 ns;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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fifo_rd_pr:process(clk, hresetn)
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fifo_rd_pr:process(clk, hresetn)
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begin
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begin
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if hresetn='0' then
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if hresetn='0' then
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rptr <= (others => '0');
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rptr <= (others => '0');
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elsif clk'event and clk='1' then
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elsif clk'event and clk='1' then
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if fifo_reset='1' then
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if fifo_reset='1' then
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rptr <= (others => '0') after 1 ns;
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rptr <= (others => '0') after 1 ns;
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elsif (fifo_read='1') then
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elsif (fifo_read='1') then
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rptr <= rptr+1 after 1 ns;
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rptr <= rptr+1 after 1 ns;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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fifo_dataout <= fifo(conv_integer(rptr(rptr'length-2 downto 0)));--data from fifo visible
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fifo_dataout <= fifo(conv_integer(rptr(rptr'length-2 downto 0)));--data from fifo visible
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fifo_count_s <= wptr(wptr'length-1 downto 0) - rptr(rptr'length-1 downto 0);
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fifo_count_s <= wptr(wptr'length-1 downto 0) - rptr(rptr'length-1 downto 0);
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fifo_full_s <= '1' when (fifo_count_s=fifo_length) else '0';--same value,/=msb
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fifo_full_s <= '1' when (fifo_count_s=fifo_length) else '0';--same value,/=msb
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fifo_empty_s <= '1' when (fifo_count_s=0) else '0';--same value,==msb
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fifo_empty_s <= '1' when (fifo_count_s=0) else '0';--same value,==msb
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fifo_hfull <= '1' when (fifo_count_s>=fifohfull_level) else '0';
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fifo_hfull <= '1' when (fifo_count_s>=fifohfull_level) else '0';
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fifo_hempty <= '1' when (fifo_count_s<=fifohempty_level) else '0';
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fifo_hempty <= '1' when (fifo_count_s<=fifohempty_level) else '0';
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fifo_full <= fifo_full_s;
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fifo_full <= fifo_full_s;
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fifo_empty <= fifo_empty_s;
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fifo_empty <= fifo_empty_s;
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fifo_count <= fifo_count_s;
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fifo_count <= fifo_count_s;
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end rtl;
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end rtl;
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