use STD.textio.all;--added for time and strings
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use STD.textio.all;--added for time and strings
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library ieee;
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library ieee;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_misc.all;
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use ieee.std_logic_misc.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use IEEE.std_logic_textio.all;--added for time and strings
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use IEEE.std_logic_textio.all;--added for time and strings
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-- Add your library and packages declaration here ...
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-- Add your library and packages declaration here ...
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use work.ahb_package.all;
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use work.ahb_package.all;
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entity uut_stimulator is
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entity uut_stimulator is
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generic (
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generic (
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stim_type: in uut_params_t:= (bits32,retry,master,'0',single,2,4,hprot_posted,2048,1,0,'0');
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stim_type: in uut_params_t:= (bits32,retry,master,'0',single,2,4,hprot_posted,2048,1,0,'0');
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enable: in integer:= 0;
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enable: in integer:= 0;
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eot_enable: in integer:= 0);
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eot_enable: in integer:= 0);
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port(
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port(
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hclk : in std_logic;
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hclk : in std_logic;
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hresetn : in std_logic;
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hresetn : in std_logic;
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amba_error: in std_logic;
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amba_error: in std_logic;
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eot_int: in std_logic;
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eot_int: in std_logic;
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conf: out conf_type_t;
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conf: out conf_type_t;
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sim_end: out std_logic
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sim_end: out std_logic
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);
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);
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end uut_stimulator;
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end uut_stimulator;
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--}} End of automatically maintained section
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--}} End of automatically maintained section
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architecture rtl of uut_stimulator is
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architecture rtl of uut_stimulator is
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signal cycle : std_logic;
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signal cycle : std_logic;
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signal counter: integer range 0 to 127;
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signal counter: integer range 0 to 127;
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begin
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begin
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process
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process
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begin
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begin
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if hresetn = '0' then
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if hresetn = '0' then
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counter <= 1;
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counter <= 1;
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else
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else
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if(counter > 15) then
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if(counter > 15) then
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assert false report "* Simulator Exit.." severity warning;
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assert false report "* Simulator Exit.." severity warning;
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sim_end <= '1';
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sim_end <= '1';
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wait;
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wait;
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else
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else
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sim_end <= '0';
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sim_end <= '0';
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counter <= counter+1;
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counter <= counter+1;
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end if;
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end if;
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end if;
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end if;
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if (eot_enable/=1) then
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if (eot_enable/=1) then
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wait for 4000 ns;
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wait for 4000 ns;
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else
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else
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wait until (eot_int='1' or amba_error='1');--write
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wait until (eot_int='1' or amba_error='1');--write
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wait until (eot_int='1' or amba_error='1');--read
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wait until (eot_int='1' or amba_error='1');--read
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end if;
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end if;
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end process;
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end process;
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cycle_pr:process
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cycle_pr:process
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begin
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begin
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if cycle/='1' then
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if cycle/='1' then
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cycle <= '1';
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cycle <= '1';
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if (eot_enable/=1) then
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if (eot_enable/=1) then
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wait for 2000 ns;
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wait for 2000 ns;
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else
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else
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wait until (eot_int='1' or amba_error='1');
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wait until (eot_int='1' or amba_error='1');
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end if;
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end if;
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else
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else
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cycle <= '0';
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cycle <= '0';
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if (eot_enable/=1) then
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if (eot_enable/=1) then
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wait for 2000 ns;
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wait for 2000 ns;
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else
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else
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wait until (eot_int='1' or amba_error='1');
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wait until (eot_int='1' or amba_error='1');
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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process
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process
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variable hburst: std_logic_vector(2 downto 0);
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variable hburst: std_logic_vector(2 downto 0);
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begin
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begin
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if (counter<=16) then
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if (counter<=16) then
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conf.write <= '0';
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conf.write <= '0';
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wait for 30 ns;
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wait for 30 ns;
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conf.write <= '1';
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conf.write <= '1';
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conf.addr <= dma_type_addr;
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conf.addr <= dma_type_addr;
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case stim_type.hburst_cycle is
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case stim_type.hburst_cycle is
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when '1' =>
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when '1' =>
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hburst := stim_type.hburst_tb;
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hburst := stim_type.hburst_tb;
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when others =>
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when others =>
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hburst := conv_std_logic_vector(counter,3);
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hburst := conv_std_logic_vector(counter,3);
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end case;
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end case;
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conf.wdata <= "000000000000000000"&
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conf.wdata <= "000000000000000000"&
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stim_type.split_tb&stim_type.prior_tb&stim_type.hsize_tb&hburst&stim_type.hprot_tb&cycle&stim_type.locked_request;
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stim_type.split_tb&stim_type.prior_tb&stim_type.hsize_tb&hburst&stim_type.hprot_tb&cycle&stim_type.locked_request;
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wait for 10 ns;
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wait for 10 ns;
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conf.addr <= dma_extadd_addr;
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conf.addr <= dma_extadd_addr;
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--conf.wdata(31 downto 12)<=stim_type.high_addr_tb;
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--conf.wdata(31 downto 12)<=stim_type.high_addr_tb;
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case stim_type.ext_addr_incr_tb is
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case stim_type.ext_addr_incr_tb is
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when 1 =>--fixed ext addr
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when 1 =>--fixed ext addr
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conf.wdata(31 downto 0)<= conv_std_logic_vector(stim_type.base_tb ,32);
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conf.wdata(31 downto 0)<= conv_std_logic_vector(stim_type.base_tb ,32);
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when 2 =>--increasing by 4, page fault if base near end of slave address space
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when 2 =>--increasing by 4, page fault if base near end of slave address space
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conf.wdata(31 downto 0)<= conv_std_logic_vector(stim_type.base_tb+(counter-1)*4 ,32);
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conf.wdata(31 downto 0)<= conv_std_logic_vector(stim_type.base_tb+(counter-1)*4 ,32);
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when others =>--growing by incr_tb-4 (0,1,2,3,4,5, ETC.)
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when others =>--growing by incr_tb-4 (0,1,2,3,4,5, ETC.)
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conf.wdata(31 downto 0)<= conv_std_logic_vector(stim_type.base_tb+(counter-1)*(stim_type.ext_addr_incr_tb-4) ,32);
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conf.wdata(31 downto 0)<= conv_std_logic_vector(stim_type.base_tb+(counter-1)*(stim_type.ext_addr_incr_tb-4) ,32);
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end case;
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end case;
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wait for 10 ns;--external address
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wait for 10 ns;--external address
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conf.addr <= dma_intadd_addr;
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conf.addr <= dma_intadd_addr;
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case stim_type.int_addr_incr_tb is
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case stim_type.int_addr_incr_tb is
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when 1 =>--fixed int addr
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when 1 =>--fixed int addr
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conf.wdata(31 downto 0)<= conv_std_logic_vector(stim_type.int_base_tb,32);
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conf.wdata(31 downto 0)<= conv_std_logic_vector(stim_type.int_base_tb,32);
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when 2 =>--increasing by 4, page fault if base near end of slave address space
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when 2 =>--increasing by 4, page fault if base near end of slave address space
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conf.wdata(31 downto 0)<= conv_std_logic_vector(stim_type.int_base_tb+(counter-1)*4 ,32);
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conf.wdata(31 downto 0)<= conv_std_logic_vector(stim_type.int_base_tb+(counter-1)*4 ,32);
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when others =>--growing by incr_tb-4 (0,1,2,3,4,5, ETC.)
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when others =>--growing by incr_tb-4 (0,1,2,3,4,5, ETC.)
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conf.wdata(31 downto 0)<= conv_std_logic_vector(stim_type.int_base_tb+(counter-1)*(stim_type.int_addr_incr_tb-4) ,32);
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conf.wdata(31 downto 0)<= conv_std_logic_vector(stim_type.int_base_tb+(counter-1)*(stim_type.int_addr_incr_tb-4) ,32);
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end case;
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end case;
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wait for 10 ns;--internal address
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wait for 10 ns;--internal address
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conf.addr <= dma_intmod_addr;
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conf.addr <= dma_intmod_addr;
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conf.wdata <= conv_std_logic_vector(stim_type.intmod_tb ,32);
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conf.wdata <= conv_std_logic_vector(stim_type.intmod_tb ,32);
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wait for 10 ns;--modifier
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wait for 10 ns;--modifier
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if enable=1 then
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if enable=1 then
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conf.addr <= dma_count_addr;
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conf.addr <= dma_count_addr;
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conf.wdata <= conv_std_logic_vector(counter,32);
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conf.wdata <= conv_std_logic_vector(counter,32);
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wait for 10 ns;--dma count
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wait for 10 ns;--dma count
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else
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else
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wait for 10 ns;--dma count
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wait for 10 ns;--dma count
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end if;
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end if;
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conf.write <= '0';
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conf.write <= '0';
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conf.addr <= "0000";
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conf.addr <= "0000";
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conf.wdata <= (others => '-');
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conf.wdata <= (others => '-');
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if (eot_enable/=1) then
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if (eot_enable/=1) then
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wait until cycle'event;
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wait until cycle'event;
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else
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else
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wait until (eot_int='1' or amba_error='1');
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wait until (eot_int='1' or amba_error='1');
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end if;
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end if;
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else
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else
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wait;
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wait;
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end if;
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end if;
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--if counter=16 then wait; end if;
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--if counter=16 then wait; end if;
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end process;
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end process;
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assert (amba_error/='1') report "###ERROR in AMBA operation!!!" severity error;
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assert (amba_error/='1') report "###ERROR in AMBA operation!!!" severity error;
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end rtl;
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end rtl;
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