LIBRARY ieee;
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_1164.all;
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USE IEEE.numeric_std.ALL;
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USE IEEE.numeric_std.ALL;
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ENTITY circuit IS
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ENTITY circuit IS
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-- Declarations
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-- Declarations
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PORT(
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PORT(
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clk : IN std_logic;
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clk : IN std_logic;
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reset : IN std_logic;
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reset : IN std_logic;
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fmin : IN std_logic_vector(7 downto 0);
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fmin : IN std_logic_vector(7 downto 0);
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dmout : OUT std_logic_vector (11 DOWNTO 0)
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dmout : OUT std_logic_vector (11 DOWNTO 0)
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);
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);
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END circuit ;
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END circuit ;
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ARCHITECTURE behavior OF circuit IS
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ARCHITECTURE behavior OF circuit IS
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-- Architecture declarations
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-- Architecture declarations
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-- Internal signal declarations
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-- Internal signal declarations
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SIGNAL d1 : signed(11 DOWNTO 0);
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SIGNAL d1 : signed(11 DOWNTO 0);
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SIGNAL d2 : signed(11 DOWNTO 0);
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SIGNAL d2 : signed(11 DOWNTO 0);
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SIGNAL dout : signed(7 DOWNTO 0);
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SIGNAL dout : signed(7 DOWNTO 0);
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SIGNAL output : signed(7 DOWNTO 0);
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SIGNAL output : signed(7 DOWNTO 0);
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-- Component Declarations
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-- Component Declarations
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COMPONENT multiplier
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COMPONENT multiplier
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PORT (
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PORT (
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clk : IN std_logic ;
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clk : IN std_logic ;
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reset : IN std_logic ;
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reset : IN std_logic ;
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input1 : IN std_logic_vector (7 DOWNTO 0);
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input1 : IN std_logic_vector (7 DOWNTO 0);
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input2 : IN signed (7 DOWNTO 0);
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input2 : IN signed (7 DOWNTO 0);
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output : OUT signed (7 DOWNTO 0)
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output : OUT signed (7 DOWNTO 0)
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);
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);
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END COMPONENT;
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END COMPONENT;
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COMPONENT fir
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COMPONENT fir
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PORT (
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PORT (
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clock : IN std_logic ;
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clock : IN std_logic ;
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reset : IN std_logic ;
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reset : IN std_logic ;
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data_in : IN signed (11 DOWNTO 0);
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data_in : IN signed (11 DOWNTO 0);
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data_out : OUT std_logic_vector (11 DOWNTO 0)
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data_out : OUT std_logic_vector (11 DOWNTO 0)
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);
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);
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END COMPONENT;
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END COMPONENT;
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COMPONENT loop_filter
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COMPONENT loop_filter
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PORT (
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PORT (
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clk : IN std_logic ;
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clk : IN std_logic ;
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reset : IN std_logic ;
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reset : IN std_logic ;
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c : IN signed (7 DOWNTO 0);
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c : IN signed (7 DOWNTO 0);
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d1 : OUT signed (11 DOWNTO 0);
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d1 : OUT signed (11 DOWNTO 0);
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d2 : OUT signed (11 DOWNTO 0)
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d2 : OUT signed (11 DOWNTO 0)
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);
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);
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END COMPONENT;
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END COMPONENT;
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COMPONENT nco
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COMPONENT nco
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PORT (
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PORT (
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clk : IN std_logic ;
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clk : IN std_logic ;
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reset : IN std_logic ;
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reset : IN std_logic ;
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din : IN signed (11 DOWNTO 0);
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din : IN signed (11 DOWNTO 0);
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dout : OUT signed (7 DOWNTO 0)
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dout : OUT signed (7 DOWNTO 0)
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);
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);
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END COMPONENT;
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END COMPONENT;
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BEGIN
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BEGIN
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-- Instance port mappings.
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-- Instance port mappings.
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I1 : multiplier
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I1 : multiplier
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PORT MAP (
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PORT MAP (
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clk => clk,
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clk => clk,
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reset => reset,
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reset => reset,
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input1 => fmin,
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input1 => fmin,
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input2 => dout,
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input2 => dout,
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output => output
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output => output
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);
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);
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I4 : fir
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I4 : fir
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PORT MAP (
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PORT MAP (
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clock => clk,
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clock => clk,
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reset => reset,
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reset => reset,
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data_in => d1,
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data_in => d1,
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data_out => dmout
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data_out => dmout
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);
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);
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I3 : loop_filter
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I3 : loop_filter
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PORT MAP (
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PORT MAP (
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clk => clk,
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clk => clk,
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reset => reset,
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reset => reset,
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c => output,
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c => output,
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d1 => d1,
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d1 => d1,
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d2 => d2
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d2 => d2
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);
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);
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I2 : nco
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I2 : nco
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PORT MAP (
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PORT MAP (
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clk => clk,
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clk => clk,
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reset => reset,
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reset => reset,
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din => d2,
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din => d2,
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dout => dout
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dout => dout
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);
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);
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END behavior;
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END behavior;
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