//==================================================================//
|
//==================================================================//
|
// File: d_Driver_ADCRamBuffer.v //
|
// File: d_Driver_ADCRamBuffer.v //
|
// Version: X //
|
// Version: X //
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -//
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -//
|
// Copyright (C) Stephen Pickett //
|
// Copyright (C) Stephen Pickett //
|
// July 15, 2005 //
|
// July 15, 2005 //
|
// //
|
// //
|
// This program is free software; you can redistribute it and/or //
|
// This program is free software; you can redistribute it and/or //
|
// modify it under the terms of the GNU General Public License //
|
// modify it under the terms of the GNU General Public License //
|
// as published by the Free Software Foundation; either version 2 //
|
// as published by the Free Software Foundation; either version 2 //
|
// of the License, or (at your option) any later version. //
|
// of the License, or (at your option) any later version. //
|
// //
|
// //
|
// This program is distributed in the hope that it will be useful, //
|
// This program is distributed in the hope that it will be useful, //
|
// but WITHOUT ANY WARRANTY; without even the implied warranty of //
|
// but WITHOUT ANY WARRANTY; without even the implied warranty of //
|
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the //
|
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the //
|
// GNU General Public License for more details. //
|
// GNU General Public License for more details. //
|
// //
|
// //
|
// If you have not received a copy of the GNU General Public License//
|
// If you have not received a copy of the GNU General Public License//
|
// along with this program; write to: //
|
// along with this program; write to: //
|
// Free Software Foundation, Inc., //
|
// Free Software Foundation, Inc., //
|
// 51 Franklin Street, Fifth Floor, //
|
// 51 Franklin Street, Fifth Floor, //
|
// Boston, MA 02110-1301, USA. //
|
// Boston, MA 02110-1301, USA. //
|
// //
|
// //
|
//------------------------------------------------------------------//
|
//------------------------------------------------------------------//
|
// Revisions: //
|
// Revisions: //
|
// Ver X July 15, 2005 Initial Development Release //
|
// Ver X July 15, 2005 Initial Development Release //
|
// //
|
// //
|
//==================================================================//
|
//==================================================================//
|
|
|
module ADCDataBuffer(
|
module ADCDataBuffer(
|
CLK_64MHZ, MASTER_CLK, MASTER_RST,
|
CLK_64MHZ, MASTER_CLK, MASTER_RST,
|
TIMESCALE, TRIGGER_LEVEL, VERT_OFFSET, HORZ_OFFSET,
|
TIMESCALE, TRIGGER_LEVEL, VERT_OFFSET, HORZ_OFFSET,
|
ADC_DATA,
|
ADC_DATA,
|
CLK_ADC,
|
CLK_ADC,
|
SNAP_DATA_EXT, SNAP_ADDR_EXT, SNAP_CLK_EXT,
|
SNAP_DATA_EXT, SNAP_ADDR_EXT, SNAP_CLK_EXT,
|
TRIGGERSTYLE
|
TRIGGERSTYLE
|
);
|
);
|
|
|
//==================================================================//
|
//==================================================================//
|
// PARAMETER DEFINITIONS //
|
// PARAMETER DEFINITIONS //
|
//==================================================================//
|
//==================================================================//
|
parameter ss_fifo_fill = 2'b00;
|
parameter ss_fifo_fill = 2'b00;
|
parameter ss_fifo_half = 2'b01;
|
parameter ss_fifo_half = 2'b01;
|
parameter ss_save_snapshot = 2'b11;
|
parameter ss_save_snapshot = 2'b11;
|
parameter ss_invalid = 2'b10;
|
parameter ss_invalid = 2'b10;
|
|
|
|
|
|
|
//==================================================================//
|
//==================================================================//
|
// VARIABLE DEFINITIONS //
|
// VARIABLE DEFINITIONS //
|
//==================================================================//
|
//==================================================================//
|
|
|
//----------------------//
|
//----------------------//
|
// INPUTS / OUTPUTS //
|
// INPUTS / OUTPUTS //
|
//----------------------//
|
//----------------------//
|
input CLK_64MHZ;
|
input CLK_64MHZ;
|
input MASTER_CLK;
|
input MASTER_CLK;
|
input MASTER_RST;
|
input MASTER_RST;
|
input[3:0] TIMESCALE;
|
input[3:0] TIMESCALE;
|
input[10:0] TRIGGER_LEVEL, VERT_OFFSET, HORZ_OFFSET;
|
input[10:0] TRIGGER_LEVEL, VERT_OFFSET, HORZ_OFFSET;
|
input[8:0] ADC_DATA;
|
input[8:0] ADC_DATA;
|
|
|
output CLK_ADC;
|
output CLK_ADC;
|
|
|
output[8:0] SNAP_DATA_EXT;
|
output[8:0] SNAP_DATA_EXT;
|
input[10:0] SNAP_ADDR_EXT;
|
input[10:0] SNAP_ADDR_EXT;
|
input SNAP_CLK_EXT;
|
input SNAP_CLK_EXT;
|
|
|
input[1:0] TRIGGERSTYLE;
|
input[1:0] TRIGGERSTYLE;
|
|
|
//----------------------//
|
//----------------------//
|
// WIRES / NODES //
|
// WIRES / NODES //
|
//----------------------//
|
//----------------------//
|
wire CLK_64MHZ, MASTER_CLK, MASTER_RST;
|
wire CLK_64MHZ, MASTER_CLK, MASTER_RST;
|
wire[3:0] TIMESCALE;
|
wire[3:0] TIMESCALE;
|
wire[10:0] TRIGGER_LEVEL, VERT_OFFSET, HORZ_OFFSET;
|
wire[10:0] TRIGGER_LEVEL, VERT_OFFSET, HORZ_OFFSET;
|
wire[8:0] ADC_DATA;
|
wire[8:0] ADC_DATA;
|
wire CLK_ADC;
|
wire CLK_ADC;
|
wire[8:0] SNAP_DATA_EXT;
|
wire[8:0] SNAP_DATA_EXT;
|
wire[10:0] SNAP_ADDR_EXT;
|
wire[10:0] SNAP_ADDR_EXT;
|
wire SNAP_CLK_EXT;
|
wire SNAP_CLK_EXT;
|
wire[1:0] TRIGGERSTYLE;
|
wire[1:0] TRIGGERSTYLE;
|
|
|
|
|
//----------------------//
|
//----------------------//
|
// VARIABLES //
|
// VARIABLES //
|
//----------------------//
|
//----------------------//
|
wire[8:0] data_from_adc;
|
wire[8:0] data_from_adc;
|
reg triggered;
|
reg triggered;
|
reg[1:0] sm_adc_ram;
|
reg[1:0] sm_adc_ram;
|
reg[10:0] fifo_addr;
|
reg[10:0] fifo_addr;
|
reg[8:0] data_from_adc_buffered;
|
reg[8:0] data_from_adc_buffered;
|
reg[10:0] trig_addr;
|
reg[10:0] trig_addr;
|
wire[8:0] buf_adc_data;
|
wire[8:0] buf_adc_data;
|
reg[10:0] snap_addr, buf_adc_addr;
|
reg[10:0] snap_addr, buf_adc_addr;
|
|
|
|
|
|
|
//==================================================================//
|
//==================================================================//
|
// 'SUB-ROUTINES' //
|
// 'SUB-ROUTINES' //
|
//==================================================================//
|
//==================================================================//
|
//------------------------------------------------------------------//
|
//------------------------------------------------------------------//
|
// Instanstiate the ADC //
|
// Instanstiate the ADC //
|
//------------------------------------------------------------------//
|
//------------------------------------------------------------------//
|
|
|
Driver_ADC ADC(
|
Driver_ADC ADC(
|
.CLK_64MHZ(CLK_64MHZ),
|
.CLK_64MHZ(CLK_64MHZ),
|
.MASTER_RST(MASTER_RST),
|
.MASTER_RST(MASTER_RST),
|
.TIMESCALE(TIMESCALE),
|
.TIMESCALE(TIMESCALE),
|
.CLK_ADC(CLK_ADC),
|
.CLK_ADC(CLK_ADC),
|
.ADC_DATA(ADC_DATA),
|
.ADC_DATA(ADC_DATA),
|
.DATA_OUT(data_from_adc)
|
.DATA_OUT(data_from_adc)
|
);
|
);
|
|
|
//------------------------------------------------------------------//
|
//------------------------------------------------------------------//
|
// Initialize the RAMs WE WILL NEED MORE! //
|
// Initialize the RAMs WE WILL NEED MORE! //
|
// RAM is structured as follows: //
|
// RAM is structured as follows: //
|
// Dual-Access RAM //
|
// Dual-Access RAM //
|
// 18kBits -> 2048Bytes + 1Parity/Byte //
|
// 18kBits -> 2048Bytes + 1Parity/Byte //
|
// Access A: 8bit + 1parity (ADC_Write) //
|
// Access A: 8bit + 1parity (ADC_Write) //
|
// Access B: 8bit + 1parity (Read) //
|
// Access B: 8bit + 1parity (Read) //
|
//------------------------------------------------------------------//
|
//------------------------------------------------------------------//
|
wire VCC, GND;
|
wire VCC, GND;
|
assign VCC = 1'b1;
|
assign VCC = 1'b1;
|
assign GND = 1'b0;
|
assign GND = 1'b0;
|
|
|
// move the following into a more organized area
|
// move the following into a more organized area
|
wire[10:0] vert_adjustment;
|
wire[10:0] vert_adjustment;
|
assign vert_adjustment = (VERT_OFFSET);
|
assign vert_adjustment = (VERT_OFFSET);
|
|
|
RAMB16_S9_S9 ADC_QuasiFifo_Buffer(
|
RAMB16_S9_S9 ADC_QuasiFifo_Buffer(
|
.DOA(), .DOB(buf_adc_data[7:0]),
|
.DOA(), .DOB(buf_adc_data[7:0]),
|
.DOPA(), .DOPB(buf_adc_data[8]),
|
.DOPA(), .DOPB(buf_adc_data[8]),
|
.ADDRA(fifo_addr), .ADDRB(buf_adc_addr),
|
.ADDRA(fifo_addr), .ADDRB(buf_adc_addr),
|
.CLKA(CLK_ADC), .CLKB(CLK_ADC),
|
.CLKA(CLK_ADC), .CLKB(CLK_ADC),
|
.DIA(data_from_adc[7:0]), .DIB(8'b0),
|
.DIA(data_from_adc[7:0]), .DIB(8'b0),
|
.DIPA(data_from_adc[8]), .DIPB(GND),
|
.DIPA(data_from_adc[8]), .DIPB(GND),
|
.ENA(VCC), .ENB(VCC),
|
.ENA(VCC), .ENB(VCC),
|
.WEA(VCC), .WEB(GND),
|
.WEA(VCC), .WEB(GND),
|
.SSRA(GND), .SSRB(GND)
|
.SSRA(GND), .SSRB(GND)
|
);
|
);
|
|
|
RAMB16_S9_S9 ADC_Data_Snapshot(
|
RAMB16_S9_S9 ADC_Data_Snapshot(
|
.DOA(), .DOB(SNAP_DATA_EXT[7:0]),
|
.DOA(), .DOB(SNAP_DATA_EXT[7:0]),
|
.DOPA(), .DOPB(SNAP_DATA_EXT[8]),
|
.DOPA(), .DOPB(SNAP_DATA_EXT[8]),
|
.ADDRA(snap_addr), .ADDRB(SNAP_ADDR_EXT),
|
.ADDRA(snap_addr), .ADDRB(SNAP_ADDR_EXT),
|
.CLKA(CLK_ADC), .CLKB(SNAP_CLK_EXT),
|
.CLKA(CLK_ADC), .CLKB(SNAP_CLK_EXT),
|
.DIA(buf_adc_data[7:0]+vert_adjustment[7:0]), .DIB(8'b0), /* VERTICAL OFFSET */
|
.DIA(buf_adc_data[7:0]+vert_adjustment[7:0]), .DIB(8'b0), /* VERTICAL OFFSET */
|
.DIPA(buf_adc_data[8]+vert_adjustment[8]), .DIPB(GND), /* VERTICAL OFFSET */
|
.DIPA(buf_adc_data[8]+vert_adjustment[8]), .DIPB(GND), /* VERTICAL OFFSET */
|
.ENA(VCC), .ENB(VCC),
|
.ENA(VCC), .ENB(VCC),
|
.WEA(VCC), .WEB(GND),
|
.WEA(VCC), .WEB(GND),
|
.SSRA(GND), .SSRB(GND)
|
.SSRA(GND), .SSRB(GND)
|
);
|
);
|
|
|
|
|
//==================================================================//
|
//==================================================================//
|
// FUNCTIONAL DEFINITIONS //
|
// FUNCTIONAL DEFINITIONS //
|
//==================================================================//
|
//==================================================================//
|
|
|
/* STATE_MACHINE */
|
/* STATE_MACHINE */
|
always @ (posedge CLK_ADC or posedge MASTER_RST) begin
|
always @ (posedge CLK_ADC or posedge MASTER_RST) begin
|
if(MASTER_RST)
|
if(MASTER_RST)
|
sm_adc_ram <= ss_fifo_fill;
|
sm_adc_ram <= ss_fifo_fill;
|
else begin
|
else begin
|
// if(sm_adc_ram != ss_fifo_fill || sm_adc_ram != ss_fifo_half || sm_adc_ram != ss_save_snapshot)
|
// if(sm_adc_ram != ss_fifo_fill || sm_adc_ram != ss_fifo_half || sm_adc_ram != ss_save_snapshot)
|
// sm_adc_ram <= ss_fifo_fill;
|
// sm_adc_ram <= ss_fifo_fill;
|
if(sm_adc_ram == ss_fifo_fill && triggered)
|
if(sm_adc_ram == ss_fifo_fill && triggered)
|
sm_adc_ram <= ss_fifo_half;
|
sm_adc_ram <= ss_fifo_half;
|
else if(sm_adc_ram == ss_fifo_half && (fifo_addr == (trig_addr + 11'd1023)))
|
else if(sm_adc_ram == ss_fifo_half && (fifo_addr == (trig_addr + 11'd1023)))
|
sm_adc_ram <= ss_save_snapshot;
|
sm_adc_ram <= ss_save_snapshot;
|
else if(sm_adc_ram == ss_save_snapshot && snap_addr == 11'd2047)
|
else if(sm_adc_ram == ss_save_snapshot && snap_addr == 11'd2047)
|
sm_adc_ram <= ss_fifo_fill;
|
sm_adc_ram <= ss_fifo_fill;
|
else if(sm_adc_ram == ss_invalid)
|
else if(sm_adc_ram == ss_invalid)
|
sm_adc_ram <= ss_fifo_fill;
|
sm_adc_ram <= ss_fifo_fill;
|
else
|
else
|
sm_adc_ram <= sm_adc_ram;
|
sm_adc_ram <= sm_adc_ram;
|
end
|
end
|
end
|
end
|
|
|
/* FIFO ADDR */
|
/* FIFO ADDR */
|
always @ (posedge CLK_ADC or posedge MASTER_RST) begin
|
always @ (posedge CLK_ADC or posedge MASTER_RST) begin
|
if(MASTER_RST)
|
if(MASTER_RST)
|
fifo_addr <= 11'b0;
|
fifo_addr <= 11'b0;
|
else if(sm_adc_ram == ss_fifo_fill || sm_adc_ram == ss_fifo_half)
|
else if(sm_adc_ram == ss_fifo_fill || sm_adc_ram == ss_fifo_half)
|
fifo_addr <= fifo_addr + 1;
|
fifo_addr <= fifo_addr + 1;
|
else
|
else
|
fifo_addr <= fifo_addr;
|
fifo_addr <= fifo_addr;
|
end
|
end
|
|
|
/* TRIGGER */
|
/* TRIGGER */
|
always @ (posedge CLK_ADC or posedge MASTER_RST) begin
|
always @ (posedge CLK_ADC or posedge MASTER_RST) begin
|
if(MASTER_RST)
|
if(MASTER_RST)
|
data_from_adc_buffered <= 9'b0;
|
data_from_adc_buffered <= 9'b0;
|
else
|
else
|
data_from_adc_buffered <= data_from_adc;
|
data_from_adc_buffered <= data_from_adc;
|
end
|
end
|
|
|
always @ (posedge CLK_ADC or posedge MASTER_RST) begin
|
always @ (posedge CLK_ADC or posedge MASTER_RST) begin
|
if(MASTER_RST)
|
if(MASTER_RST)
|
triggered <= 1'b0;
|
triggered <= 1'b0;
|
else
|
else
|
triggered <= (TRIGGERSTYLE == 2'b00) && (data_from_adc_buffered < TRIGGER_LEVEL && data_from_adc >= TRIGGER_LEVEL) || // >=
|
triggered <= (TRIGGERSTYLE == 2'b00) && (data_from_adc_buffered < TRIGGER_LEVEL && data_from_adc >= TRIGGER_LEVEL) || // >=
|
(TRIGGERSTYLE == 2'b01) && (data_from_adc_buffered > TRIGGER_LEVEL && data_from_adc <= TRIGGER_LEVEL); // <=
|
(TRIGGERSTYLE == 2'b01) && (data_from_adc_buffered > TRIGGER_LEVEL && data_from_adc <= TRIGGER_LEVEL); // <=
|
end
|
end
|
|
|
always @ (posedge triggered or posedge MASTER_RST) begin
|
always @ (posedge triggered or posedge MASTER_RST) begin
|
if(MASTER_RST)
|
if(MASTER_RST)
|
trig_addr <= 11'b0;
|
trig_addr <= 11'b0;
|
else if(sm_adc_ram == ss_fifo_fill)
|
else if(sm_adc_ram == ss_fifo_fill)
|
trig_addr <= fifo_addr;
|
trig_addr <= fifo_addr;
|
else
|
else
|
trig_addr <= trig_addr;
|
trig_addr <= trig_addr;
|
end
|
end
|
|
|
/* SNAPSHOT */
|
/* SNAPSHOT */
|
always @ (posedge CLK_ADC or posedge MASTER_RST) begin
|
always @ (posedge CLK_ADC or posedge MASTER_RST) begin
|
if(MASTER_RST) begin
|
if(MASTER_RST) begin
|
snap_addr <= 11'b0;
|
snap_addr <= 11'b0;
|
buf_adc_addr <= 11'b0;
|
buf_adc_addr <= 11'b0;
|
end else if(sm_adc_ram == ss_save_snapshot) begin
|
end else if(sm_adc_ram == ss_save_snapshot) begin
|
snap_addr <= snap_addr + 1;
|
snap_addr <= snap_addr + 1;
|
buf_adc_addr <= buf_adc_addr + 1;
|
buf_adc_addr <= buf_adc_addr + 1;
|
end else begin
|
end else begin
|
buf_adc_addr <= trig_addr - (HORZ_OFFSET-11'd319); /* HORIZONTAL OFFSET */
|
buf_adc_addr <= trig_addr - (HORZ_OFFSET-11'd319); /* HORIZONTAL OFFSET */
|
snap_addr <= 11'b0;
|
snap_addr <= 11'b0;
|
end
|
end
|
end
|
end
|
|
|
endmodule
|
endmodule
|
|
|