//==================================================================
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//==================================================================
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// File: d_Driver_RamBuffer.v
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// File: d_Driver_RamBuffer.v
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// Version: 0.01
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// Version: 0.01
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// Copyright Stephen Pickett
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// Copyright Stephen Pickett
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// April 28, 2005
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// April 28, 2005
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//------------------------------------------------------------------
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//------------------------------------------------------------------
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// Revisions:
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// Revisions:
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// Ver 0.01 Apr 28, 2005 Initial Release
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// Ver 0.01 Apr 28, 2005 Initial Release
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//
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//
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//==================================================================
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//==================================================================
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module ADCDataBuffer(
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module ADCDataBuffer(
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CLK_64MHZ, MASTER_RST,
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CLK_64MHZ, MASTER_RST,
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CLK180_64MHZ,
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CLK180_64MHZ,
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TIME_BASE,
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TIME_BASE,
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RAM_ADDR, RAM_DATA, RAM_CLK,
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RAM_ADDR, RAM_DATA, RAM_CLK,
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ADC_DATA, ADC_CLK,
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ADC_DATA, ADC_CLK,
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TRIG_ADDR,
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TRIG_ADDR,
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VGA_WRITE_DONE,
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VGA_WRITE_DONE,
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TRIGGER_LEVEL,
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TRIGGER_LEVEL,
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sm_trig
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sm_trig
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);
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);
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//==================================================================//
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//==================================================================//
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// PARAMETER DEFINITIONS //
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// PARAMETER DEFINITIONS //
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//==================================================================//
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//==================================================================//
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parameter ss_wait_for_trig = 2'b00;
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parameter ss_wait_for_trig = 2'b00;
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parameter ss_fill_mem_half = 2'b01;
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parameter ss_fill_mem_half = 2'b01;
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parameter ss_write_buffer = 2'b11;
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parameter ss_write_buffer = 2'b11;
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parameter ss_invalid = 2'b10;
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parameter ss_invalid = 2'b10;
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parameter P_trigger_level = 8'h80;
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parameter P_trigger_level = 8'h80;
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//==================================================================//
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//==================================================================//
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// VARIABLE DEFINITIONS //
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// VARIABLE DEFINITIONS //
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//==================================================================//
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//==================================================================//
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//----------------------//
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//----------------------//
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// INPUTS / OUTPUTS //
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// INPUTS / OUTPUTS //
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//----------------------//
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//----------------------//
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input CLK_64MHZ;
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input CLK_64MHZ;
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input CLK180_64MHZ;
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input CLK180_64MHZ;
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input MASTER_RST; // Global Asyncronous Reset
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input MASTER_RST; // Global Asyncronous Reset
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input[5:0] TIME_BASE; // The selected V/Div
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input[5:0] TIME_BASE; // The selected V/Div
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input[10:0] RAM_ADDR;
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input[10:0] RAM_ADDR;
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output[7:0] RAM_DATA;
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output[7:0] RAM_DATA;
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input RAM_CLK;
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input RAM_CLK;
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input[7:0] ADC_DATA;
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input[7:0] ADC_DATA;
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output ADC_CLK;
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output ADC_CLK;
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output[10:0] TRIG_ADDR;
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output[10:0] TRIG_ADDR;
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input VGA_WRITE_DONE;
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input VGA_WRITE_DONE;
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input[8:0] TRIGGER_LEVEL;
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input[8:0] TRIGGER_LEVEL;
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output[1:0] sm_trig;
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output[1:0] sm_trig;
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//----------------------//
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//----------------------//
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// WIRES / NODES //
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// WIRES / NODES //
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//----------------------//
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//----------------------//
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wire CLK_64MHZ, MASTER_RST, CLK180_64MHZ;
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wire CLK_64MHZ, MASTER_RST, CLK180_64MHZ;
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wire[5:0] TIME_BASE;
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wire[5:0] TIME_BASE;
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wire[10:0] RAM_ADDR;
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wire[10:0] RAM_ADDR;
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wire[7:0] RAM_DATA;
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wire[7:0] RAM_DATA;
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wire RAM_CLK;
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wire RAM_CLK;
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wire[7:0] ADC_DATA;
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wire[7:0] ADC_DATA;
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wire ADC_CLK;
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wire ADC_CLK;
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reg[10:0] TRIG_ADDR;
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reg[10:0] TRIG_ADDR;
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wire VGA_WRITE_DONE;
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wire VGA_WRITE_DONE;
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wire[8:0] TRIGGER_LEVEL;
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wire[8:0] TRIGGER_LEVEL;
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//----------------------//
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//----------------------//
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// VARIABLES //
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// VARIABLES //
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//----------------------//
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//----------------------//
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//==================================================================//
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//==================================================================//
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// 'SUB-ROUTINES' //
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// 'SUB-ROUTINES' //
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//==================================================================//
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//==================================================================//
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//------------------------------------------------------------------//
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//------------------------------------------------------------------//
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// Instanstiate the ADC //
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// Instanstiate the ADC //
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//------------------------------------------------------------------//
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//------------------------------------------------------------------//
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wire[7:0] DATA_FROM_ADC;
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wire[7:0] DATA_FROM_ADC;
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Driver_ADC ADC(
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Driver_ADC ADC(
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.CLK_64MHZ(CLK_64MHZ),
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.CLK_64MHZ(CLK_64MHZ),
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.MASTER_RST(MASTER_RST),
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.MASTER_RST(MASTER_RST),
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.TIME_BASE(TIME_BASE),
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.TIME_BASE(TIME_BASE),
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.ADC_CLK(ADC_CLK),
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.ADC_CLK(ADC_CLK),
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.ADC_DATA(ADC_DATA),
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.ADC_DATA(ADC_DATA),
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.DATA_OUT(DATA_FROM_ADC)
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.DATA_OUT(DATA_FROM_ADC)
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);
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);
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//------------------------------------------------------------------//
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//------------------------------------------------------------------//
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// Initialize the RAMs WE WILL NEED MORE! //
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// Initialize the RAMs WE WILL NEED MORE! //
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// RAM is structured as follows: //
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// RAM is structured as follows: //
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// Dual-Access RAM //
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// Dual-Access RAM //
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// 18kBits -> 2048Bytes + 1Parity/Byte //
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// 18kBits -> 2048Bytes + 1Parity/Byte //
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// Access A: 8bit + 1parity (ADC_Write) //
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// Access A: 8bit + 1parity (ADC_Write) //
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// Access B: 8bit + 1parity (Read) //
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// Access B: 8bit + 1parity (Read) //
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//------------------------------------------------------------------//
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//------------------------------------------------------------------//
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reg[10:0] ADDRA;
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reg[10:0] ADDRA;
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wire VCC, GND;
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wire VCC, GND;
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assign VCC = 1'b1;
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assign VCC = 1'b1;
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assign GND = 1'b0;
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assign GND = 1'b0;
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RAMB16_S9_S9 ADC_QuasiFifo_Buffer(
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RAMB16_S9_S9 ADC_QuasiFifo_Buffer(
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.DOA(), .DOB(RAM_DATA),
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.DOA(), .DOB(RAM_DATA),
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.DOPA(), .DOPB(),
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.DOPA(), .DOPB(),
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.ADDRA(ADDRA), .ADDRB(RAM_ADDR),
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.ADDRA(ADDRA), .ADDRB(RAM_ADDR),
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.CLKA(CLK180_64MHZ), .CLKB(RAM_CLK),
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.CLKA(CLK180_64MHZ), .CLKB(RAM_CLK),
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.DIA(DATA_FROM_ADC), .DIB(8'b0),
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.DIA(DATA_FROM_ADC), .DIB(8'b0),
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.DIPA(GND), .DIPB(GND),
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.DIPA(GND), .DIPB(GND),
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.ENA(VCC), .ENB(VCC),
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.ENA(VCC), .ENB(VCC),
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.WEA(VCC), .WEB(GND),
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.WEA(VCC), .WEB(GND),
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.SSRA(GND), .SSRB(GND)
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.SSRA(GND), .SSRB(GND)
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);
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);
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//==================================================================//
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//==================================================================//
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// FUNCTIONAL DEFINITIONS //
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// FUNCTIONAL DEFINITIONS //
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//==================================================================//
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//==================================================================//
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reg[1:0] sm_trig;
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reg[1:0] sm_trig;
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reg trigger_detected;
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reg trigger_detected;
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reg[9:0] cnt_1024bytes;
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reg[9:0] cnt_1024bytes;
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reg mem_half_full;
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reg mem_half_full;
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/* THE RAM WRITING TRIGGERING STATE MACHINE */
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/* THE RAM WRITING TRIGGERING STATE MACHINE */
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always @ (posedge CLK_64MHZ or posedge MASTER_RST) begin
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always @ (posedge CLK_64MHZ or posedge MASTER_RST) begin
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if(MASTER_RST == 1'b1)
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if(MASTER_RST == 1'b1)
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sm_trig <= ss_wait_for_trig;
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sm_trig <= ss_wait_for_trig;
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else if(sm_trig == ss_wait_for_trig && trigger_detected == 1'b1)
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else if(sm_trig == ss_wait_for_trig && trigger_detected == 1'b1)
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sm_trig <= ss_fill_mem_half;
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sm_trig <= ss_fill_mem_half;
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else if(sm_trig == ss_fill_mem_half && mem_half_full == 1'b1)
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else if(sm_trig == ss_fill_mem_half && mem_half_full == 1'b1)
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sm_trig <= ss_write_buffer;
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sm_trig <= ss_write_buffer;
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else if(sm_trig == ss_write_buffer && /*trigger_detected == 1'b0 &&*/ VGA_WRITE_DONE == 1'b1)
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else if(sm_trig == ss_write_buffer && /*trigger_detected == 1'b0 &&*/ VGA_WRITE_DONE == 1'b1)
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sm_trig <= ss_wait_for_trig;
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sm_trig <= ss_wait_for_trig;
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else if(sm_trig == ss_invalid)
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else if(sm_trig == ss_invalid)
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sm_trig <= ss_wait_for_trig;
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sm_trig <= ss_wait_for_trig;
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else
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else
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sm_trig <= sm_trig;
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sm_trig <= sm_trig;
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end
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end
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/* THIS PART DEALS WITH THE ADDRESS OF THE ADC BUFFER */
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/* THIS PART DEALS WITH THE ADDRESS OF THE ADC BUFFER */
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/* Write in a Circular Buffer soft of way */
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/* Write in a Circular Buffer soft of way */
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always @ (posedge ADC_CLK or posedge MASTER_RST) begin
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always @ (posedge ADC_CLK or posedge MASTER_RST) begin
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if(MASTER_RST == 1'b1) begin
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if(MASTER_RST == 1'b1) begin
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ADDRA <= 11'b0;
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ADDRA <= 11'b0;
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end else if(sm_trig == ss_wait_for_trig || sm_trig == ss_fill_mem_half)
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end else if(sm_trig == ss_wait_for_trig || sm_trig == ss_fill_mem_half)
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ADDRA <= ADDRA + 1;
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ADDRA <= ADDRA + 1;
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else
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else
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ADDRA <= ADDRA;
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ADDRA <= ADDRA;
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// ADDRA <= ADDRA + 1;
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// ADDRA <= ADDRA + 1;
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end
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end
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/* LATCHING THE TRIGGER */
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/* LATCHING THE TRIGGER */
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always @ (ADC_DATA) begin
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always @ (ADC_DATA) begin
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if(ADC_DATA >= TRIGGER_LEVEL)
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if(ADC_DATA >= TRIGGER_LEVEL)
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trigger_detected = 1'b1;
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trigger_detected = 1'b1;
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else
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else
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trigger_detected = 1'b0;
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trigger_detected = 1'b0;
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end
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end
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/* GATHERING 1024 MORE BYTES OF MEMORY */
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/* GATHERING 1024 MORE BYTES OF MEMORY */
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always @ (posedge ADC_CLK or posedge MASTER_RST) begin
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always @ (posedge ADC_CLK or posedge MASTER_RST) begin
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if(MASTER_RST == 1'b1)
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if(MASTER_RST == 1'b1)
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cnt_1024bytes <= 10'b0;
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cnt_1024bytes <= 10'b0;
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else if(sm_trig == ss_fill_mem_half)
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else if(sm_trig == ss_fill_mem_half)
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cnt_1024bytes <= cnt_1024bytes + 1;
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cnt_1024bytes <= cnt_1024bytes + 1;
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else
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else
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cnt_1024bytes <= 10'b0;
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cnt_1024bytes <= 10'b0;
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// cnt_1024bytes <= cnt_1024bytes;
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// cnt_1024bytes <= cnt_1024bytes;
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end
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end
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always @ (cnt_1024bytes) begin
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always @ (cnt_1024bytes) begin
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if(cnt_1024bytes == 10'h3FF)
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if(cnt_1024bytes == 10'h3FF)
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mem_half_full = 1'b1;
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mem_half_full = 1'b1;
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else
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else
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mem_half_full = 1'b0;
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mem_half_full = 1'b0;
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end
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end
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/* STORING THE TRIGGER ADDRESS */
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/* STORING THE TRIGGER ADDRESS */
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always @ (posedge trigger_detected or posedge MASTER_RST) begin
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always @ (posedge trigger_detected or posedge MASTER_RST) begin
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if(MASTER_RST == 1'b1)
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if(MASTER_RST == 1'b1)
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TRIG_ADDR <= 11'd0;
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TRIG_ADDR <= 11'd0;
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else
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else
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TRIG_ADDR <= ADDRA;
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TRIG_ADDR <= ADDRA;
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end
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end
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endmodule
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endmodule
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