//==================================================================
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//==================================================================
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// File: d_MouseDriver.v
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// File: d_MouseDriver.v
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// Version: 0.01
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// Version: 0.01
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// Copyright Stephen Pickett, Clarke Ellis
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// Copyright Stephen Pickett, Clarke Ellis
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// April 28, 2005
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// April 28, 2005
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//------------------------------------------------------------------
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//------------------------------------------------------------------
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// Revisions:
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// Revisions:
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// Ver 0.01 Apr 28, 2005 Initial Release
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// Ver 0.01 Apr 28, 2005 Initial Release
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//
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//
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//==================================================================
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//==================================================================
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module sub_SegDriver(
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module sub_SegDriver(
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CLK_50MHZ, MASTER_RST,
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CLK_50MHZ, MASTER_RST,
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DATA_IN,
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DATA_IN,
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SEG_OUT, SEG_SEL
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SEG_OUT, SEG_SEL
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);
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);
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//==================================================================//
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//==================================================================//
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// VARIABLE DEFINITIONS //
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// VARIABLE DEFINITIONS //
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//==================================================================//
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//==================================================================//
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//----------------------//
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//----------------------//
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// INPUTS //
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// INPUTS //
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//----------------------//
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//----------------------//
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input CLK_50MHZ; // System wide clock
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input CLK_50MHZ; // System wide clock
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input MASTER_RST; // System wide reset
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input MASTER_RST; // System wide reset
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input[15:0] DATA_IN;
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input[15:0] DATA_IN;
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//----------------------//
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//----------------------//
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// OUTPUTS //
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// OUTPUTS //
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//----------------------//
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//----------------------//
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output[6:0] SEG_OUT;
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output[6:0] SEG_OUT;
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output[3:0] SEG_SEL;
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output[3:0] SEG_SEL;
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//----------------------//
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//----------------------//
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// WIRES / NODES //
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// WIRES / NODES //
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//----------------------//
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//----------------------//
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wire CLK_50MHZ, MASTER_RST;
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wire CLK_50MHZ, MASTER_RST;
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wire[15:0] DATA_IN;
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wire[15:0] DATA_IN;
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reg [6:0] SEG_OUT;
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reg [6:0] SEG_OUT;
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reg [3:0] SEG_SEL;
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reg [3:0] SEG_SEL;
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//----------------------//
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//----------------------//
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// REGISTERS //
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// REGISTERS //
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//----------------------//
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//----------------------//
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wire[6:0] seg0, seg1, seg2, seg3;
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wire[6:0] seg0, seg1, seg2, seg3;
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reg[7:0] clk_390kHz;
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reg[7:0] clk_390kHz;
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//==================================================================//
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//==================================================================//
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// FUNCTIONAL DEFINITIONS //
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// FUNCTIONAL DEFINITIONS //
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//==================================================================//
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//==================================================================//
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always @ (posedge CLK_50MHZ or posedge MASTER_RST) begin
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always @ (posedge CLK_50MHZ or posedge MASTER_RST) begin
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if(MASTER_RST == 1'b1)
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if(MASTER_RST == 1'b1)
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clk_390kHz <= 8'b0;
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clk_390kHz <= 8'b0;
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else
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else
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clk_390kHz <= clk_390kHz + 1;
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clk_390kHz <= clk_390kHz + 1;
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end
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end
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always @ (posedge clk_390kHz[7] or posedge MASTER_RST) begin
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always @ (posedge clk_390kHz[7] or posedge MASTER_RST) begin
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if(MASTER_RST == 1'b1)
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if(MASTER_RST == 1'b1)
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SEG_SEL <= 4'b1110;
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SEG_SEL <= 4'b1110;
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else begin
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else begin
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SEG_SEL[3:1] <= SEG_SEL[2:0];
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SEG_SEL[3:1] <= SEG_SEL[2:0];
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SEG_SEL[0] <= SEG_SEL[3];
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SEG_SEL[0] <= SEG_SEL[3];
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end
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end
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end
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end
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always @ (SEG_SEL or seg0 or seg1 or seg2 or seg3) begin
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always @ (SEG_SEL or seg0 or seg1 or seg2 or seg3) begin
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if(SEG_SEL == 4'b1110)
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if(SEG_SEL == 4'b1110)
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SEG_OUT = seg0;
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SEG_OUT = seg0;
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else if(SEG_SEL == 4'b1101)
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else if(SEG_SEL == 4'b1101)
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SEG_OUT = seg1;
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SEG_OUT = seg1;
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else if(SEG_SEL == 4'b1011)
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else if(SEG_SEL == 4'b1011)
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SEG_OUT = seg2;
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SEG_OUT = seg2;
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else if(SEG_SEL == 4'b0111)
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else if(SEG_SEL == 4'b0111)
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SEG_OUT = seg3;
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SEG_OUT = seg3;
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else
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else
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SEG_OUT = 7'b1111111;
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SEG_OUT = 7'b1111111;
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end
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end
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sub_HexSeg sub_seg3( .DATA_IN(DATA_IN[15:12]),
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sub_HexSeg sub_seg3( .DATA_IN(DATA_IN[15:12]),
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.SEG_OUT(seg3)
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.SEG_OUT(seg3)
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);
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);
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sub_HexSeg sub_seg2( .DATA_IN(DATA_IN[11:8]),
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sub_HexSeg sub_seg2( .DATA_IN(DATA_IN[11:8]),
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.SEG_OUT(seg2)
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.SEG_OUT(seg2)
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);
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);
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sub_HexSeg sub_seg1( .DATA_IN(DATA_IN[7:4]),
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sub_HexSeg sub_seg1( .DATA_IN(DATA_IN[7:4]),
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.SEG_OUT(seg1)
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.SEG_OUT(seg1)
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);
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);
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sub_HexSeg sub_seg0( .DATA_IN(DATA_IN[3:0]),
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sub_HexSeg sub_seg0( .DATA_IN(DATA_IN[3:0]),
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.SEG_OUT(seg0)
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.SEG_OUT(seg0)
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);
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);
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endmodule
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endmodule
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