//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
// AltOR32
|
// AltOR32
|
// Alternative Lightweight OpenRisc
|
// Alternative Lightweight OpenRisc
|
// V2.1
|
// V2.1
|
// Ultra-Embedded.com
|
// Ultra-Embedded.com
|
// Copyright 2011 - 2014
|
// Copyright 2011 - 2014
|
//
|
//
|
// Email: admin@ultra-embedded.com
|
// Email: admin@ultra-embedded.com
|
//
|
//
|
// License: LGPL
|
// License: LGPL
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
//
|
//
|
// Copyright (C) 2011 - 2013 Ultra-Embedded.com
|
// Copyright (C) 2011 - 2014 Ultra-Embedded.com
|
//
|
//
|
// This source file may be used and distributed without
|
// This source file may be used and distributed without
|
// restriction provided that this copyright statement is not
|
// restriction provided that this copyright statement is not
|
// removed from the file and that any derivative work contains
|
// removed from the file and that any derivative work contains
|
// the original copyright notice and the associated disclaimer.
|
// the original copyright notice and the associated disclaimer.
|
//
|
//
|
// This source file is free software; you can redistribute it
|
// This source file is free software; you can redistribute it
|
// and/or modify it under the terms of the GNU Lesser General
|
// and/or modify it under the terms of the GNU Lesser General
|
// Public License as published by the Free Software Foundation;
|
// Public License as published by the Free Software Foundation;
|
// either version 2.1 of the License, or (at your option) any
|
// either version 2.1 of the License, or (at your option) any
|
// later version.
|
// later version.
|
//
|
//
|
// This source is distributed in the hope that it will be
|
// This source is distributed in the hope that it will be
|
// useful, but WITHOUT ANY WARRANTY; without even the implied
|
// useful, but WITHOUT ANY WARRANTY; without even the implied
|
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
|
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
|
// PURPOSE. See the GNU Lesser General Public License for more
|
// PURPOSE. See the GNU Lesser General Public License for more
|
// details.
|
// details.
|
//
|
//
|
// You should have received a copy of the GNU Lesser General
|
// You should have received a copy of the GNU Lesser General
|
// Public License along with this source; if not, write to the
|
// Public License along with this source; if not, write to the
|
// Free Software Foundation, Inc., 59 Temple Place, Suite 330,
|
// Free Software Foundation, Inc., 59 Temple Place, Suite 330,
|
// Boston, MA 02111-1307 USA
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// Boston, MA 02111-1307 USA
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
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|
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
// Includes
|
// Includes
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
`include "altor32_defs.v"
|
`include "altor32_defs.v"
|
|
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
// Module - Simulation register file
|
// Module - Simulation register file
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
module altor32_regfile_sim
|
module altor32_regfile_sim
|
(
|
(
|
input clk_i /*verilator public*/,
|
input clk_i /*verilator public*/,
|
input rst_i /*verilator public*/,
|
input rst_i /*verilator public*/,
|
input wr_i /*verilator public*/,
|
input wr_i /*verilator public*/,
|
input [4:0] rs_i /*verilator public*/,
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input [4:0] ra_i /*verilator public*/,
|
input [4:0] rt_i /*verilator public*/,
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input [4:0] rb_i /*verilator public*/,
|
input [4:0] rd_i /*verilator public*/,
|
input [4:0] rd_i /*verilator public*/,
|
output reg [31:0] reg_rs_o /*verilator public*/,
|
output reg [31:0] reg_ra_o /*verilator public*/,
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output reg [31:0] reg_rt_o /*verilator public*/,
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output reg [31:0] reg_rb_o /*verilator public*/,
|
input [31:0] reg_rd_i /*verilator public*/
|
input [31:0] reg_rd_i /*verilator public*/
|
);
|
);
|
|
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
// Params
|
// Params
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
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parameter SUPPORT_32REGS = "ENABLED";
|
parameter SUPPORT_32REGS = "ENABLED";
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|
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
// Registers
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// Registers
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
|
|
// Register file
|
// Register file
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reg [31:0] reg_r1_sp;
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reg [31:0] reg_r1_sp;
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reg [31:0] reg_r2_fp;
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reg [31:0] reg_r2_fp;
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reg [31:0] reg_r3;
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reg [31:0] reg_r3;
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reg [31:0] reg_r4;
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reg [31:0] reg_r4;
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reg [31:0] reg_r5;
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reg [31:0] reg_r5;
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reg [31:0] reg_r6;
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reg [31:0] reg_r6;
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reg [31:0] reg_r7;
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reg [31:0] reg_r7;
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reg [31:0] reg_r8;
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reg [31:0] reg_r8;
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reg [31:0] reg_r9_lr;
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reg [31:0] reg_r9_lr;
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reg [31:0] reg_r10;
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reg [31:0] reg_r10;
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reg [31:0] reg_r11;
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reg [31:0] reg_r11;
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reg [31:0] reg_r12;
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reg [31:0] reg_r12;
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reg [31:0] reg_r13;
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reg [31:0] reg_r13;
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reg [31:0] reg_r14;
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reg [31:0] reg_r14;
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reg [31:0] reg_r15;
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reg [31:0] reg_r15;
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reg [31:0] reg_r16;
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reg [31:0] reg_r16;
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reg [31:0] reg_r17;
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reg [31:0] reg_r17;
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reg [31:0] reg_r18;
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reg [31:0] reg_r18;
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reg [31:0] reg_r19;
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reg [31:0] reg_r19;
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reg [31:0] reg_r20;
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reg [31:0] reg_r20;
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reg [31:0] reg_r21;
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reg [31:0] reg_r21;
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reg [31:0] reg_r22;
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reg [31:0] reg_r22;
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reg [31:0] reg_r23;
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reg [31:0] reg_r23;
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reg [31:0] reg_r24;
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reg [31:0] reg_r24;
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reg [31:0] reg_r25;
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reg [31:0] reg_r25;
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reg [31:0] reg_r26;
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reg [31:0] reg_r26;
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reg [31:0] reg_r27;
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reg [31:0] reg_r27;
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reg [31:0] reg_r28;
|
reg [31:0] reg_r28;
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reg [31:0] reg_r29;
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reg [31:0] reg_r29;
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reg [31:0] reg_r30;
|
reg [31:0] reg_r30;
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reg [31:0] reg_r31;
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reg [31:0] reg_r31;
|
|
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
// Register File (for simulation)
|
// Register File (for simulation)
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
|
|
// Synchronous register write back
|
// Synchronous register write back
|
always @ (posedge clk_i or posedge rst_i)
|
always @ (posedge clk_i or posedge rst_i)
|
begin
|
begin
|
if (rst_i)
|
if (rst_i)
|
begin
|
begin
|
reg_r1_sp <= 32'h00000000;
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reg_r1_sp <= 32'h00000000;
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reg_r2_fp <= 32'h00000000;
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reg_r2_fp <= 32'h00000000;
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reg_r3 <= 32'h00000000;
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reg_r3 <= 32'h00000000;
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reg_r4 <= 32'h00000000;
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reg_r4 <= 32'h00000000;
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reg_r5 <= 32'h00000000;
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reg_r5 <= 32'h00000000;
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reg_r6 <= 32'h00000000;
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reg_r6 <= 32'h00000000;
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reg_r7 <= 32'h00000000;
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reg_r7 <= 32'h00000000;
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reg_r8 <= 32'h00000000;
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reg_r8 <= 32'h00000000;
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reg_r9_lr <= 32'h00000000;
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reg_r9_lr <= 32'h00000000;
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reg_r10 <= 32'h00000000;
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reg_r10 <= 32'h00000000;
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reg_r11 <= 32'h00000000;
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reg_r11 <= 32'h00000000;
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reg_r12 <= 32'h00000000;
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reg_r12 <= 32'h00000000;
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reg_r13 <= 32'h00000000;
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reg_r13 <= 32'h00000000;
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reg_r14 <= 32'h00000000;
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reg_r14 <= 32'h00000000;
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reg_r15 <= 32'h00000000;
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reg_r15 <= 32'h00000000;
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reg_r16 <= 32'h00000000;
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reg_r16 <= 32'h00000000;
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reg_r17 <= 32'h00000000;
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reg_r17 <= 32'h00000000;
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reg_r18 <= 32'h00000000;
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reg_r18 <= 32'h00000000;
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reg_r19 <= 32'h00000000;
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reg_r19 <= 32'h00000000;
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reg_r20 <= 32'h00000000;
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reg_r20 <= 32'h00000000;
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reg_r21 <= 32'h00000000;
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reg_r21 <= 32'h00000000;
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reg_r22 <= 32'h00000000;
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reg_r22 <= 32'h00000000;
|
reg_r23 <= 32'h00000000;
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reg_r23 <= 32'h00000000;
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reg_r24 <= 32'h00000000;
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reg_r24 <= 32'h00000000;
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reg_r25 <= 32'h00000000;
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reg_r25 <= 32'h00000000;
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reg_r26 <= 32'h00000000;
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reg_r26 <= 32'h00000000;
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reg_r27 <= 32'h00000000;
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reg_r27 <= 32'h00000000;
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reg_r28 <= 32'h00000000;
|
reg_r28 <= 32'h00000000;
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reg_r29 <= 32'h00000000;
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reg_r29 <= 32'h00000000;
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reg_r30 <= 32'h00000000;
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reg_r30 <= 32'h00000000;
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reg_r31 <= 32'h00000000;
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reg_r31 <= 32'h00000000;
|
end
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end
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else
|
else
|
begin
|
begin
|
if (wr_i == 1'b1)
|
if (wr_i == 1'b1)
|
case (rd_i[4:0])
|
case (rd_i[4:0])
|
5'b00001 :
|
5'b00001 :
|
reg_r1_sp <= reg_rd_i;
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reg_r1_sp <= reg_rd_i;
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5'b00010 :
|
5'b00010 :
|
reg_r2_fp <= reg_rd_i;
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reg_r2_fp <= reg_rd_i;
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5'b00011 :
|
5'b00011 :
|
reg_r3 <= reg_rd_i;
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reg_r3 <= reg_rd_i;
|
5'b00100 :
|
5'b00100 :
|
reg_r4 <= reg_rd_i;
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reg_r4 <= reg_rd_i;
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5'b00101 :
|
5'b00101 :
|
reg_r5 <= reg_rd_i;
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reg_r5 <= reg_rd_i;
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5'b00110 :
|
5'b00110 :
|
reg_r6 <= reg_rd_i;
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reg_r6 <= reg_rd_i;
|
5'b00111 :
|
5'b00111 :
|
reg_r7 <= reg_rd_i;
|
reg_r7 <= reg_rd_i;
|
5'b01000 :
|
5'b01000 :
|
reg_r8 <= reg_rd_i;
|
reg_r8 <= reg_rd_i;
|
5'b01001 :
|
5'b01001 :
|
reg_r9_lr <= reg_rd_i;
|
reg_r9_lr <= reg_rd_i;
|
5'b01010 :
|
5'b01010 :
|
reg_r10 <= reg_rd_i;
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reg_r10 <= reg_rd_i;
|
5'b01011 :
|
5'b01011 :
|
reg_r11 <= reg_rd_i;
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reg_r11 <= reg_rd_i;
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5'b01100 :
|
5'b01100 :
|
reg_r12 <= reg_rd_i;
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reg_r12 <= reg_rd_i;
|
5'b01101 :
|
5'b01101 :
|
reg_r13 <= reg_rd_i;
|
reg_r13 <= reg_rd_i;
|
5'b01110 :
|
5'b01110 :
|
reg_r14 <= reg_rd_i;
|
reg_r14 <= reg_rd_i;
|
5'b01111 :
|
5'b01111 :
|
reg_r15 <= reg_rd_i;
|
reg_r15 <= reg_rd_i;
|
5'b10000 :
|
5'b10000 :
|
reg_r16 <= reg_rd_i;
|
reg_r16 <= reg_rd_i;
|
5'b10001 :
|
5'b10001 :
|
reg_r17 <= reg_rd_i;
|
reg_r17 <= reg_rd_i;
|
5'b10010 :
|
5'b10010 :
|
reg_r18 <= reg_rd_i;
|
reg_r18 <= reg_rd_i;
|
5'b10011 :
|
5'b10011 :
|
reg_r19 <= reg_rd_i;
|
reg_r19 <= reg_rd_i;
|
5'b10100 :
|
5'b10100 :
|
reg_r20 <= reg_rd_i;
|
reg_r20 <= reg_rd_i;
|
5'b10101 :
|
5'b10101 :
|
reg_r21 <= reg_rd_i;
|
reg_r21 <= reg_rd_i;
|
5'b10110 :
|
5'b10110 :
|
reg_r22 <= reg_rd_i;
|
reg_r22 <= reg_rd_i;
|
5'b10111 :
|
5'b10111 :
|
reg_r23 <= reg_rd_i;
|
reg_r23 <= reg_rd_i;
|
5'b11000 :
|
5'b11000 :
|
reg_r24 <= reg_rd_i;
|
reg_r24 <= reg_rd_i;
|
5'b11001 :
|
5'b11001 :
|
reg_r25 <= reg_rd_i;
|
reg_r25 <= reg_rd_i;
|
5'b11010 :
|
5'b11010 :
|
reg_r26 <= reg_rd_i;
|
reg_r26 <= reg_rd_i;
|
5'b11011 :
|
5'b11011 :
|
reg_r27 <= reg_rd_i;
|
reg_r27 <= reg_rd_i;
|
5'b11100 :
|
5'b11100 :
|
reg_r28 <= reg_rd_i;
|
reg_r28 <= reg_rd_i;
|
5'b11101 :
|
5'b11101 :
|
reg_r29 <= reg_rd_i;
|
reg_r29 <= reg_rd_i;
|
5'b11110 :
|
5'b11110 :
|
reg_r30 <= reg_rd_i;
|
reg_r30 <= reg_rd_i;
|
5'b11111 :
|
5'b11111 :
|
reg_r31 <= reg_rd_i;
|
reg_r31 <= reg_rd_i;
|
default :
|
default :
|
;
|
;
|
endcase
|
endcase
|
end
|
end
|
end
|
end
|
|
|
generate
|
generate
|
if (SUPPORT_32REGS == "ENABLED")
|
if (SUPPORT_32REGS == "ENABLED")
|
begin
|
begin
|
// Asynchronous Register read (Rs & Rd)
|
// Asynchronous Register read (Rs & Rd)
|
always @ *
|
always @ *
|
begin
|
begin
|
case (rs_i)
|
case (ra_i)
|
5'b00000 :
|
5'b00000 :
|
reg_rs_o = 32'h00000000;
|
reg_ra_o = 32'h00000000;
|
5'b00001 :
|
5'b00001 :
|
reg_rs_o = reg_r1_sp;
|
reg_ra_o = reg_r1_sp;
|
5'b00010 :
|
5'b00010 :
|
reg_rs_o = reg_r2_fp;
|
reg_ra_o = reg_r2_fp;
|
5'b00011 :
|
5'b00011 :
|
reg_rs_o = reg_r3;
|
reg_ra_o = reg_r3;
|
5'b00100 :
|
5'b00100 :
|
reg_rs_o = reg_r4;
|
reg_ra_o = reg_r4;
|
5'b00101 :
|
5'b00101 :
|
reg_rs_o = reg_r5;
|
reg_ra_o = reg_r5;
|
5'b00110 :
|
5'b00110 :
|
reg_rs_o = reg_r6;
|
reg_ra_o = reg_r6;
|
5'b00111 :
|
5'b00111 :
|
reg_rs_o = reg_r7;
|
reg_ra_o = reg_r7;
|
5'b01000 :
|
5'b01000 :
|
reg_rs_o = reg_r8;
|
reg_ra_o = reg_r8;
|
5'b01001 :
|
5'b01001 :
|
reg_rs_o = reg_r9_lr;
|
reg_ra_o = reg_r9_lr;
|
5'b01010 :
|
5'b01010 :
|
reg_rs_o = reg_r10;
|
reg_ra_o = reg_r10;
|
5'b01011 :
|
5'b01011 :
|
reg_rs_o = reg_r11;
|
reg_ra_o = reg_r11;
|
5'b01100 :
|
5'b01100 :
|
reg_rs_o = reg_r12;
|
reg_ra_o = reg_r12;
|
5'b01101 :
|
5'b01101 :
|
reg_rs_o = reg_r13;
|
reg_ra_o = reg_r13;
|
5'b01110 :
|
5'b01110 :
|
reg_rs_o = reg_r14;
|
reg_ra_o = reg_r14;
|
5'b01111 :
|
5'b01111 :
|
reg_rs_o = reg_r15;
|
reg_ra_o = reg_r15;
|
5'b10000 :
|
5'b10000 :
|
reg_rs_o = reg_r16;
|
reg_ra_o = reg_r16;
|
5'b10001 :
|
5'b10001 :
|
reg_rs_o = reg_r17;
|
reg_ra_o = reg_r17;
|
5'b10010 :
|
5'b10010 :
|
reg_rs_o = reg_r18;
|
reg_ra_o = reg_r18;
|
5'b10011 :
|
5'b10011 :
|
reg_rs_o = reg_r19;
|
reg_ra_o = reg_r19;
|
5'b10100 :
|
5'b10100 :
|
reg_rs_o = reg_r20;
|
reg_ra_o = reg_r20;
|
5'b10101 :
|
5'b10101 :
|
reg_rs_o = reg_r21;
|
reg_ra_o = reg_r21;
|
5'b10110 :
|
5'b10110 :
|
reg_rs_o = reg_r22;
|
reg_ra_o = reg_r22;
|
5'b10111 :
|
5'b10111 :
|
reg_rs_o = reg_r23;
|
reg_ra_o = reg_r23;
|
5'b11000 :
|
5'b11000 :
|
reg_rs_o = reg_r24;
|
reg_ra_o = reg_r24;
|
5'b11001 :
|
5'b11001 :
|
reg_rs_o = reg_r25;
|
reg_ra_o = reg_r25;
|
5'b11010 :
|
5'b11010 :
|
reg_rs_o = reg_r26;
|
reg_ra_o = reg_r26;
|
5'b11011 :
|
5'b11011 :
|
reg_rs_o = reg_r27;
|
reg_ra_o = reg_r27;
|
5'b11100 :
|
5'b11100 :
|
reg_rs_o = reg_r28;
|
reg_ra_o = reg_r28;
|
5'b11101 :
|
5'b11101 :
|
reg_rs_o = reg_r29;
|
reg_ra_o = reg_r29;
|
5'b11110 :
|
5'b11110 :
|
reg_rs_o = reg_r30;
|
reg_ra_o = reg_r30;
|
5'b11111 :
|
5'b11111 :
|
reg_rs_o = reg_r31;
|
reg_ra_o = reg_r31;
|
default :
|
default :
|
reg_rs_o = 32'h00000000;
|
reg_ra_o = 32'h00000000;
|
endcase
|
endcase
|
|
|
case (rt_i)
|
case (rb_i)
|
5'b00000 :
|
5'b00000 :
|
reg_rt_o = 32'h00000000;
|
reg_rb_o = 32'h00000000;
|
5'b00001 :
|
5'b00001 :
|
reg_rt_o = reg_r1_sp;
|
reg_rb_o = reg_r1_sp;
|
5'b00010 :
|
5'b00010 :
|
reg_rt_o = reg_r2_fp;
|
reg_rb_o = reg_r2_fp;
|
5'b00011 :
|
5'b00011 :
|
reg_rt_o = reg_r3;
|
reg_rb_o = reg_r3;
|
5'b00100 :
|
5'b00100 :
|
reg_rt_o = reg_r4;
|
reg_rb_o = reg_r4;
|
5'b00101 :
|
5'b00101 :
|
reg_rt_o = reg_r5;
|
reg_rb_o = reg_r5;
|
5'b00110 :
|
5'b00110 :
|
reg_rt_o = reg_r6;
|
reg_rb_o = reg_r6;
|
5'b00111 :
|
5'b00111 :
|
reg_rt_o = reg_r7;
|
reg_rb_o = reg_r7;
|
5'b01000 :
|
5'b01000 :
|
reg_rt_o = reg_r8;
|
reg_rb_o = reg_r8;
|
5'b01001 :
|
5'b01001 :
|
reg_rt_o = reg_r9_lr;
|
reg_rb_o = reg_r9_lr;
|
5'b01010 :
|
5'b01010 :
|
reg_rt_o = reg_r10;
|
reg_rb_o = reg_r10;
|
5'b01011 :
|
5'b01011 :
|
reg_rt_o = reg_r11;
|
reg_rb_o = reg_r11;
|
5'b01100 :
|
5'b01100 :
|
reg_rt_o = reg_r12;
|
reg_rb_o = reg_r12;
|
5'b01101 :
|
5'b01101 :
|
reg_rt_o = reg_r13;
|
reg_rb_o = reg_r13;
|
5'b01110 :
|
5'b01110 :
|
reg_rt_o = reg_r14;
|
reg_rb_o = reg_r14;
|
5'b01111 :
|
5'b01111 :
|
reg_rt_o = reg_r15;
|
reg_rb_o = reg_r15;
|
5'b10000 :
|
5'b10000 :
|
reg_rt_o = reg_r16;
|
reg_rb_o = reg_r16;
|
5'b10001 :
|
5'b10001 :
|
reg_rt_o = reg_r17;
|
reg_rb_o = reg_r17;
|
5'b10010 :
|
5'b10010 :
|
reg_rt_o = reg_r18;
|
reg_rb_o = reg_r18;
|
5'b10011 :
|
5'b10011 :
|
reg_rt_o = reg_r19;
|
reg_rb_o = reg_r19;
|
5'b10100 :
|
5'b10100 :
|
reg_rt_o = reg_r20;
|
reg_rb_o = reg_r20;
|
5'b10101 :
|
5'b10101 :
|
reg_rt_o = reg_r21;
|
reg_rb_o = reg_r21;
|
5'b10110 :
|
5'b10110 :
|
reg_rt_o = reg_r22;
|
reg_rb_o = reg_r22;
|
5'b10111 :
|
5'b10111 :
|
reg_rt_o = reg_r23;
|
reg_rb_o = reg_r23;
|
5'b11000 :
|
5'b11000 :
|
reg_rt_o = reg_r24;
|
reg_rb_o = reg_r24;
|
5'b11001 :
|
5'b11001 :
|
reg_rt_o = reg_r25;
|
reg_rb_o = reg_r25;
|
5'b11010 :
|
5'b11010 :
|
reg_rt_o = reg_r26;
|
reg_rb_o = reg_r26;
|
5'b11011 :
|
5'b11011 :
|
reg_rt_o = reg_r27;
|
reg_rb_o = reg_r27;
|
5'b11100 :
|
5'b11100 :
|
reg_rt_o = reg_r28;
|
reg_rb_o = reg_r28;
|
5'b11101 :
|
5'b11101 :
|
reg_rt_o = reg_r29;
|
reg_rb_o = reg_r29;
|
5'b11110 :
|
5'b11110 :
|
reg_rt_o = reg_r30;
|
reg_rb_o = reg_r30;
|
5'b11111 :
|
5'b11111 :
|
reg_rt_o = reg_r31;
|
reg_rb_o = reg_r31;
|
default :
|
default :
|
reg_rt_o = 32'h00000000;
|
reg_rb_o = 32'h00000000;
|
endcase
|
endcase
|
end
|
end
|
end
|
end
|
else
|
else
|
begin
|
begin
|
// Asynchronous Register read (Rs & Rd)
|
// Asynchronous Register read (Rs & Rd)
|
always @ *
|
always @ *
|
begin
|
begin
|
case (rs_i)
|
case (ra_i)
|
5'b00000 :
|
5'b00000 :
|
reg_rs_o = 32'h00000000;
|
reg_ra_o = 32'h00000000;
|
5'b00001 :
|
5'b00001 :
|
reg_rs_o = reg_r1_sp;
|
reg_ra_o = reg_r1_sp;
|
5'b00010 :
|
5'b00010 :
|
reg_rs_o = reg_r2_fp;
|
reg_ra_o = reg_r2_fp;
|
5'b00011 :
|
5'b00011 :
|
reg_rs_o = reg_r3;
|
reg_ra_o = reg_r3;
|
5'b00100 :
|
5'b00100 :
|
reg_rs_o = reg_r4;
|
reg_ra_o = reg_r4;
|
5'b00101 :
|
5'b00101 :
|
reg_rs_o = reg_r5;
|
reg_ra_o = reg_r5;
|
5'b00110 :
|
5'b00110 :
|
reg_rs_o = reg_r6;
|
reg_ra_o = reg_r6;
|
5'b00111 :
|
5'b00111 :
|
reg_rs_o = reg_r7;
|
reg_ra_o = reg_r7;
|
5'b01000 :
|
5'b01000 :
|
reg_rs_o = reg_r8;
|
reg_ra_o = reg_r8;
|
5'b01001 :
|
5'b01001 :
|
reg_rs_o = reg_r9_lr;
|
reg_ra_o = reg_r9_lr;
|
5'b01010 :
|
5'b01010 :
|
reg_rs_o = reg_r10;
|
reg_ra_o = reg_r10;
|
5'b01011 :
|
5'b01011 :
|
reg_rs_o = reg_r11;
|
reg_ra_o = reg_r11;
|
5'b01100 :
|
5'b01100 :
|
reg_rs_o = reg_r12;
|
reg_ra_o = reg_r12;
|
5'b01101 :
|
5'b01101 :
|
reg_rs_o = reg_r13;
|
reg_ra_o = reg_r13;
|
5'b01110 :
|
5'b01110 :
|
reg_rs_o = reg_r14;
|
reg_ra_o = reg_r14;
|
5'b01111 :
|
5'b01111 :
|
reg_rs_o = reg_r15;
|
reg_ra_o = reg_r15;
|
default :
|
default :
|
reg_rs_o = 32'h00000000;
|
reg_ra_o = 32'h00000000;
|
endcase
|
endcase
|
|
|
case (rt_i)
|
case (rb_i)
|
5'b00000 :
|
5'b00000 :
|
reg_rt_o = 32'h00000000;
|
reg_rb_o = 32'h00000000;
|
5'b00001 :
|
5'b00001 :
|
reg_rt_o = reg_r1_sp;
|
reg_rb_o = reg_r1_sp;
|
5'b00010 :
|
5'b00010 :
|
reg_rt_o = reg_r2_fp;
|
reg_rb_o = reg_r2_fp;
|
5'b00011 :
|
5'b00011 :
|
reg_rt_o = reg_r3;
|
reg_rb_o = reg_r3;
|
5'b00100 :
|
5'b00100 :
|
reg_rt_o = reg_r4;
|
reg_rb_o = reg_r4;
|
5'b00101 :
|
5'b00101 :
|
reg_rt_o = reg_r5;
|
reg_rb_o = reg_r5;
|
5'b00110 :
|
5'b00110 :
|
reg_rt_o = reg_r6;
|
reg_rb_o = reg_r6;
|
5'b00111 :
|
5'b00111 :
|
reg_rt_o = reg_r7;
|
reg_rb_o = reg_r7;
|
5'b01000 :
|
5'b01000 :
|
reg_rt_o = reg_r8;
|
reg_rb_o = reg_r8;
|
5'b01001 :
|
5'b01001 :
|
reg_rt_o = reg_r9_lr;
|
reg_rb_o = reg_r9_lr;
|
5'b01010 :
|
5'b01010 :
|
reg_rt_o = reg_r10;
|
reg_rb_o = reg_r10;
|
5'b01011 :
|
5'b01011 :
|
reg_rt_o = reg_r11;
|
reg_rb_o = reg_r11;
|
5'b01100 :
|
5'b01100 :
|
reg_rt_o = reg_r12;
|
reg_rb_o = reg_r12;
|
5'b01101 :
|
5'b01101 :
|
reg_rt_o = reg_r13;
|
reg_rb_o = reg_r13;
|
5'b01110 :
|
5'b01110 :
|
reg_rt_o = reg_r14;
|
reg_rb_o = reg_r14;
|
5'b01111 :
|
5'b01111 :
|
reg_rt_o = reg_r15;
|
reg_rb_o = reg_r15;
|
default :
|
default :
|
reg_rt_o = 32'h00000000;
|
reg_rb_o = 32'h00000000;
|
endcase
|
endcase
|
end
|
end
|
end
|
end
|
endgenerate
|
endgenerate
|
|
|
endmodule
|
endmodule
|
|
|