//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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// AltOR32
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// AltOR32
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// Alternative Lightweight OpenRisc
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// Alternative Lightweight OpenRisc
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// V2.0
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// V2.0
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// Ultra-Embedded.com
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// Ultra-Embedded.com
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// Copyright 2011 - 2013
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// Copyright 2011 - 2013
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//
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//
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// Email: admin@ultra-embedded.com
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// Email: admin@ultra-embedded.com
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//
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//
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// License: LGPL
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// License: LGPL
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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//
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//
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// Copyright (C) 2011 - 2013 Ultra-Embedded.com
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// Copyright (C) 2011 - 2013 Ultra-Embedded.com
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//
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//
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// This source file may be used and distributed without
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// This source file may be used and distributed without
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// restriction provided that this copyright statement is not
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// restriction provided that this copyright statement is not
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// removed from the file and that any derivative work contains
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// removed from the file and that any derivative work contains
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// the original copyright notice and the associated disclaimer.
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// the original copyright notice and the associated disclaimer.
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//
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//
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// This source file is free software; you can redistribute it
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// This source file is free software; you can redistribute it
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// and/or modify it under the terms of the GNU Lesser General
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// and/or modify it under the terms of the GNU Lesser General
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// Public License as published by the Free Software Foundation;
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// Public License as published by the Free Software Foundation;
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// either version 2.1 of the License, or (at your option) any
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// either version 2.1 of the License, or (at your option) any
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// later version.
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// later version.
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//
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//
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// This source is distributed in the hope that it will be
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// This source is distributed in the hope that it will be
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// useful, but WITHOUT ANY WARRANTY; without even the implied
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// useful, but WITHOUT ANY WARRANTY; without even the implied
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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// PURPOSE. See the GNU Lesser General Public License for more
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// PURPOSE. See the GNU Lesser General Public License for more
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// details.
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// details.
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//
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//
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// You should have received a copy of the GNU Lesser General
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// You should have received a copy of the GNU Lesser General
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// Public License along with this source; if not, write to the
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// Public License along with this source; if not, write to the
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// Free Software Foundation, Inc., 59 Temple Place, Suite 330,
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// Free Software Foundation, Inc., 59 Temple Place, Suite 330,
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// Boston, MA 02111-1307 USA
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// Boston, MA 02111-1307 USA
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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// Includes
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// Includes
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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`include "timer_defs.v"
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`include "timer_defs.v"
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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// Module:
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// Module:
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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module timer_periph
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module timer_periph
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(
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(
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// General - Clocking & Reset
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// General - Clocking & Reset
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clk_i,
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clk_i,
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rst_i,
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rst_i,
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// Interrupts
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// Interrupts
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intr_systick_o,
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intr_systick_o,
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intr_hires_o,
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intr_hires_o,
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// Peripheral bus
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// Peripheral bus
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addr_i,
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addr_i,
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data_o,
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data_o,
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data_i,
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data_i,
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wr_i,
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we_i,
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rd_i
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stb_i
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);
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);
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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// Params
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// Params
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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parameter [31:0] CLK_KHZ = 12288;
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parameter [31:0] CLK_KHZ = 12288;
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parameter SYSTICK_INTR_MS = 1;
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parameter SYSTICK_INTR_MS = 1;
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parameter ENABLE_SYSTICK_TIMER = "ENABLED";
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parameter ENABLE_SYSTICK_TIMER = "ENABLED";
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parameter ENABLE_HIGHRES_TIMER = "ENABLED";
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parameter ENABLE_HIGHRES_TIMER = "ENABLED";
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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// I/O
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// I/O
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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input clk_i /*verilator public*/;
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input clk_i /*verilator public*/;
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input rst_i /*verilator public*/;
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input rst_i /*verilator public*/;
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output intr_systick_o /*verilator public*/;
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output intr_systick_o /*verilator public*/;
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output intr_hires_o /*verilator public*/;
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output intr_hires_o /*verilator public*/;
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input [7:0] addr_i /*verilator public*/;
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input [7:0] addr_i /*verilator public*/;
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output [31:0] data_o /*verilator public*/;
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output [31:0] data_o /*verilator public*/;
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input [31:0] data_i /*verilator public*/;
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input [31:0] data_i /*verilator public*/;
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input [3:0] wr_i /*verilator public*/;
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input we_i /*verilator public*/;
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input rd_i /*verilator public*/;
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input stb_i /*verilator public*/;
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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// Registers / Wires
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// Registers / Wires
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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reg [31:0] data_o;
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reg [31:0] data_o;
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// Systick Timer
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// Systick Timer
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reg systick_event;
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reg systick_event;
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reg [31:0] systick_count;
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reg [31:0] systick_count;
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reg [31:0] systick_clk_count;
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reg [31:0] systick_clk_count;
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// Hi-res system clock tick counter
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// Hi-res system clock tick counter
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reg hr_timer_intr;
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reg hr_timer_intr;
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reg [31:0] hr_timer_cnt;
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reg [31:0] hr_timer_cnt;
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reg [31:0] hr_timer_match;
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reg [31:0] hr_timer_match;
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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// Systick
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// Systick
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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generate
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generate
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if (ENABLE_SYSTICK_TIMER == "ENABLED")
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if (ENABLE_SYSTICK_TIMER == "ENABLED")
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begin
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begin
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// SysTick Timer (1 ms resolution)
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// SysTick Timer (1 ms resolution)
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always @ (posedge rst_i or posedge clk_i )
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always @ (posedge rst_i or posedge clk_i )
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begin
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begin
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if (rst_i == 1'b1)
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if (rst_i == 1'b1)
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begin
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begin
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systick_count <= 32'h00000000;
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systick_count <= 32'h00000000;
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systick_clk_count <= 32'h00000000;
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systick_clk_count <= 32'h00000000;
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systick_event <= 1'b0;
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systick_event <= 1'b0;
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end
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end
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else
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else
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begin
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begin
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systick_event <= 1'b0;
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systick_event <= 1'b0;
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if (systick_clk_count == CLK_KHZ)
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if (systick_clk_count == CLK_KHZ)
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begin
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begin
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systick_count <= (systick_count + 1);
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systick_count <= (systick_count + 1);
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systick_event <= 1'b1;
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systick_event <= 1'b1;
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systick_clk_count <= 32'h00000000;
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systick_clk_count <= 32'h00000000;
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end
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end
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else
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else
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systick_clk_count <= (systick_clk_count + 1);
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systick_clk_count <= (systick_clk_count + 1);
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end
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end
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end
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end
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// SysTick Interrupt
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// SysTick Interrupt
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integer systick_event_count;
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integer systick_event_count;
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reg systick_event_intr;
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reg systick_event_intr;
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always @ (posedge rst_i or posedge clk_i )
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always @ (posedge rst_i or posedge clk_i )
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begin
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begin
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if (rst_i == 1'b1)
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if (rst_i == 1'b1)
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begin
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begin
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systick_event_count <= 0;
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systick_event_count <= 0;
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systick_event_intr <= 1'b0;
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systick_event_intr <= 1'b0;
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end
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end
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else
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else
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begin
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begin
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systick_event_intr <= 1'b0;
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systick_event_intr <= 1'b0;
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if (systick_event)
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if (systick_event)
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begin
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begin
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systick_event_count <= (systick_event_count + 1);
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systick_event_count <= (systick_event_count + 1);
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if (systick_event_count == (SYSTICK_INTR_MS-1))
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if (systick_event_count == (SYSTICK_INTR_MS-1))
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begin
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begin
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systick_event_intr <= 1'b1;
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systick_event_intr <= 1'b1;
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systick_event_count <= 0;
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systick_event_count <= 0;
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end
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end
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end
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end
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end
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end
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end
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end
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assign intr_systick_o = systick_event_intr;
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assign intr_systick_o = systick_event_intr;
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end
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end
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else
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else
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begin
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begin
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// Systick disabled
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// Systick disabled
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always @ (posedge rst_i or posedge clk_i )
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always @ (posedge rst_i or posedge clk_i )
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begin
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begin
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if (rst_i == 1'b1)
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if (rst_i == 1'b1)
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systick_count <= 32'h00000000;
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systick_count <= 32'h00000000;
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else
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else
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systick_count <= 32'h00000000;
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systick_count <= 32'h00000000;
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end
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end
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assign intr_systick_o = 1'b0;
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assign intr_systick_o = 1'b0;
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end
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end
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endgenerate
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endgenerate
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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// Hi Resolution Timer
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// Hi Resolution Timer
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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generate
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generate
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if (ENABLE_HIGHRES_TIMER == "ENABLED")
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if (ENABLE_HIGHRES_TIMER == "ENABLED")
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begin
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begin
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always @ (posedge rst_i or posedge clk_i)
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always @ (posedge rst_i or posedge clk_i)
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begin
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begin
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if (rst_i == 1'b1)
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if (rst_i == 1'b1)
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begin
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begin
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hr_timer_cnt <= 32'h00000000;
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hr_timer_cnt <= 32'h00000000;
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hr_timer_intr <= 1'b0;
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hr_timer_intr <= 1'b0;
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end
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end
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else
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else
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begin
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begin
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hr_timer_intr <= 1'b0;
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hr_timer_intr <= 1'b0;
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// Clock tick counter
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// Clock tick counter
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hr_timer_cnt <= (hr_timer_cnt + 1);
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hr_timer_cnt <= (hr_timer_cnt + 1);
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// Hi-res Timer IRQ
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// Hi-res Timer IRQ
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if ((hr_timer_match != 32'h00000000) && (hr_timer_match == hr_timer_cnt))
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if ((hr_timer_match != 32'h00000000) && (hr_timer_match == hr_timer_cnt))
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hr_timer_intr <= 1'b1;
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hr_timer_intr <= 1'b1;
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end
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end
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end
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end
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assign intr_hires_o = hr_timer_intr;
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assign intr_hires_o = hr_timer_intr;
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end
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end
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else
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else
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begin
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begin
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// Hi resolution timer disabled
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// Hi resolution timer disabled
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always @ (posedge rst_i or posedge clk_i )
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always @ (posedge rst_i or posedge clk_i )
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begin
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begin
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if (rst_i == 1'b1)
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if (rst_i == 1'b1)
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hr_timer_cnt <= 32'h00000000;
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hr_timer_cnt <= 32'h00000000;
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else
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else
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hr_timer_cnt <= 32'h00000000;
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hr_timer_cnt <= 32'h00000000;
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end
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end
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assign intr_hires_o = 1'b0;
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assign intr_hires_o = 1'b0;
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end
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end
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endgenerate
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endgenerate
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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// Peripheral Register Write
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// Peripheral Register Write
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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always @ (posedge rst_i or posedge clk_i )
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always @ (posedge rst_i or posedge clk_i )
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begin
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begin
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if (rst_i == 1'b1)
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if (rst_i == 1'b1)
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begin
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begin
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hr_timer_match <= 32'h00000000;
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hr_timer_match <= 32'h00000000;
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end
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end
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else
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else
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begin
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begin
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// Write Cycle
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// Write Cycle
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if (wr_i != 4'b0000)
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if (we_i & stb_i)
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begin
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begin
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case (addr_i)
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case (addr_i)
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`TIMER_HIRES :
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`TIMER_HIRES :
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hr_timer_match <= data_i;
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hr_timer_match <= data_i;
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default :
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default :
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;
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;
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endcase
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endcase
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end
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end
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end
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end
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end
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end
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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// Peripheral Register Read
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// Peripheral Register Read
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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always @ (posedge rst_i or posedge clk_i )
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always @ *
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begin
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if (rst_i == 1'b1)
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begin
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data_o <= 32'h00000000;
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end
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else
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begin
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// Read cycle?
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if (rd_i == 1'b1)
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begin
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begin
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case (addr_i[7:0])
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case (addr_i[7:0])
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// 32-bit systick/1ms counter
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// 32-bit systick/1ms counter
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`TIMER_SYSTICK_VAL :
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`TIMER_SYSTICK_VAL :
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data_o <= systick_count;
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data_o = systick_count;
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// Hi res timer (clock rate)
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// Hi res timer (clock rate)
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`TIMER_HIRES :
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`TIMER_HIRES :
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data_o <= hr_timer_cnt;
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data_o = hr_timer_cnt;
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default :
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default :
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data_o <= 32'h00000000;
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data_o = 32'h00000000;
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endcase
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endcase
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end
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end
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end
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end
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endmodule
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endmodule
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