//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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// AltOR32
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// AltOR32
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// Alternative Lightweight OpenRisc
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// Alternative Lightweight OpenRisc
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// V2.0
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// V2.0
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// Ultra-Embedded.com
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// Ultra-Embedded.com
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// Copyright 2011 - 2013
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// Copyright 2011 - 2013
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//
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//
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// Email: admin@ultra-embedded.com
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// Email: admin@ultra-embedded.com
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//
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//
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// License: LGPL
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// License: LGPL
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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//
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//
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// Copyright (C) 2011 - 2013 Ultra-Embedded.com
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// Copyright (C) 2011 - 2013 Ultra-Embedded.com
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//
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//
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// This source file may be used and distributed without
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// This source file may be used and distributed without
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// restriction provided that this copyright statement is not
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// restriction provided that this copyright statement is not
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// removed from the file and that any derivative work contains
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// removed from the file and that any derivative work contains
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// the original copyright notice and the associated disclaimer.
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// the original copyright notice and the associated disclaimer.
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//
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//
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// This source file is free software; you can redistribute it
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// This source file is free software; you can redistribute it
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// and/or modify it under the terms of the GNU Lesser General
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// and/or modify it under the terms of the GNU Lesser General
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// Public License as published by the Free Software Foundation;
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// Public License as published by the Free Software Foundation;
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// either version 2.1 of the License, or (at your option) any
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// either version 2.1 of the License, or (at your option) any
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// later version.
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// later version.
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//
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//
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// This source is distributed in the hope that it will be
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// This source is distributed in the hope that it will be
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// useful, but WITHOUT ANY WARRANTY; without even the implied
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// useful, but WITHOUT ANY WARRANTY; without even the implied
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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// PURPOSE. See the GNU Lesser General Public License for more
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// PURPOSE. See the GNU Lesser General Public License for more
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// details.
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// details.
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//
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//
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// You should have received a copy of the GNU Lesser General
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// You should have received a copy of the GNU Lesser General
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// Public License along with this source; if not, write to the
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// Public License along with this source; if not, write to the
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// Free Software Foundation, Inc., 59 Temple Place, Suite 330,
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// Free Software Foundation, Inc., 59 Temple Place, Suite 330,
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// Boston, MA 02111-1307 USA
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// Boston, MA 02111-1307 USA
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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// Module
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// Module
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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module top
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module top
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(
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(
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// Clocking & Reset
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// Clocking & Reset
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input clk_i,
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input clk_i,
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input rst_i,
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input rst_i,
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// Fault Output
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// Fault Output
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output fault_o,
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output fault_o,
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// Break Output
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// Break Output
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output break_o,
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output break_o,
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// Interrupt Input
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// Interrupt Input
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input intr_i
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input intr_i
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);
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);
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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// Params
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// Params
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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parameter CLK_KHZ = 8192;
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parameter CLK_KHZ = 8192;
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parameter BOOT_VECTOR = 32'h10000000;
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parameter BOOT_VECTOR = 32'h10000000;
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parameter ISR_VECTOR = 32'h10000000;
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parameter ISR_VECTOR = 32'h10000000;
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|
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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// Registers / Wires
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// Registers / Wires
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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wire [31:0] soc_addr;
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wire [31:0] soc_addr;
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wire [31:0] soc_data_w;
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wire [31:0] soc_data_w;
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wire [31:0] soc_data_r;
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wire [31:0] soc_data_r;
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wire [3:0] soc_wr;
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wire soc_we;
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wire soc_rd;
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wire soc_stb;
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wire soc_ack;
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wire soc_irq;
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wire soc_irq;
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wire[31:0] dmem_address;
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wire[31:0] dmem_address;
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wire[31:0] dmem_data_w;
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wire[31:0] dmem_data_w;
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wire[31:0] dmem_data_r;
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wire[31:0] dmem_data_r;
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wire[3:0] dmem_wr;
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wire[3:0] dmem_sel;
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wire dmem_rd;
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wire[2:0] dmem_cti;
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wire dmem_burst;
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wire dmem_we;
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wire dmem_stb;
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wire dmem_cyc;
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wire dmem_stall;
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wire dmem_ack;
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wire dmem_ack;
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reg dmem_req_r;
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wire[31:0] imem_addr;
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wire[31:0] imem_addr;
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wire[31:0] imem_data;
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wire[31:0] imem_data;
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wire imem_rd;
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wire[3:0] imem_sel;
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wire imem_burst;
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wire imem_stb;
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wire imem_cyc;
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wire[2:0] imem_cti;
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wire imem_stall;
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wire imem_ack;
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wire imem_ack;
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reg imem_req_r;
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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// Instantiation
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// Instantiation
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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// BlockRAM
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// BlockRAM
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ram
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ram
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#(
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#(
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.block_count(128) // 1MB
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.block_count(128) // 1MB
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)
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)
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u_ram
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u_ram
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(
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(
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.clka_i(clk_i),
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.clka_i(clk_i),
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.ena_i(1'b1),
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.rsta_i(rst_i),
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.wea_i(4'b0),
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.stba_i(imem_stb),
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.wea_i(1'b0),
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.sela_i(imem_sel),
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.addra_i(imem_addr[31:2]),
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.addra_i(imem_addr[31:2]),
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.dataa_i(32'b0),
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.dataa_i(32'b0),
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.dataa_o(imem_data),
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.dataa_o(imem_data),
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.acka_o(imem_ack),
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.clkb_i(clk_i),
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.clkb_i(clk_i),
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.enb_i(1'b1),
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.rstb_i(rst_i),
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.web_i(dmem_wr),
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.stbb_i(dmem_stb),
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.web_i(dmem_we),
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.selb_i(dmem_sel),
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.addrb_i(dmem_address[31:2]),
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.addrb_i(dmem_address[31:2]),
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.datab_i(dmem_data_w),
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.datab_i(dmem_data_w),
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.datab_o(dmem_data_r)
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.datab_o(dmem_data_r),
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.ackb_o(dmem_ack)
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);
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);
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// CPU
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// CPU
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cpu_if
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cpu_if
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#(
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#(
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.CLK_KHZ(CLK_KHZ),
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.CLK_KHZ(CLK_KHZ),
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.BOOT_VECTOR(32'h10000000),
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.BOOT_VECTOR(32'h10000000),
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.ISR_VECTOR(32'h10000000),
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.ISR_VECTOR(32'h10000000),
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.ENABLE_ICACHE("ENABLED"),
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.ENABLE_ICACHE("ENABLED"),
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.ENABLE_DCACHE("ENABLED"),
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.ENABLE_DCACHE("ENABLED"),
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.REGISTER_FILE_TYPE("SIMULATION")
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.REGISTER_FILE_TYPE("SIMULATION")
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)
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)
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u_cpu
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u_cpu
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(
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(
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// General - clocking & reset
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// General - clocking & reset
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.clk_i(clk_i),
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.clk_i(clk_i),
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.rst_i(rst_i),
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.rst_i(rst_i),
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.fault_o(fault_o),
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.fault_o(fault_o),
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.break_o(break_o),
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.break_o(break_o),
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.nmi_i(1'b0),
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.nmi_i(1'b0),
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.intr_i(soc_irq),
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.intr_i(soc_irq),
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// Instruction Memory 0 (0x10000000 - 0x10FFFFFF)
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// Instruction Memory 0 (0x10000000 - 0x10FFFFFF)
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.imem0_addr_o(imem_addr),
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.imem0_addr_o(imem_addr),
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.imem0_rd_o(imem_rd),
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.imem0_data_i(imem_data),
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.imem0_burst_o(imem_burst),
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.imem0_sel_o(imem_sel),
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.imem0_data_in_i(imem_data),
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.imem0_cti_o(imem_cti),
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.imem0_accept_i(1'b1),
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.imem0_cyc_o(imem_cyc),
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.imem0_stb_o(imem_stb),
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.imem0_stall_i(1'b0),
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.imem0_ack_i(imem_ack),
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.imem0_ack_i(imem_ack),
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// Data Memory 0 (0x10000000 - 0x10FFFFFF)
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// Data Memory 0 (0x10000000 - 0x10FFFFFF)
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.dmem0_addr_o(dmem_address),
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.dmem0_addr_o(dmem_address),
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.dmem0_data_o(dmem_data_w),
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.dmem0_data_o(dmem_data_w),
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.dmem0_data_i(dmem_data_r),
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.dmem0_data_i(dmem_data_r),
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.dmem0_wr_o(dmem_wr),
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.dmem0_sel_o(dmem_sel),
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.dmem0_rd_o(dmem_rd),
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.dmem0_cti_o(dmem_cti),
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.dmem0_accept_i(1'b1),
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.dmem0_cyc_o(dmem_cyc),
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.dmem0_burst_o(dmem_burst),
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.dmem0_we_o(dmem_we),
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.dmem0_stb_o(dmem_stb),
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.dmem0_stall_i(1'b0),
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.dmem0_ack_i(dmem_ack),
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.dmem0_ack_i(dmem_ack),
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// Data Memory 1 (0x11000000 - 0x11FFFFFF)
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// Data Memory 1 (0x11000000 - 0x11FFFFFF)
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.dmem1_addr_o(),
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.dmem1_addr_o(/*open*/),
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.dmem1_data_o(),
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.dmem1_data_o(/*open*/),
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.dmem1_data_i(32'b0),
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.dmem1_data_i(32'b0),
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.dmem1_wr_o(),
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.dmem1_sel_o(/*open*/),
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.dmem1_rd_o(),
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.dmem1_we_o(/*open*/),
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.dmem1_accept_i(1'b1),
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.dmem1_stb_o(/*open*/),
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.dmem1_burst_o(/*open*/),
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.dmem1_cyc_o(/*open*/),
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.dmem1_cti_o(/*open*/),
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.dmem1_stall_i(1'b0),
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.dmem1_ack_i(1'b1),
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.dmem1_ack_i(1'b1),
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// Data Memory 2 (0x12000000 - 0x12FFFFFF)
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// Data Memory 2 (0x12000000 - 0x12FFFFFF)
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.dmem2_addr_o(soc_addr),
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.dmem2_addr_o(soc_addr),
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.dmem2_data_o(soc_data_w),
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.dmem2_data_o(soc_data_w),
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.dmem2_data_i(soc_data_r),
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.dmem2_data_i(soc_data_r),
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.dmem2_wr_o(soc_wr),
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.dmem2_sel_o(/*open*/),
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.dmem2_rd_o(soc_rd),
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.dmem2_we_o(soc_we),
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.dmem2_accept_i(1'b1),
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.dmem2_stb_o(soc_stb),
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.dmem2_burst_o(/*open*/),
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.dmem2_cyc_o(/*open*/),
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.dmem2_ack_i(1'b1)
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.dmem2_cti_o(/*open*/),
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.dmem2_stall_i(1'b0),
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.dmem2_ack_i(soc_ack)
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);
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);
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// CPU SOC
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// CPU SOC
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soc
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soc
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#(
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#(
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.CLK_KHZ(CLK_KHZ),
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.CLK_KHZ(CLK_KHZ),
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.ENABLE_SYSTICK_TIMER("ENABLED"),
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.ENABLE_SYSTICK_TIMER("ENABLED"),
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.ENABLE_HIGHRES_TIMER("ENABLED"),
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.ENABLE_HIGHRES_TIMER("ENABLED"),
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.EXTERNAL_INTERRUPTS(1)
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.EXTERNAL_INTERRUPTS(1)
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)
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)
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u_soc
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u_soc
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(
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(
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// General - clocking & reset
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// General - clocking & reset
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.clk_i(clk_i),
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.clk_i(clk_i),
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.rst_i(rst_i),
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.rst_i(rst_i),
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.ext_intr_i(1'b0),
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.ext_intr_i(1'b0),
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.intr_o(soc_irq),
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.intr_o(soc_irq),
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// Memory Port
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// Memory Port
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.io_addr_i(soc_addr),
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.io_addr_i(soc_addr),
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.io_data_i(soc_data_w),
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.io_data_i(soc_data_w),
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.io_data_o(soc_data_r),
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.io_data_o(soc_data_r),
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.io_wr_i(soc_wr),
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.io_we_i(soc_we),
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.io_rd_i(soc_rd)
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.io_stb_i(soc_stb),
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.io_ack_o(soc_ack)
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);
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);
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// Ack
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always @(posedge clk_i or posedge rst_i)
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begin
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if (rst_i == 1'b1)
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begin
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imem_req_r <= 1'b0;
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end
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else
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begin
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imem_req_r <= imem_rd;
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end
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end
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assign imem_ack = imem_req_r;
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// Ack
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always @(posedge clk_i or posedge rst_i)
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begin
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if (rst_i == 1'b1)
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begin
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dmem_req_r <= 1'b0;
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end
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else
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begin
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dmem_req_r <= dmem_rd | (|dmem_wr);
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end
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end
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assign dmem_ack = dmem_req_r;
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endmodule
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endmodule
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