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[/] [alu_with_selectable_inputs_and_outputs/] [tags/] [arelease/] [tests/] [improved_test.v] - Diff between revs 3 and 4

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/////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////
////                                                             ////
////                                                             ////
////      This project has been provided to you on behalf of:    ////
////      This project has been provided to you on behalf of:    ////
////                                                             ////
////                                                             ////
////            S.C. ASICArt S.R.L.                              ////
////            S.C. ASICArt S.R.L.                              ////
////                            www.asicart.com                  ////
////                            www.asicart.com                  ////
////                            eli_f@asicart.com                ////
////                            eli_f@asicart.com                ////
////                                                             ////
////                                                             ////
////        Author: Dragos Constantin Doncean                    ////
////        Author: Dragos Constantin Doncean                    ////
////        Email: doncean@asicart.com                           ////
////        Email: doncean@asicart.com                           ////
////        Mobile: +40-740-936997                               ////
////        Mobile: +40-740-936997                               ////
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////      Downloaded from: http://www.opencores.org/             ////
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/////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////
////                                                             ////
////                                                             ////
//// Copyright (C) 2007 Dragos Constantin Doncean                ////
//// Copyright (C) 2007 Dragos Constantin Doncean                ////
////                         www.asicart.com                     ////
////                         www.asicart.com                     ////
////                         doncean@asicart.com                 ////
////                         doncean@asicart.com                 ////
////                                                             ////
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/////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////
 
 
 
 
//TEST MODULE - IMPROVED TEST
//TEST MODULE - IMPROVED TEST
 
 
module proj_improved_test;
module proj_improved_test;
 
 
wire test_clk, test_res, test_stb;
wire test_clk, test_res, test_stb;
wire [1:0] test_sel;
wire [1:0] test_sel;
wire [7:0] test_data_in_0, test_data_in_1, test_data_in_2;
wire [7:0] test_data_in_0, test_data_in_1, test_data_in_2;
wire test_data_valid_in;
wire test_data_valid_in;
wire test_valid_0, test_valid_1;
wire test_valid_0, test_valid_1;
wire [15:0] test_out_0, test_out_1;
wire [15:0] test_out_0, test_out_1;
wire test_parity_0, test_parity_1;
wire test_parity_0, test_parity_1;
wire [7:0] test_ic_data_0, test_ic_data_1, test_ic_data_2, test_ic_data_3;
wire [7:0] test_ic_data_0, test_ic_data_1, test_ic_data_2, test_ic_data_3;
wire [15:0] test_oc_data;
wire [15:0] test_oc_data;
wire test_oc_parity;
wire test_oc_parity;
wire [0:127] test_ic_data_collected, test_oc_data_collected;
wire [0:127] test_ic_data_collected, test_oc_data_collected;
 
 
//DUT instantiation
//DUT instantiation
DUT dut(.dut_clk(test_clk), .dut_res(test_res), .dut_stb(test_stb),
DUT dut(.dut_clk(test_clk), .dut_res(test_res), .dut_stb(test_stb),
                .dut_sel(test_sel),
                .dut_sel(test_sel),
                .dut_data_in_0(test_data_in_0), .dut_data_in_1(test_data_in_1), .dut_data_in_2(test_data_in_2),
                .dut_data_in_0(test_data_in_0), .dut_data_in_1(test_data_in_1), .dut_data_in_2(test_data_in_2),
                .dut_data_valid_in(test_data_valid_in),
                .dut_data_valid_in(test_data_valid_in),
                .dut_valid_0(test_valid_0), .dut_valid_1(test_valid_1),
                .dut_valid_0(test_valid_0), .dut_valid_1(test_valid_1),
                .dut_out_0(test_out_0), .dut_out_1(test_out_1),
                .dut_out_0(test_out_0), .dut_out_1(test_out_1),
                .dut_parity_0(test_parity_0), .dut_parity_1(test_parity_1));
                .dut_parity_0(test_parity_0), .dut_parity_1(test_parity_1));
 
 
//DUT VERIFICATION ENVIRONMENT
//DUT VERIFICATION ENVIRONMENT
//Contains CLK generator, monitors, BFMs, collectors and the checker
//Contains CLK generator, monitors, BFMs, collectors and the checker
//They are instantiated here, in the test module
//They are instantiated here, in the test module
 
 
//--------BFMs' instantiations--------
//--------BFMs' instantiations--------
CLK_GEN clk_gen(.gen_clk(test_clk));
CLK_GEN clk_gen(.gen_clk(test_clk));
 
 
RES_BFM res_bfm(.bfm_res(test_res));
RES_BFM res_bfm(.bfm_res(test_res));
 
 
DATA_IN_BFM data_in_bfm(.bfm_stb(test_stb),
DATA_IN_BFM data_in_bfm(.bfm_stb(test_stb),
        .bfm_sel(test_sel),
        .bfm_sel(test_sel),
        .bfm_data_in_0(test_data_in_0), .bfm_data_in_1(test_data_in_1), .bfm_data_in_2(test_data_in_2),
        .bfm_data_in_0(test_data_in_0), .bfm_data_in_1(test_data_in_1), .bfm_data_in_2(test_data_in_2),
        .bfm_data_valid_in(test_data_valid_in));
        .bfm_data_valid_in(test_data_valid_in));
 
 
//--------Monitors' instantiations--------
//--------Monitors' instantiations--------
CLK_MONITOR clk_monitor(.m_clk(test_clk));
CLK_MONITOR clk_monitor(.m_clk(test_clk));
 
 
RES_MONITOR res_monitor(.m_res(test_res));
RES_MONITOR res_monitor(.m_res(test_res));
 
 
STB_MONITOR stb_monitor(.m_clk(test_clk), .m_stb(test_stb));
STB_MONITOR stb_monitor(.m_clk(test_clk), .m_stb(test_stb));
 
 
SEL_MONITOR sel_monitor(.m_clk(test_clk), .m_stb(test_stb), .m_sel(test_sel));
SEL_MONITOR sel_monitor(.m_clk(test_clk), .m_stb(test_stb), .m_sel(test_sel));
 
 
DATA_IN_MONITOR data_in_monitor(.m_clk(test_clk), .m_stb(test_stb),
DATA_IN_MONITOR data_in_monitor(.m_clk(test_clk), .m_stb(test_stb),
        .m_data_in_0(test_data_in_0), .m_data_in_1(test_data_in_1), .m_data_in_2(test_data_in_2));
        .m_data_in_0(test_data_in_0), .m_data_in_1(test_data_in_1), .m_data_in_2(test_data_in_2));
 
 
DATA_VALID_IN_MONITOR data_valid_in_monitor(.m_clk(test_clk), .m_stb(test_stb),
DATA_VALID_IN_MONITOR data_valid_in_monitor(.m_clk(test_clk), .m_stb(test_stb),
        .m_data_valid_in(test_data_valid_in));
        .m_data_valid_in(test_data_valid_in));
 
 
VALID_MONITOR valid_monitor(.m_clk(test_clk), .m_res(test_res),
VALID_MONITOR valid_monitor(.m_clk(test_clk), .m_res(test_res),
        .m_valid_0(test_valid_0), .m_valid_1(test_valid_1));
        .m_valid_0(test_valid_0), .m_valid_1(test_valid_1));
 
 
DATA_OUT_MONITOR data_out_monitor(.m_clk(test_clk), .m_res(test_res),
DATA_OUT_MONITOR data_out_monitor(.m_clk(test_clk), .m_res(test_res),
        .m_out_0(test_out_0), .m_out_1(test_out_1));
        .m_out_0(test_out_0), .m_out_1(test_out_1));
 
 
PARITY_MONITOR parity_monitor(.m_clk(test_clk), .m_res(test_res),
PARITY_MONITOR parity_monitor(.m_clk(test_clk), .m_res(test_res),
        .m_parity_0(test_parity_0), .m_parity_1(test_parity_1));
        .m_parity_0(test_parity_0), .m_parity_1(test_parity_1));
 
 
//--------Collectors' instantiations--------
//--------Collectors' instantiations--------
INPUT_COLLECTOR input_collector(.ic_clk(test_clk), .ic_res(test_res), .ic_stb(test_stb),
INPUT_COLLECTOR input_collector(.ic_clk(test_clk), .ic_res(test_res), .ic_stb(test_stb),
        .ic_sel(test_sel),
        .ic_sel(test_sel),
        .ic_data_in_0(test_data_in_0), .ic_data_in_1(test_data_in_1), .ic_data_in_2(test_data_in_2),
        .ic_data_in_0(test_data_in_0), .ic_data_in_1(test_data_in_1), .ic_data_in_2(test_data_in_2),
        .ic_data_valid_in(test_data_valid_in),
        .ic_data_valid_in(test_data_valid_in),
        .ic_data_out_0(test_ic_data_0), .ic_data_out_1(test_ic_data_1), .ic_data_out_2(test_ic_data_2), .ic_data_out_3(test_ic_data_3),
        .ic_data_out_0(test_ic_data_0), .ic_data_out_1(test_ic_data_1), .ic_data_out_2(test_ic_data_2), .ic_data_out_3(test_ic_data_3),
        .ic_data_collected(test_ic_data_collected));
        .ic_data_collected(test_ic_data_collected));
 
 
OUTPUT_COLLECTOR output_collector(.oc_clk(test_clk), .oc_res(test_res),
OUTPUT_COLLECTOR output_collector(.oc_clk(test_clk), .oc_res(test_res),
        .oc_valid_0(test_valid_0), .oc_valid_1(test_valid_1),
        .oc_valid_0(test_valid_0), .oc_valid_1(test_valid_1),
        .oc_out_0(test_out_0), .oc_out_1(test_out_1),
        .oc_out_0(test_out_0), .oc_out_1(test_out_1),
        .oc_parity_0(test_parity_0), .oc_parity_1(test_parity_1),
        .oc_parity_0(test_parity_0), .oc_parity_1(test_parity_1),
        .oc_data(test_oc_data),
        .oc_data(test_oc_data),
        .oc_parity(test_oc_parity),
        .oc_parity(test_oc_parity),
        .oc_data_collected(test_oc_data_collected));
        .oc_data_collected(test_oc_data_collected));
 
 
//--------Checker's instantiation--------
//--------Checker's instantiation--------
CHECKER checker(.c_clk(test_clk), .c_res(test_res),
CHECKER checker(.c_clk(test_clk), .c_res(test_res),
        .ic_data_0(test_ic_data_0), .ic_data_1(test_ic_data_1), .ic_data_2(test_ic_data_2), .ic_data_3(test_ic_data_3),
        .ic_data_0(test_ic_data_0), .ic_data_1(test_ic_data_1), .ic_data_2(test_ic_data_2), .ic_data_3(test_ic_data_3),
        .oc_data(test_oc_data),
        .oc_data(test_oc_data),
        .oc_parity(test_oc_parity),
        .oc_parity(test_oc_parity),
        .ic_data_collected(test_ic_data_collected),
        .ic_data_collected(test_ic_data_collected),
        .oc_data_collected(test_oc_data_collected));
        .oc_data_collected(test_oc_data_collected));
 
 
//Waveform database
//Waveform database
initial
initial
begin
begin
 
 
        $shm_open("../run/waves/waves_improved_test");  // Open database named "waves"
        $shm_open("../run/waves/waves_improved_test");  // Open database named "waves"
        $shm_probe(proj_improved_test, "AS"); // Record tb scope and all sub hierarchy
        $shm_probe(proj_improved_test, "AS"); // Record tb scope and all sub hierarchy
end
end
 
 
/*
/*
//for waveform viewing with GTKWave
//for waveform viewing with GTKWave
initial
initial
begin
begin
        $dumpfile ("proj0.dump") ;
        $dumpfile ("proj0.dump") ;
        $dumpvars;
        $dumpvars;
        $dumpon;
        $dumpon;
        //$dumpall;
        //$dumpall;
end
end
*/
*/
 
 
endmodule
endmodule
 
 

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