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Subversion Repositories alu_with_selectable_inputs_and_outputs

[/] [alu_with_selectable_inputs_and_outputs/] [trunk/] [verif_env/] [collectors/] [input_collector.v] - Diff between revs 2 and 4

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/////////////////////////////////////////////////////////////////////
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////                                                             ////
////                                                             ////
////      This project has been provided to you on behalf of:    ////
////      This project has been provided to you on behalf of:    ////
////                                                             ////
////                                                             ////
////            S.C. ASICArt S.R.L.                              ////
////            S.C. ASICArt S.R.L.                              ////
////                            www.asicart.com                  ////
////                            www.asicart.com                  ////
////                            eli_f@asicart.com                ////
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////        Author: Dragos Constantin Doncean                    ////
////        Author: Dragos Constantin Doncean                    ////
////        Email: doncean@asicart.com                           ////
////        Email: doncean@asicart.com                           ////
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//// Copyright (C) 2007 Dragos Constantin Doncean                ////
//// Copyright (C) 2007 Dragos Constantin Doncean                ////
////                         www.asicart.com                     ////
////                         www.asicart.com                     ////
////                         doncean@asicart.com                 ////
////                         doncean@asicart.com                 ////
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//----------------Collectors----------------
//----------------Collectors----------------
 
 
//INPUT COLLECTOR
//INPUT COLLECTOR
 
 
module INPUT_COLLECTOR(ic_clk, ic_res, ic_stb,
module INPUT_COLLECTOR(ic_clk, ic_res, ic_stb,
        ic_sel,
        ic_sel,
        ic_data_in_0, ic_data_in_1, ic_data_in_2,
        ic_data_in_0, ic_data_in_1, ic_data_in_2,
        ic_data_valid_in,
        ic_data_valid_in,
        ic_data_out_0, ic_data_out_1, ic_data_out_2, ic_data_out_3,
        ic_data_out_0, ic_data_out_1, ic_data_out_2, ic_data_out_3,
        ic_data_collected);
        ic_data_collected);
 
 
input ic_clk, ic_res, ic_stb;
input ic_clk, ic_res, ic_stb;
input [1:0] ic_sel;
input [1:0] ic_sel;
input [7:0] ic_data_in_0, ic_data_in_1, ic_data_in_2;
input [7:0] ic_data_in_0, ic_data_in_1, ic_data_in_2;
input ic_data_valid_in;
input ic_data_valid_in;
output [7:0] ic_data_out_0, ic_data_out_1, ic_data_out_2, ic_data_out_3;
output [7:0] ic_data_out_0, ic_data_out_1, ic_data_out_2, ic_data_out_3;
output [0:127] ic_data_collected;
output [0:127] ic_data_collected;
 
 
reg ic_stb_was_1;
reg ic_stb_was_1;
 
 
reg [7:0] ic_data_out_0, ic_data_out_1, ic_data_out_2, ic_data_out_3;
reg [7:0] ic_data_out_0, ic_data_out_1, ic_data_out_2, ic_data_out_3;
reg [0:127] ic_data_collected;
reg [0:127] ic_data_collected;
 
 
reg [7:0] ic_data[0:3];
reg [7:0] ic_data[0:3];
integer i, j, k;
integer i, j, k;
 
 
integer fh;
integer fh;
 
 
always @ (posedge ic_clk or posedge ic_res)
always @ (posedge ic_clk or posedge ic_res)
if(ic_res)
if(ic_res)
begin
begin
        ic_stb_was_1 = 0;
        ic_stb_was_1 = 0;
        ic_data_out_0 = 0;
        ic_data_out_0 = 0;
        ic_data_out_1 = 0;
        ic_data_out_1 = 0;
        ic_data_out_2 = 0;
        ic_data_out_2 = 0;
        ic_data_out_3 = 0;
        ic_data_out_3 = 0;
        ic_data_collected = 0;
        ic_data_collected = 0;
        for(j = 0; j < 4; j = j + 1)
        for(j = 0; j < 4; j = j + 1)
                ic_data[j] = 0;
                ic_data[j] = 0;
        i = 0;
        i = 0;
        j = 0;
        j = 0;
        k = 0;
        k = 0;
end
end
else
else
begin
begin
        if(ic_stb)
        if(ic_stb)
                ic_stb_was_1 = 1;
                ic_stb_was_1 = 1;
        if(ic_data_valid_in)
        if(ic_data_valid_in)
        begin
        begin
                case(ic_sel)
                case(ic_sel)
                        'd0: ic_data[k] = ic_data_in_0;
                        'd0: ic_data[k] = ic_data_in_0;
                        'd1: ic_data[k] = ic_data_in_1;
                        'd1: ic_data[k] = ic_data_in_1;
                        'd2: ic_data[k] = ic_data_in_2;
                        'd2: ic_data[k] = ic_data_in_2;
                endcase
                endcase
                k = k + 1;
                k = k + 1;
        end
        end
        else
        else
        begin
        begin
                if(ic_stb_was_1)
                if(ic_stb_was_1)
                begin
                begin
                        k = 0;
                        k = 0;
                        for(j = 0; j < 4; j = j + 1)
                        for(j = 0; j < 4; j = j + 1)
                                case(j)
                                case(j)
                                        'd0: ic_data_out_0 = ic_data[j];
                                        'd0: ic_data_out_0 = ic_data[j];
                                        'd1: ic_data_out_1 = ic_data[j];
                                        'd1: ic_data_out_1 = ic_data[j];
                                        'd2: ic_data_out_2 = ic_data[j];
                                        'd2: ic_data_out_2 = ic_data[j];
                                        'd3: ic_data_out_3 = ic_data[j];
                                        'd3: ic_data_out_3 = ic_data[j];
                                endcase
                                endcase
                end
                end
                if(ic_stb_was_1)
                if(ic_stb_was_1)
                begin
                begin
                        ic_data_collected[i] = 1;
                        ic_data_collected[i] = 1;
                        i = i + 1;
                        i = i + 1;
                        ic_stb_was_1 = 0;
                        ic_stb_was_1 = 0;
                end
                end
        end
        end
end
end
 
 
//Print INPUT COLLECTOR buffer contents
//Print INPUT COLLECTOR buffer contents
always @ (i)
always @ (i)
begin
begin
        if(fh === 32'bx)
        if(fh === 32'bx)
                fh = $fopen("input_collector.out");
                fh = $fopen("input_collector.out");
 
 
        $fdisplay(fh, "%0d INFO: Input Transaction no: %0d", $time, i);
        $fdisplay(fh, "%0d INFO: Input Transaction no: %0d", $time, i);
        $fdisplay(fh, "%0d INFO: ic_data_out_0 = %b", $time, ic_data_out_0);
        $fdisplay(fh, "%0d INFO: ic_data_out_0 = %b", $time, ic_data_out_0);
        // split ic_data_out_0
        // split ic_data_out_0
        $fdisplay(fh, "\tINFO: operator type = %0d", ic_data_out_0[7:4]);
        $fdisplay(fh, "\tINFO: operator type = %0d", ic_data_out_0[7:4]);
        $fdisplay(fh, "\tINFO: operator symbol = %0d", ic_data_out_0[3:1]);
        $fdisplay(fh, "\tINFO: operator symbol = %0d", ic_data_out_0[3:1]);
        $fdisplay(fh, "\tINFO: output channel = %0d", ic_data_out_0[0]);
        $fdisplay(fh, "\tINFO: output channel = %0d", ic_data_out_0[0]);
        //
        //
        $fdisplay(fh, "%0d INFO: ic_data_out_1 = %b", $time, ic_data_out_1);
        $fdisplay(fh, "%0d INFO: ic_data_out_1 = %b", $time, ic_data_out_1);
        $fdisplay(fh, "%0d INFO: ic_data_out_2 = %b", $time, ic_data_out_2);
        $fdisplay(fh, "%0d INFO: ic_data_out_2 = %b", $time, ic_data_out_2);
        $fdisplay(fh, "%0d INFO: ic_data_out_3 = %b\n", $time, ic_data_out_3);
        $fdisplay(fh, "%0d INFO: ic_data_out_3 = %b\n", $time, ic_data_out_3);
 
 
        //$fclose(fh);
        //$fclose(fh);
end
end
 
 
endmodule
endmodule
 
 

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