/*****************************************************************
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/*****************************************************************
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// //
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// //
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// Amber 2 Core Cache Test //
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// Amber 2 Core Cache Test //
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// //
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// //
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// This file is part of the Amber project //
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// This file is part of the Amber project //
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// http://www.opencores.org/project,amber //
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// http://www.opencores.org/project,amber //
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// //
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// //
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// Description //
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// Description //
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// Tests the interaction between a swap instruction //
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// Tests the interaction between a swap instruction //
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// and the cache. //
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// and the cache. //
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// //
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// //
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// Author(s): //
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// Author(s): //
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// - Conor Santifort, csantifort.amber@gmail.com //
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// - Conor Santifort, csantifort.amber@gmail.com //
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// //
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// //
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//////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////
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// //
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// //
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// Copyright (C) 2010 Authors and OPENCORES.ORG //
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// Copyright (C) 2010 Authors and OPENCORES.ORG //
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// //
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// //
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// This source file may be used and distributed without //
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// This source file may be used and distributed without //
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// restriction provided that this copyright statement is not //
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// restriction provided that this copyright statement is not //
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// removed from the file and that any derivative work contains //
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// removed from the file and that any derivative work contains //
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// the original copyright notice and the associated disclaimer. //
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// the original copyright notice and the associated disclaimer. //
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// //
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// //
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// This source file is free software; you can redistribute it //
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// This source file is free software; you can redistribute it //
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// and/or modify it under the terms of the GNU Lesser General //
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// and/or modify it under the terms of the GNU Lesser General //
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// Public License as published by the Free Software Foundation; //
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// Public License as published by the Free Software Foundation; //
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// either version 2.1 of the License, or (at your option) any //
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// either version 2.1 of the License, or (at your option) any //
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// later version. //
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// later version. //
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// //
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// //
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// This source is distributed in the hope that it will be //
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// This source is distributed in the hope that it will be //
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// useful, but WITHOUT ANY WARRANTY; without even the implied //
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// useful, but WITHOUT ANY WARRANTY; without even the implied //
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
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// PURPOSE. See the GNU Lesser General Public License for more //
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// PURPOSE. See the GNU Lesser General Public License for more //
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// details. //
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// details. //
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// //
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// //
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// You should have received a copy of the GNU Lesser General //
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// You should have received a copy of the GNU Lesser General //
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// Public License along with this source; if not, download it //
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// Public License along with this source; if not, download it //
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// from http://www.opencores.org/lgpl.shtml //
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// from http://www.opencores.org/lgpl.shtml //
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// //
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// //
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*****************************************************************/
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*****************************************************************/
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/*
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/*
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Bug is caused by very subtle timing interactions in the Cache
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Bug is caused by very subtle timing interactions in the Cache
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It does not detect a hit, which it should, on the read phase of the swap
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It does not detect a hit, which it should, on the read phase of the swap
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operation. It doesnt detect the hit because it is still completing
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operation. It doesnt detect the hit because it is still completing
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a fill started by the memory request to load an instructuion
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a fill started by the memory request to load an instructuion
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at swap instruction + 8.
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at swap instruction + 8.
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This only occurs when the swap target address is in the cache
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This only occurs when the swap target address is in the cache
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but the cache instruction address is not, and the instruction
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but the cache instruction address is not, and the instruction
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address the third of a group of 4 instruction words.
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address the third of a group of 4 instruction words.
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Test copies sequence to another bit of memory and runs it.
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Test copies sequence to another bit of memory and runs it.
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Repeats this a few times moving the sequence to slightly
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Repeats this a few times moving the sequence to slightly
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different memory locations each time
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different memory locations each time
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*/
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*/
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#include "amber_registers.h"
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#include "amber_registers.h"
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.section .text
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.section .text
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.globl main
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.globl main
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main:
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main:
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@ ------------------------------------------
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@ ------------------------------------------
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@ Copy code
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@ Copy code
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@ ------------------------------------------
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@ ------------------------------------------
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@ Copy code sequence to another area in memory
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@ Copy code sequence to another area in memory
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mov r13, #4
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mov r13, #4
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big_loop:
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big_loop:
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ldr r9, Loc1
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ldr r9, Loc1
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add r9, r9, r13
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add r9, r9, r13
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mov r11, r9
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mov r11, r9
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ldr r8, Adrseq
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ldr r8, Adrseq
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ldr r10, Adrseqend
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ldr r10, Adrseqend
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copy:
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copy:
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ldmia r8!, {r0-r7}
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ldmia r8!, {r0-r7}
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stmia r11!, {r0-r7}
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stmia r11!, {r0-r7}
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cmp r8, r10
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cmp r8, r10
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blt copy
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blt copy
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@ ------------------------------------------
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@ ------------------------------------------
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@ Enable and clear cache
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@ Enable and clear cache
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@ ------------------------------------------
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@ ------------------------------------------
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@ ---------------------
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@ Enable the cache
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@ Enable the cache
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@ ---------------------
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mov r0, #0xffffffff
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mov r0, #0xffffffff
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mcr p15, 0, r0, c3, c0, 0 @ cacheable area
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mcr 15, 0, r0, cr3, cr0, 0 @ cacheable area
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mov r0, #1
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mov r0, #1
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mcr p15, 0, r0, c2, c0, 0 @ cache enable
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mcr 15, 0, r0, cr2, cr0, 0 @ cache enable
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nop
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nop
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nop
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nop
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@ flush the cache
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@ flush the cache
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mcr p15, 0, r0, c1, c0, 0
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mcr 15, 0, r0, cr1, cr0, 0
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nop
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nop
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nop
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nop
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@ jump to special sequence
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@ jump to special sequence
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@ want to return to the instruction immediately after mov pc, r9
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@ want to return to the instruction immediately after mov pc, r9
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mov lr, pc
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mov lr, pc
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mov pc, r9
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mov pc, r9
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return:
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return:
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ldr r3, [r5]
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ldr r3, [r5]
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cmp r3, #0
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cmp r3, #0
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movne r10, #10
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movne r10, #10
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bne testfail
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bne testfail
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cmp r13, #40
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cmp r13, #40
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beq testpass
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beq testpass
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add r13, r13, #4
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add r13, r13, #4
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mov r0, r13
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mov r0, r13
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b big_loop
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b big_loop
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@ ------------------------------------------
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@ ------------------------------------------
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@ ------------------------------------------
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@ ------------------------------------------
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@ puts swap address into cache
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@ puts swap address into cache
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@ move 0x7ff32c0 into r5
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@ move 0x7ff32c0 into r5
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seq: mov r5, #0x000000c0
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seq: mov r5, #0x000000c0
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orr r5, r5, #0x00003200
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orr r5, r5, #0x00003200
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orr r5, r5, #0x00ff0000
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orr r5, r5, #0x00ff0000
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orr r5, r5, #0x07000000
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orr r5, r5, #0x07000000
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ldr r8, [r5]
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ldr r8, [r5]
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mov ip, #0
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mov ip, #0
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mov r2, #1
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mov r2, #1
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str r2, [r5]
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str r2, [r5]
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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@ ------------------------------------------
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@ ------------------------------------------
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@ busybox code
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@ busybox code
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@ ------------------------------------------
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@ ------------------------------------------
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str r2, [r5, #4]
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str r2, [r5, #4]
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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str ip, [r5, #4]
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str ip, [r5, #4]
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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str ip, [r5, #8]
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str ip, [r5, #8]
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swp r3, ip, [r5]
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swp r3, ip, [r5]
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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ldr r3, [r5, #8]
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ldr r3, [r5, #8]
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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mov pc, lr
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mov pc, lr
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nop
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nop
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nop
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nop
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nop
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nop
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seqend: nop
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seqend: nop
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@ ------------------------------------------
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@ ------------------------------------------
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@ ------------------------------------------
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@ ------------------------------------------
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testfail:
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testfail:
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ldr r11, AdrTestStatus
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ldr r11, AdrTestStatus
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str r10, [r11]
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str r10, [r11]
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b testfail
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b testfail
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testpass:
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testpass:
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ldr r11, AdrTestStatus
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ldr r11, AdrTestStatus
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mov r10, #17
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mov r10, #17
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str r10, [r11]
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str r10, [r11]
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b testpass
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b testpass
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Loc1: .word 0x200
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Loc1: .word 0x200
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Adrseq: .word seq
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Adrseq: .word seq
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Adrseqend: .word seqend
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Adrseqend: .word seqend
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/* Write 17 to this address to generate a Test Passed message */
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/* Write 17 to this address to generate a Test Passed message */
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AdrTestStatus: .word ADR_AMBER_TEST_STATUS
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AdrTestStatus: .word ADR_AMBER_TEST_STATUS
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/* ========================================================================= */
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/* ========================================================================= */
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/* ========================================================================= */
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/* ========================================================================= */
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