/*****************************************************************
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/*****************************************************************
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// //
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// //
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// Amber 2 Core Instruction Test //
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// Amber 2 Core Instruction Test //
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// //
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// //
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// This file is part of the Amber project //
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// This file is part of the Amber project //
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// http://www.opencores.org/project,amber //
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// http://www.opencores.org/project,amber //
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// //
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// //
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// Description //
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// Description //
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// Bug with Multiply Accumulate. The flags were gettting set //
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// Bug with Multiply Accumulate. The flags were gettting set //
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// 1 cycle early. So in an operation with ( 0 x n ) + 1, the //
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// 1 cycle early. So in an operation with ( 0 x n ) + 1, the //
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// Z flag was set because it didn't take into account the //
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// Z flag was set because it didn't take into account the //
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// addition done right at the end. //
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// addition done right at the end. //
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// //
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// //
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// Author(s): //
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// Author(s): //
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// - Conor Santifort, csantifort.amber@gmail.com //
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// - Conor Santifort, csantifort.amber@gmail.com //
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// //
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// //
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//////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////
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// //
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// //
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// Copyright (C) 2010 Authors and OPENCORES.ORG //
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// Copyright (C) 2010 Authors and OPENCORES.ORG //
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// //
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// //
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// This source file may be used and distributed without //
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// This source file may be used and distributed without //
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// restriction provided that this copyright statement is not //
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// restriction provided that this copyright statement is not //
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// removed from the file and that any derivative work contains //
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// removed from the file and that any derivative work contains //
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// the original copyright notice and the associated disclaimer. //
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// the original copyright notice and the associated disclaimer. //
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// //
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// //
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// This source file is free software; you can redistribute it //
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// This source file is free software; you can redistribute it //
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// and/or modify it under the terms of the GNU Lesser General //
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// and/or modify it under the terms of the GNU Lesser General //
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// Public License as published by the Free Software Foundation; //
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// Public License as published by the Free Software Foundation; //
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// either version 2.1 of the License, or (at your option) any //
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// either version 2.1 of the License, or (at your option) any //
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// later version. //
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// later version. //
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// //
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// //
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// This source is distributed in the hope that it will be //
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// This source is distributed in the hope that it will be //
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// useful, but WITHOUT ANY WARRANTY; without even the implied //
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// useful, but WITHOUT ANY WARRANTY; without even the implied //
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
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// PURPOSE. See the GNU Lesser General Public License for more //
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// PURPOSE. See the GNU Lesser General Public License for more //
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// details. //
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// details. //
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// //
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// //
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// You should have received a copy of the GNU Lesser General //
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// You should have received a copy of the GNU Lesser General //
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// Public License along with this source; if not, download it //
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// Public License along with this source; if not, download it //
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// from http://www.opencores.org/lgpl.shtml //
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// from http://www.opencores.org/lgpl.shtml //
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// //
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// //
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*****************************************************************/
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*****************************************************************/
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#include "amber_registers.h"
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#include "amber_registers.h"
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.section .text
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.section .text
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.globl main
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.globl main
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main:
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main:
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@ r6 = mode
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@ r6 = mode
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@ r3 = inode->i_mode
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@ r3 = inode->i_mode
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@ setup
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@ setup
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mov r0, #0
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mov r0, #0
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mov r1, #4
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mov r1, #4
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mov sp, #StackArea
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@ -------------------------------------
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@ -------------------------------------
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@ Replicated code from Linux Kernel
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@ Replicated code from Linux Kernel
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@ chip.c / set_irq_chip
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@ chip.c / set_irq_chip
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stmda sp,{r4, r5, r6, lr}
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stmda sp,{r4, r5, r6, lr}
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ldr r3, [pc, #120] @ 2e53ac
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ldr r3, [pc, #120] @ 2e53ac
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ldr r3, [r3]
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ldr r3, [r3]
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cmp r0, r3
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cmp r0, r3
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mov r5, r1
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mov r5, r1
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bcs j1
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bcs j1
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ldr r2, [pc, #104] @ 2e53b0
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ldr r2, [pc, #104] @ 2e53b0
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mov r3, #60 @ 0x3c
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mov r3, #60 @ 0x3c
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mlas r6, r0, r3, r2 @ if result == 0 -> warn_slowpath
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mlas r6, r0, r3, r2 @ if result == 0 -> warn_slowpath
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bne j2
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bne j2
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j1:
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j1:
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mov r3, r0
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mov r3, r0
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mov r1, #95 @ 0x5f
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mov r1, #95 @ 0x5f
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ldr r0, [pc, #84] @ 2e53b4
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ldr r0, [pc, #84] @ 2e53b4
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ldr r2, [pc, #84] @ 2e53b8
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ldr r2, [pc, #84] @ 2e53b8
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bl warn_slowpath
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bl warn_slowpath
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mvn r0, #21 @ 0x15
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mvn r0, #21 @ 0x15
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ldmib sp, {r4, r5, r6, pc}
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ldmib sp, {r4, r5, r6, pc}
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j2:
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j2:
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ldr r3, [pc, #72] @ 2e53bc
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ldr r3, [pc, #72] @ 2e53bc
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cmp r1, #0 @ 0x0
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cmp r1, #0 @ 0x0
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moveq r5, r3
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moveq r5, r3
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mov r4, pc
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mov r4, pc
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orr r3, r4, #128 @ 0x80
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orr r3, r4, #128 @ 0x80
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teqp pc, r3
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teqp pc, r3
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mov r0, r5
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mov r0, r5
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bl irq_chip_set_defaults
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bl irq_chip_set_defaults
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ands r0, r4, #128 @ 0x80
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ands r0, r4, #128 @ 0x80
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str r5, [r6, #8]
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str r5, [r6, #8]
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beq j3
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beq j3
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teqp pc, r4
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teqp pc, r4
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mov r0, #0 @ 0x0
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mov r0, #0 @ 0x0
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ldmib sp, {r4, r5, r6, pc}
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ldmib sp, {r4, r5, r6, pc}
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j3:
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j3:
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teqp pc, r4
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teqp pc, r4
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ldmib sp, {r4, r5, r6, pc}
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ldmib sp, {r4, r5, r6, pc}
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.word nr_irqs
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.word nr_irqs
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.word 0xc04c6ce4
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.word 0xc04c6ce4
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.word 0xc0482c14
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.word 0xc0482c14
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.word 0xc0482c28
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.word 0xc0482c28
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.word 0xc04c77e8
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.word 0xc04c77e8
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nr_irqs:
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nr_irqs:
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.word 47
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.word 47
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b testpass
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b testpass
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@ -------------------------------------
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@ -------------------------------------
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warn_slowpath:
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warn_slowpath:
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mov r10, #20
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mov r10, #20
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b testfail
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b testfail
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irq_chip_set_defaults:
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irq_chip_set_defaults:
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b testpass
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b testpass
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testfail:
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testfail:
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ldr r11, AdrTestStatus
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ldr r11, AdrTestStatus
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str r10, [r11]
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str r10, [r11]
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b testfail
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b testfail
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testpass:
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testpass:
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ldr r11, AdrTestStatus
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ldr r11, AdrTestStatus
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mov r10, #17
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mov r10, #17
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str r10, [r11]
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str r10, [r11]
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b testpass
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b testpass
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/* Write 17 to this address to generate a Test Passed message */
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/* Write 17 to this address to generate a Test Passed message */
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AdrTestStatus: .word ADR_AMBER_TEST_STATUS
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AdrTestStatus: .word ADR_AMBER_TEST_STATUS
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.word 0
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.word 0
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.word 0
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.word 0
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StackArea:
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