*** Steps to create the Spartan-6 DDR3 memory interface for the SP605 development board.
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*** Steps to create the Spartan-6 DDR3 memory interface for the SP605 development board.
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These instructions are based on using Xilinx ISE 11.5
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These instructions are based on using Xilinx ISE 11.5
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Use Coregen/MIG 3.3 to create the controller.
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Use Coregen/MIG 3.3 to create the controller.
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- Component Name: ddr3
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- Component Name: ddr3
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- Bank 3 Memory Type DDR3 SDRAM
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- Bank 3 Memory Type DDR3 SDRAM
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- Frequency: 400MHz
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- Frequency: 400MHz
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- Memory Part: MT41J64M16XX-187E
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- Memory Part: MT41J64M16XX-187E
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- Configuration Selection: One 128-bit bi-directional port
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- Configuration Selection: One 128-bit bi-directional port
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- Memory Address Mapping Selection: Row, Bank, Column
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- Memory Address Mapping Selection: Row, Bank, Column
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Once the controller is generated copy all the Verilog files from the user_design/rtl directory to $AMBER_BASE/hw/vlog/xs6_ddr3.
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Once the controller is generated copy all the Verilog files from the user_design/rtl directory to $AMBER_BASE/hw/vlog/xs6_ddr3.
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Then make the following modifications
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Then make the following modifications
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1. ddr3.v
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1. ddr3.v
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Rename this module to mcb_ddr3.v.
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Rename this module to mcb_ddr3.v.
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Replace the inputs c3_sys_clk_p, c3_sys_clk_n with sys_clk_ibufg.
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Replace the inputs c3_sys_clk_p, c3_sys_clk_n with sys_clk_ibufg.
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Delete the outputs c3_clk0 and c3_rst0.
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Delete the outputs c3_clk0 and c3_rst0.
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2. memc3_infrastructure.v
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2. memc3_infrastructure.v
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Replace the inputs c3_sys_clk_p, c3_sys_clk_n with sys_clk_ibufg.
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Replace the inputs sys_clk_p, sys_clk_n with sys_clk_ibufg.
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Delete the outputs c3_clk0 and c3_rst0.
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Delete the outputs clk0 and rst0.
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Delete the line with (* KEEP = "TRUE" *) wire sys_clk_ibufg;
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Change the localparam from
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Change the localparam from
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localparam CLK_PERIOD_NS = C_MEMCLK_PERIOD / 1000.0;
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localparam CLK_PERIOD_NS = C_MEMCLK_PERIOD / 1000.0;
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to
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to
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localparam CLK_PERIOD_NS = C_MEMCLK_PERIOD / 500.0;
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localparam CLK_PERIOD_NS = C_MEMCLK_PERIOD / 500.0;
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Delete the generate statement from lines 124 to 154
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Delete the generate statement from lines 124 to 154
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On the PLL_ADV instantiation,
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On the PLL_ADV instantiation,
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Change the parameter CLKFBOUT_MULT from 2 to 4.
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Change the parameter CLKFBOUT_MULT from 2 to 4.
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Disconnect the CLKOUT2 output
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Disconnect the CLKOUT2 output
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Delete the U_BUFG_CLK0 instantiation.
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Delete the U_BUFG_CLK0 instantiation.
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Delete the rst0_sync_r logic.
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Delete the rst0_sync_r logic.
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