URL
https://opencores.org/ocsvn/an-fpga-implementation-of-low-latency-noc-based-mpsoc/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk
Go to most recent revision |
Only display areas with differences |
Details |
Blame |
View Log
Rev 25 |
Rev 28 |
All notable changes to this project will be documented in this file.
|
All notable changes to this project will be documented in this file.
|
|
|
|
|
|
##[1.5.1] - 3-2-2017
|
|
## changed
|
|
- src_c/jtag_main.c: variable length memory support is added.
|
|
- NoC emulator: Jtag tabs are reduced to total of 3. A 64 core 2-VC NoC emulation is sucessfully tested on DE4 FPGA board.
|
|
-ssa: Now can work with fully adaptive routing.
|
|
|
|
|
##[1.5.0] - 13-10-2016
|
##[1.5.0] - 13-10-2016
|
### Added
|
### Added
|
- static straight allocator (SSA) which accelerates packets traversing to the same direction to the NoC router.
|
- static straight allocator (SSA) which accelerates packets traversing to the same direction to the NoC router.
|
- NoC emulator.
|
- NoC emulator.
|
- Altor processor.
|
- Altor processor.
|
- Jtag_wb: allow access to the wishbone bus slave ports via Jtag.
|
- Jtag_wb: allow access to the wishbone bus slave ports via Jtag.
|
- Jtag_main: A C code which allows host PC to have access to the jtag_wb.
|
- Jtag_main: A C code which allows host PC to have access to the jtag_wb.
|
|
|
|
|
## changed
|
## changed
|
- Memory IP cores are categorized into two IPs: Single and double port.
|
- Memory IP cores are categorized into two IPs: Single and double port.
|
- The access via jtag_wb or Altera In-System Memory Content Editor is added as optional via parameter setting for single port memory.
|
- The access via jtag_wb or Altera In-System Memory Content Editor is added as optional via parameter setting for single port memory.
|
|
|
|
|
|
|
##[1.0.0] - 27-1-2016
|
##[1.0.0] - 27-1-2016
|
### added
|
### added
|
- ProNoC: new version with GUI generator
|
- ProNoC: new version with GUI generator
|
- Interface generator
|
- Interface generator
|
- IP generator
|
- IP generator
|
- Processing tile generator
|
- Processing tile generator
|
- NoC based MCSoC generator
|
- NoC based MCSoC generator
|
|
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.