All notable changes to this project will be documented in this file.
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All notable changes to this project will be documented in this file.
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##[1.8.0] - 16-5-2018
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## Added
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- Support hard-built QoS/EoS support in NoC using weighted Round-Robin arbiter
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- Add real application task grah simulation support in NoC simulator
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- add new
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- Add two new (OpenRISC) softprocessors: Or1200 & Mor1kx
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- Add documention for timer, ni-master, ni-slave, memory, and dma IP cores.
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- Add User manual file
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- Add USB blaster II suooprt in JTAG controller
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- Add GUI for adding new Altera FPGA boards.
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- The simulator/ emulator now can provide additional smulation results
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(a) Average latency per average desired flit injection ratio
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(b) Average throughput per average desired flit injection ratio
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(c) send/received packets number for each router at different injection ratios
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(d) send/received worst-case delay for each router at different injection ratios
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(e) Simulation execution clock cycles
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## changed
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- Fixe the bug in NoC that halts the simulation when B is defined as 2.
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- Support Burst Type Extension for Incrementing and Decrementing bursts in RAM controller
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##[1.7.0] - 15-7-2017
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##[1.7.0] - 15-7-2017
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## Added
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## Added
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- Software compilation text-editor
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- Software compilation text-editor
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- Processing tile Diagrame Viewer
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- Processing tile Diagrame Viewer
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- Modelsim/Verilator/QuartusII GUI compilation assist
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- Modelsim/Verilator/QuartusII GUI compilation assist
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- Multi-channel DMA
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- Multi-channel DMA
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## changed
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## changed
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- New multi-channel DMA-based NI
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- New multi-channel DMA-based NI
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##[1.6.0] - 6-3-2017
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##[1.6.0] - 6-3-2017
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## Added
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## Added
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- NoC GUI simulator (using Verilator)
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- NoC GUI simulator (using Verilator)
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##[1.5.2] - 22-2-2017
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##[1.5.2] - 22-2-2017
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## changed
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## changed
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- fixed bug in wishbone bus
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- fixed bug in wishbone bus
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##[1.5.1] - 3-2-2017
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##[1.5.1] - 3-2-2017
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## changed
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## changed
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- src_c/jtag_main.c: variable length memory support is added.
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- src_c/jtag_main.c: variable length memory support is added.
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- NoC emulator: Jtag tabs are reduced to total of 3. A 64 core 2-VC NoC emulation is sucessfully tested on DE4 FPGA board.
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- NoC emulator: Jtag tabs are reduced to total of 3. A 64 core 2-VC NoC emulation is sucessfully tested on DE4 FPGA board.
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- ssa: Now can work with fully adaptive routing.
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- ssa: Now can work with fully adaptive routing.
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##[1.5.0] - 13-10-2016
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##[1.5.0] - 13-10-2016
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### Added
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### Added
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- static straight allocator (SSA) which accelerates packets traversing to the same direction to the NoC router.
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- static straight allocator (SSA) which accelerates packets traversing to the same direction to the NoC router.
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- NoC emulator.
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- NoC emulator.
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- Altor processor.
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- Altor processor.
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- Jtag_wb: allow access to the wishbone bus slave ports via Jtag.
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- Jtag_wb: allow access to the wishbone bus slave ports via Jtag.
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- Jtag_main: A C code which allows host PC to have access to the jtag_wb.
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- Jtag_main: A C code which allows host PC to have access to the jtag_wb.
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## changed
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## changed
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- Memory IP cores are categorized into two IPs: Single and double port.
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- Memory IP cores are categorized into two IPs: Single and double port.
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- The access via jtag_wb or Altera In-System Memory Content Editor is added as optional via parameter setting for single port memory.
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- The access via jtag_wb or Altera In-System Memory Content Editor is added as optional via parameter setting for single port memory.
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##[1.0.0] - 27-1-2016
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##[1.0.0] - 27-1-2016
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### added
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### added
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- ProNoC: new version with GUI generator
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- ProNoC: new version with GUI generator
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- Interface generator
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- Interface generator
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- IP generator
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- IP generator
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- Processing tile generator
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- Processing tile generator
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- NoC based MCSoC generator
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- NoC based MCSoC generator
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