/**************************************
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/**************************************
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* Module: emulator
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* Module: emulator
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* Date:2017-01-20
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* Date:2017-01-20
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* Author: alireza
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* Author: alireza
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*
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*
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* Description:
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* Description:
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***************************************/
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***************************************/
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module noc_emulator
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module noc_emulator
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import pronoc_pkg::*;
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import pronoc_pkg::*;
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#(
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#(
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// simulation
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// simulation
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parameter PATTERN_VJTAG_INDEX=125,
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parameter PATTERN_VJTAG_INDEX=125,
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parameter STATISTIC_VJTAG_INDEX=124
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parameter STATISTIC_VJTAG_INDEX=124
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)(
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)(
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jtag_ctrl_reset,
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jtag_ctrl_reset,
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start_o,
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start_o,
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reset,
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reset,
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clk,
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clk,
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done
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done
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);
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);
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parameter MAX_RATIO = 100;
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parameter MAX_RATIO = 100;
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parameter RAM_Aw=7;
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parameter RAM_Aw=7;
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parameter STATISTIC_NUM=8;
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parameter STATISTIC_NUM=8;
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input reset,jtag_ctrl_reset,clk;
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input reset,jtag_ctrl_reset,clk;
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output done;
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output done;
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output start_o;
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output start_o;
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localparam
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localparam
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PCK_CNTw =30, // 1 G packets
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PCK_CNTw =30, // 1 G packets
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PCK_SIZw =14, // 16 K flit
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PCK_SIZw =14, // 16 K flit
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MAX_EAw =8,
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MAX_EAw =8,
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MAX_Cw =4; // 16 message classes
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MAX_Cw =4; // 16 message classes
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//localparam MAX_SIM_CLKs = 1_000_000_000;
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//localparam MAX_SIM_CLKs = 1_000_000_000;
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reg start_i;
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reg start_i;
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reg [10:0] cnt;
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reg [10:0] cnt;
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assign start_o=start_i;
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assign start_o=start_i;
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//noc connection channels
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//noc connection channels
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smartflit_chanel_t chan_in_all [NE-1 : 0];
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smartflit_chanel_t chan_in_all [NE-1 : 0];
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smartflit_chanel_t chan_out_all [NE-1 : 0];
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smartflit_chanel_t chan_out_all [NE-1 : 0];
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noc_top the_top(
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noc_top the_top(
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.reset(reset),
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.reset(reset),
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.clk(clk),
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.clk(clk),
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.chan_in_all(chan_in_all),
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.chan_in_all(chan_in_all),
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.chan_out_all(chan_out_all)
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.chan_out_all(chan_out_all),
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.router_event()
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);
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);
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Jtag_traffic_gen #(
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Jtag_traffic_gen #(
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.PATTERN_VJTAG_INDEX(PATTERN_VJTAG_INDEX),
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.PATTERN_VJTAG_INDEX(PATTERN_VJTAG_INDEX),
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.STATISTIC_VJTAG_INDEX(STATISTIC_VJTAG_INDEX),
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.STATISTIC_VJTAG_INDEX(STATISTIC_VJTAG_INDEX),
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.MAX_RATIO(MAX_RATIO),
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.MAX_RATIO(MAX_RATIO),
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.RAM_Aw(RAM_Aw),
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.RAM_Aw(RAM_Aw),
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.STATISTIC_NUM(STATISTIC_NUM), // the last 8 rows of RAM is reserved for collecting statistic values;
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.STATISTIC_NUM(STATISTIC_NUM), // the last 8 rows of RAM is reserved for collecting statistic values;
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.PCK_CNTw(PCK_CNTw), // 1 G packets
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.PCK_CNTw(PCK_CNTw), // 1 G packets
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.PCK_SIZw(PCK_SIZw), // 16 K flit
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.PCK_SIZw(PCK_SIZw), // 16 K flit
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.MAX_EAw(MAX_EAw), // 16 nodes in x dimension
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.MAX_EAw(MAX_EAw), // 16 nodes in x dimension
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.MAX_Cw(MAX_Cw) // 16 message class
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.MAX_Cw(MAX_Cw) // 16 message class
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)
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)
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the_traffic_gen
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the_traffic_gen
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(
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(
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.start_i(start_i),
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.start_i(start_i),
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.jtag_ctrl_reset(jtag_ctrl_reset),
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.jtag_ctrl_reset(jtag_ctrl_reset),
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.reset(reset),
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.reset(reset),
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.clk(clk),
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.clk(clk),
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.done(done),
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.done(done),
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//noc
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//noc
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.chan_in_all(chan_out_all),
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.chan_in_all(chan_out_all),
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.chan_out_all(chan_in_all)
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.chan_out_all(chan_in_all)
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);
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);
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always @(posedge clk or posedge reset) begin
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always @(posedge clk or posedge reset) begin
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if(reset) begin
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if(reset) begin
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cnt <=0;
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cnt <=0;
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start_i <=0;
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start_i <=0;
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end else begin
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end else begin
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if(cnt < 1020) cnt<= cnt+1'b1;
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if(cnt < 1020) cnt<= cnt+1'b1;
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if(cnt== 1000)begin
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if(cnt== 1000)begin
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start_i<=1'b1;
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start_i<=1'b1;
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end else if(cnt== 1010)begin
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end else if(cnt== 1010)begin
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start_i<=1'b0;
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start_i<=1'b0;
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end
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end
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end
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end
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end
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end
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endmodule
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endmodule
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/***************
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/***************
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Jtag_traffic_gen:
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Jtag_traffic_gen:
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A traffic generator which can be programed using JTAG port
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A traffic generator which can be programed using JTAG port
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****************/
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****************/
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module Jtag_traffic_gen
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module Jtag_traffic_gen
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import pronoc_pkg::*;
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import pronoc_pkg::*;
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#(
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#(
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parameter PATTERN_VJTAG_INDEX=125,
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parameter PATTERN_VJTAG_INDEX=125,
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parameter STATISTIC_VJTAG_INDEX=124,
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parameter STATISTIC_VJTAG_INDEX=124,
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parameter RAM_Aw=7,
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parameter RAM_Aw=7,
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parameter STATISTIC_NUM=8,
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parameter STATISTIC_NUM=8,
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parameter MAX_RATIO = 100,
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parameter MAX_RATIO = 100,
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parameter PCK_CNTw =30, // 1 G packets
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parameter PCK_CNTw =30, // 1 G packets
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parameter PCK_SIZw =14, // 16 K flit
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parameter PCK_SIZw =14, // 16 K flit
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parameter MAX_EAw =8,
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parameter MAX_EAw =8,
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parameter MAX_Cw =4 // 16 message class
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parameter MAX_Cw =4 // 16 message class
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)
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)
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(
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(
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chan_in_all,
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chan_in_all,
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chan_out_all,
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chan_out_all,
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done,
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done,
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start_i,
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start_i,
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jtag_ctrl_reset,
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jtag_ctrl_reset,
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reset,
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reset,
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clk
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clk
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);
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);
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input reset,jtag_ctrl_reset, clk;
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input reset,jtag_ctrl_reset, clk;
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input start_i;
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input start_i;
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output done;
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output done;
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// NOC interfaces
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// NOC interfaces
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input smartflit_chanel_t chan_in_all [NE-1 : 0];
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input smartflit_chanel_t chan_in_all [NE-1 : 0];
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output smartflit_chanel_t chan_out_all [NE-1 : 0];
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output smartflit_chanel_t chan_out_all [NE-1 : 0];
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wire [NE-1 : 0] start;
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wire [NE-1 : 0] start;
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wire [NE-1 : 0] done_sep;
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wire [NE-1 : 0] done_sep;
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assign done = &done_sep;
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assign done = &done_sep;
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start_delay_gen #(
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start_delay_gen #(
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.NC(NE) //number of cores
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.NC(NE) //number of cores
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)
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)
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st_gen
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st_gen
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(
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(
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.clk(clk),
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.clk(clk),
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.reset(reset),
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.reset(reset),
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.start_i(start_i),
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.start_i(start_i),
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.start_o(start)
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.start_o(start)
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);
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);
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//jtag pattern controller
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//jtag pattern controller
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localparam
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localparam
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NEw=$clog2(NE),
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NEw=$clog2(NE),
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Dw=64,
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Dw=64,
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Aw =RAM_Aw;
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Aw =RAM_Aw;
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wire [Dw-1 : 0] jtag_data ;
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wire [Dw-1 : 0] jtag_data ;
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wire [Aw-1 : 0] jtag_addr ;
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wire [Aw-1 : 0] jtag_addr ;
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wire jtag_we;
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wire jtag_we;
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wire [Dw-1 : 0] jtag_q ;
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wire [Dw-1 : 0] jtag_q ;
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wire [NEw-1: 0] jtag_RAM_select;
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wire [NEw-1: 0] jtag_RAM_select;
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wire [NE-1 : 0] jtag_we_sep;
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wire [NE-1 : 0] jtag_we_sep;
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wire [Dw-1 : 0] jtag_q_sep [NE-1 : 0];
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wire [Dw-1 : 0] jtag_q_sep [NE-1 : 0];
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assign jtag_q = jtag_q_sep[jtag_RAM_select];
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assign jtag_q = jtag_q_sep[jtag_RAM_select];
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jtag_emulator_controller #(
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jtag_emulator_controller #(
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.VJTAG_INDEX(PATTERN_VJTAG_INDEX),
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.VJTAG_INDEX(PATTERN_VJTAG_INDEX),
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.Dw(Dw),
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.Dw(Dw),
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.Aw(Aw+NEw)
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.Aw(Aw+NEw)
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)
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)
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pttern_jtag_controller
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pttern_jtag_controller
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(
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(
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.dat_o(jtag_data),
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.dat_o(jtag_data),
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.addr_o({jtag_RAM_select,jtag_addr}),
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.addr_o({jtag_RAM_select,jtag_addr}),
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.we_o(jtag_we),
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.we_o(jtag_we),
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.q_i(jtag_q),
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.q_i(jtag_q),
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.clk(clk),
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.clk(clk),
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.reset(jtag_ctrl_reset)
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.reset(jtag_ctrl_reset)
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);
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);
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//jtag statistic reader
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//jtag statistic reader
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localparam
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localparam
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STATISw=log2(STATISTIC_NUM);
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STATISw=log2(STATISTIC_NUM);
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wire [STATISw-1 : 0] statis_jtag_addr ;
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wire [STATISw-1 : 0] statis_jtag_addr ;
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wire [Dw-1 : 0] statis_jtag_data_i;
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wire [Dw-1 : 0] statis_jtag_data_i;
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wire [NEw-1: 0] statis_jtag_select;
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wire [NEw-1: 0] statis_jtag_select;
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wire [Dw-1 : 0] statis_jtag_q_sep [NE-1 : 0];
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wire [Dw-1 : 0] statis_jtag_q_sep [NE-1 : 0];
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assign statis_jtag_data_i = statis_jtag_q_sep[statis_jtag_select];
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assign statis_jtag_data_i = statis_jtag_q_sep[statis_jtag_select];
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jtag_emulator_controller #(
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jtag_emulator_controller #(
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.VJTAG_INDEX(STATISTIC_VJTAG_INDEX),
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.VJTAG_INDEX(STATISTIC_VJTAG_INDEX),
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.Dw(Dw),
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.Dw(Dw),
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.Aw(STATISw+NEw)
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.Aw(STATISw+NEw)
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|
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)
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)
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jtag_statistic_reader
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jtag_statistic_reader
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(
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(
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.dat_o(),
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.dat_o(),
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.addr_o({statis_jtag_select,statis_jtag_addr}),
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.addr_o({statis_jtag_select,statis_jtag_addr}),
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.we_o( ),
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.we_o( ),
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.q_i(statis_jtag_data_i),
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.q_i(statis_jtag_data_i),
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.clk(clk),
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.clk(clk),
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.reset(jtag_ctrl_reset)
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.reset(jtag_ctrl_reset)
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);
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);
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function integer addrencode;
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function integer addrencode;
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input integer pos,k,n,kw;
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input integer pos,k,n,kw;
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integer pow,i,tmp;begin
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integer pow,i,tmp;begin
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addrencode=0;
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addrencode=0;
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pow=1;
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pow=1;
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for (i = 0; i
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for (i = 0; i
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tmp=(pos/pow);
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tmp=(pos/pow);
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tmp=tmp%k;
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tmp=tmp%k;
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tmp=tmp<
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tmp=tmp<
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addrencode=addrencode | tmp;
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addrencode=addrencode | tmp;
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pow=pow * k;
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pow=pow * k;
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end
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end
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end
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end
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endfunction
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endfunction
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genvar i;
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genvar i;
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generate
|
generate
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for (i=0; i
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for (i=0; i
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wire [EAw-1 : 0] current_e_addr [NE-1 : 0];
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wire [EAw-1 : 0] current_e_addr [NE-1 : 0];
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endp_addr_encoder #(
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endp_addr_encoder #(
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.TOPOLOGY(TOPOLOGY),
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.TOPOLOGY(TOPOLOGY),
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.T1(T1),
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.T1(T1),
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.T2(T2),
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.T2(T2),
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.T3(T3),
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.T3(T3),
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.EAw(EAw),
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.EAw(EAw),
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.NE(NE)
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.NE(NE)
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)
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)
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encoder
|
encoder
|
(
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(
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.id(i[NEw-1 : 0]),
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.id(i[NEw-1 : 0]),
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.code(current_e_addr[i])
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.code(current_e_addr[i])
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);
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);
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// seperate interfaces per router
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// seperate interfaces per router
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assign jtag_we_sep[i] = (jtag_RAM_select == i) ? jtag_we :1'b0;
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assign jtag_we_sep[i] = (jtag_RAM_select == i) ? jtag_we :1'b0;
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|
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traffic_gen_ram #(
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traffic_gen_ram #(
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.RAM_Aw(RAM_Aw),
|
.RAM_Aw(RAM_Aw),
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.STATISTIC_NUM(STATISTIC_NUM),
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.STATISTIC_NUM(STATISTIC_NUM),
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.MAX_RATIO(MAX_RATIO),
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.MAX_RATIO(MAX_RATIO),
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.PCK_CNTw(PCK_CNTw), // 1 G packets
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.PCK_CNTw(PCK_CNTw), // 1 G packets
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.PCK_SIZw(PCK_SIZw), // 16 K flit
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.PCK_SIZw(PCK_SIZw), // 16 K flit
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.MAX_EAw(MAX_EAw),
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.MAX_EAw(MAX_EAw),
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.MAX_Cw(MAX_Cw) // 16 message cla
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.MAX_Cw(MAX_Cw) // 16 message cla
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)
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)
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traffic_gen_ram_inst
|
traffic_gen_ram_inst
|
(
|
(
|
.reset(reset),
|
.reset(reset),
|
.clk(clk),
|
.clk(clk),
|
.current_r_addr(chan_in_all[i].ctrl_chanel.neighbors_r_addr),
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.current_r_addr(chan_in_all[i].ctrl_chanel.neighbors_r_addr),
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.current_e_addr(current_e_addr[i]),
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.current_e_addr(current_e_addr[i]),
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.start(start[i]),
|
.start(start[i]),
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.done(done_sep[i]),
|
.done(done_sep[i]),
|
//pattern updater
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//pattern updater
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.jtag_data_b(jtag_data),
|
.jtag_data_b(jtag_data),
|
.jtag_addr_b(jtag_addr),
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.jtag_addr_b(jtag_addr),
|
.jtag_we_b( jtag_we_sep[i]),
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.jtag_we_b( jtag_we_sep[i]),
|
.jtag_q_b( jtag_q_sep[i]),
|
.jtag_q_b( jtag_q_sep[i]),
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//statistic reader
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//statistic reader
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.statistic_jtag_addr_b(statis_jtag_addr),
|
.statistic_jtag_addr_b(statis_jtag_addr),
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.statistic_jtag_q_b( statis_jtag_q_sep[i]),
|
.statistic_jtag_q_b( statis_jtag_q_sep[i]),
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//noc interface
|
//noc interface
|
.chan_in (chan_in_all[i]),
|
.chan_in (chan_in_all[i]),
|
.chan_out(chan_out_all[i])
|
.chan_out(chan_out_all[i])
|
|
|
);
|
);
|
end
|
end
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endgenerate
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endgenerate
|
|
|
endmodule
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endmodule
|
|
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|
|
|
/********************
|
/********************
|
*
|
*
|
* traffic_gen_ram
|
* traffic_gen_ram
|
*
|
*
|
*********************/
|
*********************/
|
|
|
module traffic_gen_ram
|
module traffic_gen_ram
|
import pronoc_pkg::*;
|
import pronoc_pkg::*;
|
#(
|
#(
|
parameter RAM_Aw=7,
|
parameter RAM_Aw=7,
|
parameter STATISTIC_NUM=8, // the last 8 rows of RAM is reserved for collecting statistic values;
|
parameter STATISTIC_NUM=8, // the last 8 rows of RAM is reserved for collecting statistic values;
|
parameter MAX_RATIO=100,
|
parameter MAX_RATIO=100,
|
parameter PCK_CNTw =30, // 1 G packets
|
parameter PCK_CNTw =30, // 1 G packets
|
parameter PCK_SIZw =14, // 16 K flit
|
parameter PCK_SIZw =14, // 16 K flit
|
parameter MAX_EAw =8,
|
parameter MAX_EAw =8,
|
parameter MAX_Cw =4 // 16 message class
|
parameter MAX_Cw =4 // 16 message class
|
|
|
)
|
)
|
(
|
(
|
|
|
done,
|
done,
|
current_r_addr,
|
current_r_addr,
|
current_e_addr,
|
current_e_addr,
|
start,
|
start,
|
|
|
//noc port
|
//noc port
|
chan_in,
|
chan_in,
|
chan_out,
|
chan_out,
|
|
|
//Pattern RAM to jtag interface
|
//Pattern RAM to jtag interface
|
jtag_data_b,
|
jtag_data_b,
|
jtag_addr_b,
|
jtag_addr_b,
|
jtag_we_b,
|
jtag_we_b,
|
jtag_q_b,
|
jtag_q_b,
|
|
|
// Statistic to jtag interface
|
// Statistic to jtag interface
|
statistic_jtag_addr_b,
|
statistic_jtag_addr_b,
|
statistic_jtag_q_b,
|
statistic_jtag_q_b,
|
|
|
reset,
|
reset,
|
clk
|
clk
|
);
|
);
|
|
|
|
|
function integer log2;
|
function integer log2;
|
input integer number; begin
|
input integer number; begin
|
log2=0;
|
log2=0;
|
while(2**log2
|
while(2**log2
|
log2=log2+1;
|
log2=log2+1;
|
end
|
end
|
end
|
end
|
endfunction // log2
|
endfunction // log2
|
|
|
|
|
// localparam MAX_PATTERN = (2**RAM_Aw)-1; // support up to MAX_PATTERN different injections pattern
|
// localparam MAX_PATTERN = (2**RAM_Aw)-1; // support up to MAX_PATTERN different injections pattern
|
|
|
|
|
|
|
|
|
//define maximum width for each parameter of packet injector
|
//define maximum width for each parameter of packet injector
|
|
|
localparam RATIOw =7; // log2(100)
|
localparam RATIOw =7; // log2(100)
|
|
|
localparam Dw=PCK_CNTw+ RATIOw + PCK_SIZw + MAX_EAw + MAX_Cw +1;//=64
|
localparam Dw=PCK_CNTw+ RATIOw + PCK_SIZw + MAX_EAw + MAX_Cw +1;//=64
|
localparam Aw=RAM_Aw;
|
localparam Aw=RAM_Aw;
|
localparam STATISw=log2(STATISTIC_NUM);
|
localparam STATISw=log2(STATISTIC_NUM);
|
|
|
localparam
|
localparam
|
STATE_NUM=5,
|
STATE_NUM=5,
|
IDEAL =1,
|
IDEAL =1,
|
WAIT1 = 2,
|
WAIT1 = 2,
|
WAIT2 = 4,
|
WAIT2 = 4,
|
SEND_PCK=8,
|
SEND_PCK=8,
|
/*
|
/*
|
SAVE_SENT_PCK_NUM=4,
|
SAVE_SENT_PCK_NUM=4,
|
SAVE_RSVD_PCK_NUM=8,
|
SAVE_RSVD_PCK_NUM=8,
|
SAVE_TOTAL_LATENCY_NUM=16,
|
SAVE_TOTAL_LATENCY_NUM=16,
|
SAVE_WORST_LATENCY_NUM=32,
|
SAVE_WORST_LATENCY_NUM=32,
|
*/
|
*/
|
ASSET_DONE=16;
|
ASSET_DONE=16;
|
|
|
localparam
|
localparam
|
CLK_CNTw = log2(MAX_SIM_CLKs+1),
|
CLK_CNTw = log2(MAX_SIM_CLKs+1),
|
MAX_PCK_NUM = (2**PCK_CNTw)-1,
|
MAX_PCK_NUM = (2**PCK_CNTw)-1,
|
MAX_PCK_SIZ = (2**PCK_SIZw)-1; // max packet size
|
MAX_PCK_SIZ = (2**PCK_SIZw)-1; // max packet size
|
|
|
localparam [Aw-1 : 0]
|
localparam [Aw-1 : 0]
|
RAM_CNT_ADDR = 0,
|
RAM_CNT_ADDR = 0,
|
PATTERN_START_ADDR=1,
|
PATTERN_START_ADDR=1,
|
// PATTERN_END_ADDR= MAX_PATTERN,
|
// PATTERN_END_ADDR= MAX_PATTERN,
|
SENT_PCK_ADDR = 0,
|
SENT_PCK_ADDR = 0,
|
RSVD_PCK_ADDR = 1,
|
RSVD_PCK_ADDR = 1,
|
TOTAL_LATENCY_ADDR = 2,
|
TOTAL_LATENCY_ADDR = 2,
|
WORST_LATENCY_ADDR = 3;
|
WORST_LATENCY_ADDR = 3;
|
|
|
|
|
input reset, clk;
|
input reset, clk;
|
// the connected router address
|
// the connected router address
|
input [RAw-1 :0] current_r_addr;
|
input [RAw-1 :0] current_r_addr;
|
// the current endpoint address
|
// the current endpoint address
|
input [EAw-1 :0] current_e_addr;
|
input [EAw-1 :0] current_e_addr;
|
|
|
|
|
|
|
input start;
|
input start;
|
|
|
output reg done;
|
output reg done;
|
reg done_next;
|
reg done_next;
|
|
|
input [Dw-1 : 0] jtag_data_b;
|
input [Dw-1 : 0] jtag_data_b;
|
input [Aw-1 : 0] jtag_addr_b;
|
input [Aw-1 : 0] jtag_addr_b;
|
input jtag_we_b;
|
input jtag_we_b;
|
output [Dw-1 : 0] jtag_q_b;
|
output [Dw-1 : 0] jtag_q_b;
|
|
|
input [STATISw-1 : 0] statistic_jtag_addr_b;
|
input [STATISw-1 : 0] statistic_jtag_addr_b;
|
output reg [Dw-1 : 0] statistic_jtag_q_b;
|
output reg [Dw-1 : 0] statistic_jtag_q_b;
|
|
|
|
|
|
|
// NOC interfaces
|
// NOC interfaces
|
input smartflit_chanel_t chan_in;
|
input smartflit_chanel_t chan_in;
|
output smartflit_chanel_t chan_out;
|
output smartflit_chanel_t chan_out;
|
|
|
|
|
|
|
wire [Dw-1 : 0] q_a;
|
wire [Dw-1 : 0] q_a;
|
reg [Aw-1 : 0] addr_a,addr_a_next;
|
reg [Aw-1 : 0] addr_a,addr_a_next;
|
reg we_a;
|
reg we_a;
|
reg [Dw-1 : 0] data_a;
|
reg [Dw-1 : 0] data_a;
|
|
|
|
|
wire [PCK_CNTw-1 :0] pck_num_to_send_in;
|
wire [PCK_CNTw-1 :0] pck_num_to_send_in;
|
wire [RATIOw-1 :0] ratio,ratio_in;
|
wire [RATIOw-1 :0] ratio,ratio_in;
|
wire [PCK_SIZw-1 :0] pck_size_in;
|
wire [PCK_SIZw-1 :0] pck_size_in;
|
wire [MAX_EAw-1 :0] dest_e_in;
|
wire [MAX_EAw-1 :0] dest_e_in;
|
wire [MAX_Cw-1 :0] pck_class_in;
|
wire [MAX_Cw-1 :0] pck_class_in;
|
wire last_adr_in;
|
wire last_adr_in;
|
|
|
assign {pck_num_to_send_in,ratio_in, pck_size_in,dest_e_in, pck_class_in, last_adr_in}= q_a;
|
assign {pck_num_to_send_in,ratio_in, pck_size_in,dest_e_in, pck_class_in, last_adr_in}= q_a;
|
|
|
wire [EAw-1 :0] dest_e_addr = dest_e_in [EAw-1 :0];
|
wire [EAw-1 :0] dest_e_addr = dest_e_in [EAw-1 :0];
|
wire [Cw-1 :0] pck_class= pck_class_in[Cw-1 :0];
|
wire [Cw-1 :0] pck_class= pck_class_in[Cw-1 :0];
|
|
|
|
|
wire [CLK_CNTw-1 :0] time_stamp_h2t;
|
wire [CLK_CNTw-1 :0] time_stamp_h2t;
|
wire sent_done, update;
|
wire sent_done, update;
|
reg [ STATE_NUM-1 : 0] ps,ns;
|
reg [ STATE_NUM-1 : 0] ps,ns;
|
reg [63 : 0] total_pck_recieved,total_pck_recieved_next,total_pck_sent,total_pck_sent_next;
|
reg [63 : 0] total_pck_recieved,total_pck_recieved_next,total_pck_sent,total_pck_sent_next;
|
reg [63 : 0] total_latency_cnt,total_latency_cnt_next;
|
reg [63 : 0] total_latency_cnt,total_latency_cnt_next;
|
reg [31 : 0] ram_counter,ram_counter_next;
|
reg [31 : 0] ram_counter,ram_counter_next;
|
reg [PCK_CNTw-1 : 0] pck_number_sent,pck_number_sent_next;
|
reg [PCK_CNTw-1 : 0] pck_number_sent,pck_number_sent_next;
|
reg [CLK_CNTw-1 : 0] worst_latency,worst_latency_next;
|
reg [CLK_CNTw-1 : 0] worst_latency,worst_latency_next;
|
|
|
reg nvalid_dest,reset_pck_number_sent_old;
|
reg nvalid_dest,reset_pck_number_sent_old;
|
wire nvalid_dest_next= (current_e_addr==dest_e_addr && ps!=IDEAL && ps!=WAIT1);
|
wire nvalid_dest_next= (current_e_addr==dest_e_addr && ps!=IDEAL && ps!=WAIT1);
|
wire reset_pck_number_sent= ((pck_number_sent==pck_num_to_send_in) | nvalid_dest) & ~reset_pck_number_sent_old;
|
wire reset_pck_number_sent= ((pck_number_sent==pck_num_to_send_in) | nvalid_dest) & ~reset_pck_number_sent_old;
|
reg stop;
|
reg stop;
|
assign ratio=(ps==SEND_PCK)? ratio_in : {RATIOw{1'b0}};
|
assign ratio=(ps==SEND_PCK)? ratio_in : {RATIOw{1'b0}};
|
|
|
dual_port_ram #(
|
dual_port_ram #(
|
.Dw (Dw),
|
.Dw (Dw),
|
.Aw (Aw)
|
.Aw (Aw)
|
)
|
)
|
the_ram
|
the_ram
|
(
|
(
|
.clk (clk),
|
.clk (clk),
|
//port a
|
//port a
|
.data_a (data_a),
|
.data_a (data_a),
|
.addr_a (addr_a),
|
.addr_a (addr_a),
|
.we_a (we_a),
|
.we_a (we_a),
|
.q_a (q_a),
|
.q_a (q_a),
|
|
|
//port b connected to the jtag
|
//port b connected to the jtag
|
.data_b (jtag_data_b),
|
.data_b (jtag_data_b),
|
.addr_b (jtag_addr_b),
|
.addr_b (jtag_addr_b),
|
.we_b (jtag_we_b),
|
.we_b (jtag_we_b),
|
.q_b (jtag_q_b)
|
.q_b (jtag_q_b)
|
);
|
);
|
|
|
wire start_traffic;
|
wire start_traffic;
|
reg [3:0] counter;
|
reg [3:0] counter;
|
|
|
always @(posedge clk or posedge reset) begin
|
always @(posedge clk or posedge reset) begin
|
if(reset) counter <=4'd0;
|
if(reset) counter <=4'd0;
|
else begin
|
else begin
|
if(start) counter <=4'd1;
|
if(start) counter <=4'd1;
|
else if(counter> 4'd0 && counter<=4'b1111) counter <=counter+1'b1;
|
else if(counter> 4'd0 && counter<=4'b1111) counter <=counter+1'b1;
|
end
|
end
|
end
|
end
|
|
|
assign start_traffic = counter == 4'b1100; // delaied for 12 clock cycles
|
assign start_traffic = counter == 4'b1100; // delaied for 12 clock cycles
|
|
|
|
|
traffic_gen_top #(
|
traffic_gen_top #(
|
.MAX_RATIO(MAX_RATIO)
|
.MAX_RATIO(MAX_RATIO)
|
)
|
)
|
the_traffic_gen
|
the_traffic_gen
|
(
|
(
|
|
|
.reset(reset),
|
.reset(reset),
|
.clk(clk),
|
.clk(clk),
|
//input
|
//input
|
.ratio (ratio),
|
.ratio (ratio),
|
.start(start_traffic),
|
.start(start_traffic),
|
.stop(stop),
|
.stop(stop),
|
.pck_size_in(pck_size_in),
|
.pck_size_in(pck_size_in),
|
.current_e_addr(current_e_addr),
|
.current_e_addr(current_e_addr),
|
.dest_e_addr(dest_e_addr),
|
.dest_e_addr(dest_e_addr),
|
.pck_class_in(pck_class),
|
.pck_class_in(pck_class),
|
.init_weight({WEIGHTw{1'b0}}),
|
.init_weight({WEIGHTw{1'b0}}),
|
.report ( ),
|
.report ( ),
|
|
|
//output
|
//output
|
.update(update), // update the noc_analayzer
|
.update(update), // update the noc_analayzer
|
.src_e_addr( ),
|
.src_e_addr( ),
|
.pck_number( ),
|
.pck_number( ),
|
.sent_done(sent_done), // tail flit has been sent
|
.sent_done(sent_done), // tail flit has been sent
|
.hdr_flit_sent( ),
|
.hdr_flit_sent( ),
|
.distance( ),
|
.distance( ),
|
.pck_class_out( ),
|
.pck_class_out( ),
|
.time_stamp_h2h( ),
|
.time_stamp_h2h( ),
|
.time_stamp_h2t(time_stamp_h2t),
|
.time_stamp_h2t(time_stamp_h2t),
|
.flit_out_class(),
|
.flit_out_class(),
|
//noc
|
//noc
|
.chan_in(chan_in),
|
.chan_in(chan_in),
|
.chan_out(chan_out),
|
.chan_out(chan_out),
|
|
.mcast_dst_num_o()
|
|
|
|
|
);
|
);
|
|
|
always @ (*)begin
|
always @ (*)begin
|
case (statistic_jtag_addr_b)
|
case (statistic_jtag_addr_b)
|
SENT_PCK_ADDR: statistic_jtag_q_b= total_pck_sent;
|
SENT_PCK_ADDR: statistic_jtag_q_b= total_pck_sent;
|
RSVD_PCK_ADDR: statistic_jtag_q_b= total_pck_recieved;
|
RSVD_PCK_ADDR: statistic_jtag_q_b= total_pck_recieved;
|
TOTAL_LATENCY_ADDR: statistic_jtag_q_b= total_latency_cnt;
|
TOTAL_LATENCY_ADDR: statistic_jtag_q_b= total_latency_cnt;
|
WORST_LATENCY_ADDR: statistic_jtag_q_b= worst_latency;
|
WORST_LATENCY_ADDR: statistic_jtag_q_b= worst_latency;
|
default: statistic_jtag_q_b= worst_latency;
|
default: statistic_jtag_q_b= worst_latency;
|
endcase
|
endcase
|
end
|
end
|
|
|
|
|
|
|
|
|
always @ (*)begin
|
always @ (*)begin
|
ns=ps;
|
ns=ps;
|
addr_a_next = addr_a;
|
addr_a_next = addr_a;
|
pck_number_sent_next = pck_number_sent;
|
pck_number_sent_next = pck_number_sent;
|
done_next =done;
|
done_next =done;
|
total_latency_cnt_next = total_latency_cnt;
|
total_latency_cnt_next = total_latency_cnt;
|
worst_latency_next = worst_latency;
|
worst_latency_next = worst_latency;
|
total_pck_recieved_next = total_pck_recieved;
|
total_pck_recieved_next = total_pck_recieved;
|
total_pck_sent_next = total_pck_sent;
|
total_pck_sent_next = total_pck_sent;
|
ram_counter_next = ram_counter;
|
ram_counter_next = ram_counter;
|
data_a = total_pck_sent;
|
data_a = total_pck_sent;
|
we_a = 0;
|
we_a = 0;
|
stop=1'b0;
|
stop=1'b0;
|
|
|
if(update)begin
|
if(update)begin
|
total_latency_cnt_next = total_latency_cnt + time_stamp_h2t;
|
total_latency_cnt_next = total_latency_cnt + time_stamp_h2t;
|
if(time_stamp_h2t >worst_latency ) worst_latency_next=time_stamp_h2t;
|
if(time_stamp_h2t >worst_latency ) worst_latency_next=time_stamp_h2t;
|
total_pck_recieved_next =total_pck_recieved+1'b1;
|
total_pck_recieved_next =total_pck_recieved+1'b1;
|
end
|
end
|
|
|
if(sent_done)begin
|
if(sent_done)begin
|
pck_number_sent_next =pck_number_sent+1'b1;
|
pck_number_sent_next =pck_number_sent+1'b1;
|
total_pck_sent_next =total_pck_sent+1'b1;
|
total_pck_sent_next =total_pck_sent+1'b1;
|
end
|
end
|
|
|
|
|
case(ps)
|
case(ps)
|
IDEAL : begin
|
IDEAL : begin
|
done_next =1'b0;
|
done_next =1'b0;
|
addr_a_next =RAM_CNT_ADDR;
|
addr_a_next =RAM_CNT_ADDR;
|
ram_counter_next = q_a[31:0]; // first ram data shows how many times the RAM is needed to ne read
|
ram_counter_next = q_a[31:0]; // first ram data shows how many times the RAM is needed to ne read
|
if( start) begin
|
if( start) begin
|
addr_a_next=PATTERN_START_ADDR;
|
addr_a_next=PATTERN_START_ADDR;
|
ns= WAIT1;
|
ns= WAIT1;
|
end
|
end
|
|
|
end//IDEAL
|
end//IDEAL
|
WAIT1 : begin
|
WAIT1 : begin
|
ns= WAIT2;
|
ns= WAIT2;
|
|
|
end
|
end
|
WAIT2 : begin
|
WAIT2 : begin
|
ns= SEND_PCK;
|
ns= SEND_PCK;
|
|
|
end
|
end
|
SEND_PCK: begin
|
SEND_PCK: begin
|
if (reset_pck_number_sent) begin
|
if (reset_pck_number_sent) begin
|
pck_number_sent_next={PCK_CNTw{1'b0}};
|
pck_number_sent_next={PCK_CNTw{1'b0}};
|
if(last_adr_in)begin
|
if(last_adr_in)begin
|
if(ram_counter==0)begin
|
if(ram_counter==0)begin
|
ns = ASSET_DONE;// SAVE_SENT_PCK_NUM;
|
ns = ASSET_DONE;// SAVE_SENT_PCK_NUM;
|
//addr_a_next = SENT_PCK_ADDR;
|
//addr_a_next = SENT_PCK_ADDR;
|
end else addr_a_next = 1;
|
end else addr_a_next = 1;
|
ram_counter_next=ram_counter-1'b1;
|
ram_counter_next=ram_counter-1'b1;
|
end else begin
|
end else begin
|
addr_a_next=addr_a+1'b1;
|
addr_a_next=addr_a+1'b1;
|
|
|
end
|
end
|
|
|
end
|
end
|
|
|
|
|
|
|
|
|
|
|
end//SEND_PCk
|
end//SEND_PCk
|
/*
|
/*
|
SAVE_SENT_PCK_NUM: begin
|
SAVE_SENT_PCK_NUM: begin
|
data_a = total_pck_sent;
|
data_a = total_pck_sent;
|
we_a = 1;
|
we_a = 1;
|
addr_a_next =RSVD_PCK_ADDR ;
|
addr_a_next =RSVD_PCK_ADDR ;
|
ns= SAVE_RSVD_PCK_NUM;
|
ns= SAVE_RSVD_PCK_NUM;
|
|
|
end
|
end
|
SAVE_RSVD_PCK_NUM: begin
|
SAVE_RSVD_PCK_NUM: begin
|
data_a = total_pck_recieved;
|
data_a = total_pck_recieved;
|
addr_a_next =TOTAL_LATENCY_ADDR;
|
addr_a_next =TOTAL_LATENCY_ADDR;
|
we_a = 1;
|
we_a = 1;
|
ns= SAVE_TOTAL_LATENCY_NUM;
|
ns= SAVE_TOTAL_LATENCY_NUM;
|
|
|
|
|
end
|
end
|
SAVE_TOTAL_LATENCY_NUM: begin
|
SAVE_TOTAL_LATENCY_NUM: begin
|
data_a = total_latency_cnt;
|
data_a = total_latency_cnt;
|
addr_a_next =WORST_LATENCY_ADDR;
|
addr_a_next =WORST_LATENCY_ADDR;
|
we_a = 1;
|
we_a = 1;
|
ns=SAVE_WORST_LATENCY_NUM;
|
ns=SAVE_WORST_LATENCY_NUM;
|
|
|
|
|
end
|
end
|
SAVE_WORST_LATENCY_NUM:begin
|
SAVE_WORST_LATENCY_NUM:begin
|
data_a = worst_latency;
|
data_a = worst_latency;
|
we_a = 1;
|
we_a = 1;
|
ns= ASSET_DONE;
|
ns= ASSET_DONE;
|
end
|
end
|
*/
|
*/
|
ASSET_DONE: begin
|
ASSET_DONE: begin
|
done_next =1'b1;
|
done_next =1'b1;
|
stop=1'b1;
|
stop=1'b1;
|
end
|
end
|
endcase
|
endcase
|
end//always
|
end//always
|
|
|
|
|
|
|
always @(posedge clk) begin
|
always @(posedge clk) begin
|
if(reset)begin
|
if(reset)begin
|
ps <= IDEAL;
|
ps <= IDEAL;
|
addr_a <={Aw{1'b0}};
|
addr_a <={Aw{1'b0}};
|
pck_number_sent<={PCK_CNTw{1'b0}};
|
pck_number_sent<={PCK_CNTw{1'b0}};
|
done<=1'b0;
|
done<=1'b0;
|
total_latency_cnt<=64'd0;
|
total_latency_cnt<=64'd0;
|
total_pck_recieved<=64'd0;
|
total_pck_recieved<=64'd0;
|
total_pck_sent<=64'd0;
|
total_pck_sent<=64'd0;
|
ram_counter<= 32'd0;
|
ram_counter<= 32'd0;
|
nvalid_dest<=1'b0;
|
nvalid_dest<=1'b0;
|
reset_pck_number_sent_old<=1'b0;
|
reset_pck_number_sent_old<=1'b0;
|
worst_latency<={CLK_CNTw{1'b0}};
|
worst_latency<={CLK_CNTw{1'b0}};
|
end else begin
|
end else begin
|
ps <= ns;
|
ps <= ns;
|
addr_a<= addr_a_next;
|
addr_a<= addr_a_next;
|
pck_number_sent<= pck_number_sent_next;
|
pck_number_sent<= pck_number_sent_next;
|
done <=done_next;
|
done <=done_next;
|
total_latency_cnt<= total_latency_cnt_next;
|
total_latency_cnt<= total_latency_cnt_next;
|
total_pck_recieved<= total_pck_recieved_next;
|
total_pck_recieved<= total_pck_recieved_next;
|
total_pck_sent<= total_pck_sent_next;
|
total_pck_sent<= total_pck_sent_next;
|
ram_counter<= ram_counter_next;
|
ram_counter<= ram_counter_next;
|
nvalid_dest<=nvalid_dest_next;
|
nvalid_dest<=nvalid_dest_next;
|
reset_pck_number_sent_old<=reset_pck_number_sent;
|
reset_pck_number_sent_old<=reset_pck_number_sent;
|
worst_latency<=worst_latency_next;
|
worst_latency<=worst_latency_next;
|
end
|
end
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end
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end
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endmodule
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endmodule
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/***********************
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/***********************
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*
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*
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* jtag_emulator_controller
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* jtag_emulator_controller
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*
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*
|
***********************/
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***********************/
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|
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|
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module jtag_emulator_controller #(
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module jtag_emulator_controller #(
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parameter VJTAG_INDEX=125,
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parameter VJTAG_INDEX=125,
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parameter Dw=32,
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parameter Dw=32,
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parameter Aw=32
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parameter Aw=32
|
|
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)(
|
)(
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clk,
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clk,
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reset,
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reset,
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//wishbone master interface signals
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//wishbone master interface signals
|
|
|
dat_o,
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dat_o,
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addr_o,
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addr_o,
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we_o,
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we_o,
|
q_i
|
q_i
|
);
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);
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|
|
//IO declaration
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//IO declaration
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input reset,clk;
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input reset,clk;
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|
|
|
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//wishbone master interface signals
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//wishbone master interface signals
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|
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output [Dw-1 : 0] dat_o;
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output [Dw-1 : 0] dat_o;
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output [Aw-1 : 0] addr_o;
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output [Aw-1 : 0] addr_o;
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output we_o;
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output we_o;
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input [Dw-1 : 0] q_i;
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input [Dw-1 : 0] q_i;
|
|
|
|
|
|
|
localparam STATE_NUM=3,
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localparam STATE_NUM=3,
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IDEAL =1,
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IDEAL =1,
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WB_WR_DATA=2,
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WB_WR_DATA=2,
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WB_RD_DATA=4;
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WB_RD_DATA=4;
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|
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reg [STATE_NUM-1 : 0] ps,ns;
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reg [STATE_NUM-1 : 0] ps,ns;
|
|
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wire [Dw-1 :0] data_out, data_in;
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wire [Dw-1 :0] data_out, data_in;
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wire wb_wr_addr_en, wb_wr_data_en, wb_rd_data_en;
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wire wb_wr_addr_en, wb_wr_data_en, wb_rd_data_en;
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reg wr_mem_en, wb_cap_rd;
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reg wr_mem_en, wb_cap_rd;
|
|
|
reg [Aw-1 : 0] wb_addr,wb_addr_next;
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reg [Aw-1 : 0] wb_addr,wb_addr_next;
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reg [Dw-1 : 0] wb_wr_data,wb_rd_data;
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reg [Dw-1 : 0] wb_wr_data,wb_rd_data;
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reg wb_addr_inc;
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reg wb_addr_inc;
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|
|
|
|
|
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assign we_o = wr_mem_en;
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assign we_o = wr_mem_en;
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assign dat_o = wb_wr_data;
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assign dat_o = wb_wr_data;
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assign addr_o = wb_addr;
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assign addr_o = wb_addr;
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assign data_in = wb_rd_data;
|
assign data_in = wb_rd_data;
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//vjtag vjtag signals declaration
|
//vjtag vjtag signals declaration
|
|
|
|
|
localparam VJ_DW= (Dw > Aw)? Dw : Aw;
|
localparam VJ_DW= (Dw > Aw)? Dw : Aw;
|
|
|
|
|
vjtag_ctrl #(
|
vjtag_ctrl #(
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.DW(VJ_DW),
|
.DW(VJ_DW),
|
.VJTAG_INDEX(VJTAG_INDEX)
|
.VJTAG_INDEX(VJTAG_INDEX)
|
)
|
)
|
vjtag_ctrl_inst
|
vjtag_ctrl_inst
|
(
|
(
|
.clk(clk),
|
.clk(clk),
|
.reset(reset),
|
.reset(reset),
|
.data_out(data_out),
|
.data_out(data_out),
|
.data_in(data_in),
|
.data_in(data_in),
|
.wb_wr_addr_en(wb_wr_addr_en),
|
.wb_wr_addr_en(wb_wr_addr_en),
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.wb_wr_data_en(wb_wr_data_en),
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.wb_wr_data_en(wb_wr_data_en),
|
.wb_rd_data_en(wb_rd_data_en),
|
.wb_rd_data_en(wb_rd_data_en),
|
.status_i( )
|
.status_i( )
|
);
|
);
|
|
|
|
|
|
|
always @(posedge clk or posedge reset) begin
|
always @(posedge clk or posedge reset) begin
|
if(reset) begin
|
if(reset) begin
|
wb_addr <= {Aw{1'b0}};
|
wb_addr <= {Aw{1'b0}};
|
wb_wr_data <= {Dw{1'b0}};
|
wb_wr_data <= {Dw{1'b0}};
|
ps <= IDEAL;
|
ps <= IDEAL;
|
end else begin
|
end else begin
|
wb_addr <= wb_addr_next;
|
wb_addr <= wb_addr_next;
|
ps <= ns;
|
ps <= ns;
|
if(wb_wr_data_en) wb_wr_data <= data_out;
|
if(wb_wr_data_en) wb_wr_data <= data_out;
|
if(wb_cap_rd) wb_rd_data <= q_i;
|
if(wb_cap_rd) wb_rd_data <= q_i;
|
end
|
end
|
end
|
end
|
|
|
|
|
always @(*)begin
|
always @(*)begin
|
wb_addr_next= wb_addr;
|
wb_addr_next= wb_addr;
|
if(wb_wr_addr_en) wb_addr_next = data_out [Aw-1 : 0];
|
if(wb_wr_addr_en) wb_addr_next = data_out [Aw-1 : 0];
|
else if (wb_addr_inc) wb_addr_next = wb_addr + 1'b1;
|
else if (wb_addr_inc) wb_addr_next = wb_addr + 1'b1;
|
end
|
end
|
|
|
|
|
|
|
always @(*)begin
|
always @(*)begin
|
ns=ps;
|
ns=ps;
|
wr_mem_en =1'b0;
|
wr_mem_en =1'b0;
|
|
|
wb_addr_inc=1'b0;
|
wb_addr_inc=1'b0;
|
wb_cap_rd=1'b0;
|
wb_cap_rd=1'b0;
|
case(ps)
|
case(ps)
|
IDEAL : begin
|
IDEAL : begin
|
if(wb_wr_data_en) ns= WB_WR_DATA;
|
if(wb_wr_data_en) ns= WB_WR_DATA;
|
if(wb_rd_data_en) ns= WB_RD_DATA;
|
if(wb_rd_data_en) ns= WB_RD_DATA;
|
end
|
end
|
WB_WR_DATA: begin
|
WB_WR_DATA: begin
|
wr_mem_en =1'b1;
|
wr_mem_en =1'b1;
|
ns=IDEAL;
|
ns=IDEAL;
|
wb_addr_inc=1'b1;
|
wb_addr_inc=1'b1;
|
|
|
end
|
end
|
WB_RD_DATA: begin
|
WB_RD_DATA: begin
|
|
|
wb_cap_rd=1'b1;
|
wb_cap_rd=1'b1;
|
ns=IDEAL;
|
ns=IDEAL;
|
//wb_addr_inc=1'b1;
|
//wb_addr_inc=1'b1;
|
|
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
|
|
//assign led={wb_addr[7:0], wb_wr_data[7:0]};
|
//assign led={wb_addr[7:0], wb_wr_data[7:0]};
|
|
|
endmodule
|
endmodule
|
|
|
|
|
|
|
|
|
|
|