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`include "system_conf.v"
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`include "system_conf.v"
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`include "lm32_include.v"
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`include "lm32_include.v"
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module lm32 #(
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module lm32 #(
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parameter INTR_NUM=32,
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parameter INTR_NUM=32,
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parameter CFG_PL_MULTIPLY= "ENABLED", //"ENABLED","DISABLED"
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parameter CFG_PL_MULTIPLY= "ENABLED", //"ENABLED","DISABLED"
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parameter CFG_PL_BARREL_SHIFT= "ENABLED",
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parameter CFG_PL_BARREL_SHIFT= "ENABLED",
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parameter CFG_SIGN_EXTEND="ENABLED",
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parameter CFG_SIGN_EXTEND="ENABLED",
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parameter CFG_MC_DIVIDE="DISABLED"
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parameter CFG_MC_DIVIDE="DISABLED"
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)(
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)(
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// ----- Inputs -------
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// ----- Inputs -------
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clk_i,
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clk_i,
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rst_i,
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rst_i,
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interrupt,
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interrupt,
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en_i,
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// Instruction Wishbone master
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// Instruction Wishbone master
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I_DAT_I,
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I_DAT_I,
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I_ACK_I,
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I_ACK_I,
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I_ERR_I,
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I_ERR_I,
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I_RTY_I,
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I_RTY_I,
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I_DAT_O,
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I_DAT_O,
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I_ADR_O,
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I_ADR_O,
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I_CYC_O,
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I_CYC_O,
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I_SEL_O,
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I_SEL_O,
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I_STB_O,
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I_STB_O,
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I_WE_O,
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I_WE_O,
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I_CTI_O,
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I_CTI_O,
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//I_LOCK_O,
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//I_LOCK_O,
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I_BTE_O,
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I_BTE_O,
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// Data Wishbone master
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// Data Wishbone master
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D_DAT_I,
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D_DAT_I,
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D_ACK_I,
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D_ACK_I,
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D_ERR_I,
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D_ERR_I,
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D_RTY_I,
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D_RTY_I,
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D_DAT_O,
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D_DAT_O,
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D_ADR_O,
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D_ADR_O,
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D_CYC_O,
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D_CYC_O,
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D_SEL_O,
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D_SEL_O,
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D_STB_O,
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D_STB_O,
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D_WE_O,
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D_WE_O,
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D_CTI_O,
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D_CTI_O,
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//D_LOCK_O,
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//D_LOCK_O,
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D_BTE_O
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D_BTE_O
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);
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);
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input clk_i; // Clock
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input clk_i; // Clock
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input rst_i; // Reset
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input rst_i; // Reset
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input en_i;
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wire reset;
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assign reset = rst_i | ~ en_i;
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//`ifdef CFG_INTERRUPTS_ENABLED
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//`ifdef CFG_INTERRUPTS_ENABLED
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input [`LM32_INTERRUPT_RNG] interrupt; // Interrupt pins
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input [`LM32_INTERRUPT_RNG] interrupt; // Interrupt pins
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//`endif
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//`endif
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`ifdef CFG_USER_ENABLED
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`ifdef CFG_USER_ENABLED
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input [`LM32_WORD_RNG] user_result; // User-defined instruction result
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input [`LM32_WORD_RNG] user_result; // User-defined instruction result
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input user_complete; // Indicates the user-defined instruction result is valid
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input user_complete; // Indicates the user-defined instruction result is valid
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`endif
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`endif
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`ifdef CFG_IWB_ENABLED
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`ifdef CFG_IWB_ENABLED
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input [`LM32_WORD_RNG] I_DAT_I; // Instruction Wishbone interface read data
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input [`LM32_WORD_RNG] I_DAT_I; // Instruction Wishbone interface read data
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input I_ACK_I; // Instruction Wishbone interface acknowledgement
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input I_ACK_I; // Instruction Wishbone interface acknowledgement
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input I_ERR_I; // Instruction Wishbone interface error
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input I_ERR_I; // Instruction Wishbone interface error
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input I_RTY_I; // Instruction Wishbone interface retry
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input I_RTY_I; // Instruction Wishbone interface retry
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`endif
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`endif
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`ifdef CFG_USER_ENABLED
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`ifdef CFG_USER_ENABLED
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output user_valid; // Indicates that user_opcode and user_operand_* are valid
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output user_valid; // Indicates that user_opcode and user_operand_* are valid
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wire user_valid;
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wire user_valid;
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output [`LM32_USER_OPCODE_RNG] user_opcode; // User-defined instruction opcode
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output [`LM32_USER_OPCODE_RNG] user_opcode; // User-defined instruction opcode
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reg [`LM32_USER_OPCODE_RNG] user_opcode;
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reg [`LM32_USER_OPCODE_RNG] user_opcode;
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output [`LM32_WORD_RNG] user_operand_0; // First operand for user-defined instruction
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output [`LM32_WORD_RNG] user_operand_0; // First operand for user-defined instruction
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wire [`LM32_WORD_RNG] user_operand_0;
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wire [`LM32_WORD_RNG] user_operand_0;
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output [`LM32_WORD_RNG] user_operand_1; // Second operand for user-defined instruction
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output [`LM32_WORD_RNG] user_operand_1; // Second operand for user-defined instruction
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wire [`LM32_WORD_RNG] user_operand_1;
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wire [`LM32_WORD_RNG] user_operand_1;
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`endif
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`endif
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`ifdef CFG_IWB_ENABLED
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`ifdef CFG_IWB_ENABLED
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output [`LM32_WORD_RNG] I_DAT_O; // Instruction Wishbone interface write data
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output [`LM32_WORD_RNG] I_DAT_O; // Instruction Wishbone interface write data
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wire [`LM32_WORD_RNG] I_DAT_O;
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wire [`LM32_WORD_RNG] I_DAT_O;
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output [`LM32_WORD_RNG] I_ADR_O; // Instruction Wishbone interface address
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output [`LM32_WORD_RNG] I_ADR_O; // Instruction Wishbone interface address
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wire [`LM32_WORD_RNG] I_ADR_O;
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wire [`LM32_WORD_RNG] I_ADR_O;
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output I_CYC_O; // Instruction Wishbone interface cycle
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output I_CYC_O; // Instruction Wishbone interface cycle
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wire I_CYC_O;
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wire I_CYC_O;
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output [`LM32_BYTE_SELECT_RNG] I_SEL_O; // Instruction Wishbone interface byte select
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output [`LM32_BYTE_SELECT_RNG] I_SEL_O; // Instruction Wishbone interface byte select
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wire [`LM32_BYTE_SELECT_RNG] I_SEL_O;
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wire [`LM32_BYTE_SELECT_RNG] I_SEL_O;
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output I_STB_O; // Instruction Wishbone interface strobe
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output I_STB_O; // Instruction Wishbone interface strobe
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wire I_STB_O;
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wire I_STB_O;
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output I_WE_O; // Instruction Wishbone interface write enable
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output I_WE_O; // Instruction Wishbone interface write enable
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wire I_WE_O;
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wire I_WE_O;
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output [`LM32_CTYPE_RNG] I_CTI_O; // Instruction Wishbone interface cycle type
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output [`LM32_CTYPE_RNG] I_CTI_O; // Instruction Wishbone interface cycle type
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wire [`LM32_CTYPE_RNG] I_CTI_O;
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wire [`LM32_CTYPE_RNG] I_CTI_O;
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//output I_LOCK_O; // Instruction Wishbone interface lock bus
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//output I_LOCK_O; // Instruction Wishbone interface lock bus
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//wire I_LOCK_O;
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//wire I_LOCK_O;
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output [`LM32_BTYPE_RNG] I_BTE_O; // Instruction Wishbone interface burst type
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output [`LM32_BTYPE_RNG] I_BTE_O; // Instruction Wishbone interface burst type
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wire [`LM32_BTYPE_RNG] I_BTE_O;
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wire [`LM32_BTYPE_RNG] I_BTE_O;
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`endif
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`endif
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input [`LM32_WORD_RNG] D_DAT_I; // Data Wishbone interface read data
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input [`LM32_WORD_RNG] D_DAT_I; // Data Wishbone interface read data
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input D_ACK_I; // Data Wishbone interface acknowledgement
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input D_ACK_I; // Data Wishbone interface acknowledgement
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input D_ERR_I; // Data Wishbone interface error
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input D_ERR_I; // Data Wishbone interface error
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input D_RTY_I; // Data Wishbone interface retry
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input D_RTY_I; // Data Wishbone interface retry
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output [`LM32_WORD_RNG] D_DAT_O; // Data Wishbone interface write data
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output [`LM32_WORD_RNG] D_DAT_O; // Data Wishbone interface write data
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wire [`LM32_WORD_RNG] D_DAT_O;
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wire [`LM32_WORD_RNG] D_DAT_O;
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output [`LM32_WORD_RNG] D_ADR_O; // Data Wishbone interface address
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output [`LM32_WORD_RNG] D_ADR_O; // Data Wishbone interface address
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wire [`LM32_WORD_RNG] D_ADR_O;
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wire [`LM32_WORD_RNG] D_ADR_O;
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output D_CYC_O; // Data Wishbone interface cycle
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output D_CYC_O; // Data Wishbone interface cycle
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wire D_CYC_O;
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wire D_CYC_O;
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output [`LM32_BYTE_SELECT_RNG] D_SEL_O; // Data Wishbone interface byte select
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output [`LM32_BYTE_SELECT_RNG] D_SEL_O; // Data Wishbone interface byte select
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wire [`LM32_BYTE_SELECT_RNG] D_SEL_O;
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wire [`LM32_BYTE_SELECT_RNG] D_SEL_O;
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output D_STB_O; // Data Wishbone interface strobe
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output D_STB_O; // Data Wishbone interface strobe
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wire D_STB_O;
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wire D_STB_O;
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output D_WE_O; // Data Wishbone interface write enable
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output D_WE_O; // Data Wishbone interface write enable
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wire D_WE_O;
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wire D_WE_O;
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output [`LM32_CTYPE_RNG] D_CTI_O; // Data Wishbone interface cycle type
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output [`LM32_CTYPE_RNG] D_CTI_O; // Data Wishbone interface cycle type
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wire [`LM32_CTYPE_RNG] D_CTI_O;
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wire [`LM32_CTYPE_RNG] D_CTI_O;
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//output D_LOCK_O; // Date Wishbone interface lock bus
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//output D_LOCK_O; // Date Wishbone interface lock bus
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//wire D_LOCK_O;
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//wire D_LOCK_O;
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output [`LM32_BTYPE_RNG] D_BTE_O; // Data Wishbone interface burst type
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output [`LM32_BTYPE_RNG] D_BTE_O; // Data Wishbone interface burst type
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wire [`LM32_BTYPE_RNG] D_BTE_O;
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wire [`LM32_BTYPE_RNG] D_BTE_O;
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wire [31:0] iadr_o,dadr_o;
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wire [31:0] iadr_o,dadr_o;
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lm32_top the_lm32_top(
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lm32_top the_lm32_top(
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.clk_i(clk_i),
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.clk_i(clk_i),
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.rst_i(rst_i),
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.rst_i(reset ),
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.interrupt_n(~interrupt),
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.interrupt_n(~interrupt),
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.I_DAT_I(I_DAT_I),
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.I_DAT_I(I_DAT_I),
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.I_ACK_I(I_ACK_I),
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.I_ACK_I(I_ACK_I),
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.I_ERR_I(I_ERR_I),
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.I_ERR_I(I_ERR_I),
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.I_RTY_I(I_RTY_I),
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.I_RTY_I(I_RTY_I),
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.D_DAT_I(D_DAT_I),
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.D_DAT_I(D_DAT_I),
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.D_ACK_I(D_ACK_I),
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.D_ACK_I(D_ACK_I),
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.D_ERR_I(D_ERR_I),
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.D_ERR_I(D_ERR_I),
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.D_RTY_I(D_RTY_I),
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.D_RTY_I(D_RTY_I),
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.I_DAT_O(I_DAT_O),
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.I_DAT_O(I_DAT_O),
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.I_ADR_O(iadr_o),
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.I_ADR_O(iadr_o),
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.I_CYC_O(I_CYC_O),
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.I_CYC_O(I_CYC_O),
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.I_SEL_O(I_SEL_O),
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.I_SEL_O(I_SEL_O),
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.I_STB_O(I_STB_O),
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.I_STB_O(I_STB_O),
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.I_WE_O(I_WE_O),
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.I_WE_O(I_WE_O),
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.I_CTI_O(I_CTI_O),
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.I_CTI_O(I_CTI_O),
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.I_LOCK_O(),
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.I_LOCK_O(),
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.I_BTE_O(I_BTE_O),
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.I_BTE_O(I_BTE_O),
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.D_DAT_O(D_DAT_O),
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.D_DAT_O(D_DAT_O),
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.D_ADR_O(dadr_o),
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.D_ADR_O(dadr_o),
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.D_CYC_O(D_CYC_O),
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.D_CYC_O(D_CYC_O),
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.D_SEL_O(D_SEL_O),
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.D_SEL_O(D_SEL_O),
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.D_STB_O(D_STB_O),
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.D_STB_O(D_STB_O),
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.D_WE_O(D_WE_O),
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.D_WE_O(D_WE_O),
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.D_CTI_O(D_CTI_O),
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.D_CTI_O(D_CTI_O),
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.D_LOCK_O(),
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.D_LOCK_O(),
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.D_BTE_O(D_BTE_O)
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.D_BTE_O(D_BTE_O)
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);
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);
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assign D_ADR_O= {2'b00,dadr_o[31:2]};
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assign D_ADR_O= {2'b00,dadr_o[31:2]};
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assign I_ADR_O= {2'b00,iadr_o[31:2]};
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assign I_ADR_O= {2'b00,iadr_o[31:2]};
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// assign iwb_dat_o = 0;
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// assign iwb_dat_o = 0;
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// assign iwb_tag_o = 3'b000; // clasic wishbone without burst
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// assign iwb_tag_o = 3'b000; // clasic wishbone without burst
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// assign dwb_tag_o = 3'b000; // clasic wishbone without burst
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// assign dwb_tag_o = 3'b000; // clasic wishbone without burst
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// assign iwb_adr_o[31:30] = 2'b00;
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// assign iwb_adr_o[31:30] = 2'b00;
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// assign dwb_adr_o[31:30] = 2'b00;
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// assign dwb_adr_o[31:30] = 2'b00;
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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